- 12 Apr, 2022 38 commits
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Daniele Palmas authored
Add the following Telit FN980 composition: 0x1057: tty, adb, rmnet, tty, tty, tty, tty, tty Signed-off-by:
Daniele Palmas <dnlplm@gmail.com> Acked-by:
Bjørn Mork <bjorn@mork.no> Link: https://lore.kernel.org/r/20220411135943.4067264-1-dnlplm@gmail.comSigned-off-by:
Paolo Abeni <pabeni@redhat.com>
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Paolo Abeni authored
Martin Habets says: ==================== sfc: Remove some global definitions These are some small cleanups to remove definitions that need not be defined in .h files. ==================== Link: https://lore.kernel.org/r/164967635861.17602.16525009567130361754.stgit@palantir17.mph.netSigned-off-by:
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Martin Habets authored
The strings are only used in efx_common.c so the definitions can be static in there. Signed-off-by:
Martin Habets <habetsm.xilinx@gmail.com> Signed-off-by:
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Martin Habets authored
It is defined both in efx.h and tx_common.h. Remove the definition in efx.h. Signed-off-by:
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Martin Habets authored
This means we can remove them from efx_channel.h and avoid naming conflicts later. efx_channel_dummy_op_void() cannot be static as it is used in ef100_nic.c. Signed-off-by:
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Paolo Abeni authored
Russell King says: ==================== net: dsa: mt7530: updates for phylink changes This revised series is a partial conversion of the mt7530 DSA driver to the modern phylink infrastructure. This driver has some exceptional cases which prevent - at the moment - its full conversion (particularly with the Autoneg bit) to using phylink_generic_validate(). Patch 1 fixes the incorrect test highlighted in the first RFC series. Patch 2 fixes the incorrect assumption that RGMII is unable to support 1000BASE-X. Patch 3 populates the supported_interfaces for each port Patch 4 removes the interface checks that become unnecessary as a result of patch 3. Patch 5 removes use of phylink_helper_basex_speed() which is no longer required by phylink. Patch 6 becomes possible after patch 5, only indicating the ethtool modes that can be supported with a particular interface mode - this involves removing some modes and adding others as per phylink documentation. Patch 7 switches the driver to use phylink_get_linkmodes(), which moves the driver as close as we can to phylink_generic_validate() due to the Autoneg bit issue mentioned above. Patch 8 converts the driver to the phylink pcs support, removing a bunch of driver private indirected methods. We include TRGMII as a PCS even though strictly TRGMII does not have a PCS. This is convenient to allow the change in patch 9 to be made. Patch 9 moves the special autoneg handling to the PCS validate method, which means we can convert the MAC side to the generic validator. Patch 10 marks the driver as non-legacy. The series was posted on 23 February, and a ping sent on 3 March, but no feedback has been received. The previous posting also received no feedback on the actual patches either. v2: - fix build issue in patch 5 - add Marek's tested-by drivers/net/dsa/mt7530.c | 330 +++++++++++++++++++++-------------------------- drivers/net/dsa/mt7530.h | 26 ++-- 2 files changed, 159 insertions(+), 197 deletions(-) ==================== Link: https://lore.kernel.org/r/YlP4vGKVrlIJUUHK@shell.armlinux.org.ukSigned-off-by:
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Russell King (Oracle) authored
The mt7530 driver does not make use of the speed, duplex, pause or advertisement in its phylink_mac_config() implementation, so it can be marked as a non-legacy driver. Tested-by:
Marek Behún <kabel@kernel.org> Signed-off-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Russell King (Oracle) authored
Move the autoneg bit handling to the PCS validation, which allows us to get rid of mt753x_phylink_validate() and rely on the default phylink_generic_validate() implementation for the MAC side. Tested-by:
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Russell King (Oracle) authored
Partially convert the mt7530 driver to use phylink's PCS support. This is a partial implementation as we don't move anything into the pcs_config method yet - this driver supports SGMII or 1000BASE-X without in-band. Tested-by:
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Russell King (Oracle) authored
Switch mt7530 to use phylink_get_linkmodes() to generate the ethtool linkmodes that can be supported. We are unable to use the generic helper for this as pause modes are dependent on the interface as the Autoneg bit depends on the interface mode. Tested-by:
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Russell King (Oracle) authored
Now that mt7530 is not using the basex helper, it becomes unnecessary to indicate support for both 1000baseX and 2500baseX when one of the 803.3z PHY interface modes is being selected. Ensure that the driver indicates only those linkmodes that can actually be supported by the PHY interface mode. Tested-by:
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Russell King (Oracle) authored
Now that we have a better method to select SFP interface modes, we no longer need to use phylink_helper_basex_speed() in a driver's validation function. Tested-by:
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Russell King (Oracle) authored
As phylink checks the interface mode against the supported_interfaces bitmap, we no longer need to validate the interface mode, nor handle PHY_INTERFACE_MODE_NA in the validation function. Remove these to simplify the implementation. Tested-by:
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Russell King (Oracle) authored
Populate the supported interfaces and MAC capabilities for mt7530, mt7531 and mt7621 DSA switches. Filling this in will enable phylink to pre-check the PHY interface mode against the the supported interfaces bitmap prior to calling the validate function, and will eventually allow us to convert to using the generic validation. Tested-by:
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Russell King (Oracle) authored
When using an external PHY connected using RGMII to mt7531 port 5, the PHY can be used to used support 1000BASE-X connections. Moreover, if 1000BASE-T is supported, then we should allow 1000BASE-X as well, since which are supported is a property of the PHY. Therefore, it makes no sense to exclude this from the linkmodes when 1000BASE-T is supported. Fixes: c288575f ("net: dsa: mt7530: Add the support of MT7531 switch") Tested-by:
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Paolo Abeni authored
Joachim Wiberg says: ==================== net: bridge: add support for host l2 mdb entries Fix to an obvious omissions for layer-2 host mdb entries, this v2 adds the missing selftest and some minor style fixes. Note: this patch revealed some worrying problems in how the bridge forwards unknown BUM traffic and also how unknown multicast is forwarded when a IP multicast router is known, which a another (RFC) patch series intend to address. That series will build on this selftest, hence the name of the test. v2: - Add braces to other if/else clauses (Jakub) - Add selftest to verify add/del of mac/ipv4/ipv6 mdb entries (Jakub) ==================== Link: https://lore.kernel.org/r/20220411084054.298807-1-troglobit@gmail.comSigned-off-by: -
Joachim Wiberg authored
Boiler plate for testing static mdb entries. This first test verifies adding and removing host mdb entries for all supported types: IPv4, IPv6, and MAC multicast. Signed-off-by:
Joachim Wiberg <troglobit@gmail.com> Signed-off-by:
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Joachim Wiberg authored
This patch expands on the earlier work on layer-2 mdb entries by adding support for host entries. Due to the fact that host joined entries do not have any flag field, we infer the permanent flag when reporting the entries to userspace, which otherwise would be listed as 'temp'. Before patch: ~# bridge mdb add dev br0 port br0 grp 01:00:00:c0:ff:ee permanent Error: bridge: Flags are not allowed for host groups. ~# bridge mdb add dev br0 port br0 grp 01:00:00:c0:ff:ee Error: bridge: Only permanent L2 entries allowed. After patch: ~# bridge mdb add dev br0 port br0 grp 01:00:00:c0:ff:ee permanent ~# bridge mdb show dev br0 port br0 grp 01:00:00:c0:ff:ee permanent vid 1 Signed-off-by:Nikolay Aleksandrov <razor@blackwall.org> Signed-off-by:
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Lv Ruyi authored
There are some spelling mistakes in the comment. Fix it. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Lv Ruyi <lv.ruyi@zte.com.cn> Link: https://lore.kernel.org/r/20220411032546.2517628-1-lv.ruyi@zte.com.cnSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
Minghao Chi <chi.minghao@zte.com.cn> Reviewed-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220411013812.2517212-1-chi.minghao@zte.com.cnSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Haowen Bai authored
fix warning reported by smatch: 251 drivers/net/ethernet/sfc/ef10.c:2259 efx_ef10_tx_tso_desc() warn: assigning (-208) to unsigned variable 'ip_tot_len' Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Acked-by:
Edward Cree <ecree.xilinx@gmail.com> Link: https://lore.kernel.org/r/1649640757-30041-1-git-send-email-baihaowen@meizu.comSigned-off-by:
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Arınç ÜNAL authored
Add BR_HAIRPIN_MODE, BR_ISOLATED and BR_MULTICAST_TO_UNICAST port flags to BR_PORT_FLAGS_HW_OFFLOAD so that switchdev drivers which have an offloaded data plane have a chance to reject these bridge port flags if they don't support them yet. It makes the code path go through the SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS driver handlers, which return -EINVAL for everything they don't recognize. For drivers that don't catch SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS at all, switchdev will return -EOPNOTSUPP for those which is then ignored, but those are in the minority. Signed-off-by:
Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by:
Ido Schimmel <idosch@nvidia.com> Reviewed-by:
Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20220410134227.18810-1-arinc.unal@arinc9.comSigned-off-by:
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Jakub Kicinski authored
Horatiu Vultur says: ==================== net: lan966x: Add support for FDMA Currently when injecting or extracting a frame from CPU, the frame is given to the HW each word at a time. There is another way to inject/extract frames from CPU using FDMA(Frame Direct Memory Access). In this way the entire frame is given to the HW. This improves both RX and TX bitrate. ==================== Tested-by: Michael Walle <michael@walle.cc> # on kontron-kswitch-d10 Link: https://lore.kernel.org/r/20220408070357.559899-1-horatiu.vultur@microchip.comSigned-off-by:
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Horatiu Vultur authored
When changing the MTU, it is required to change also the size of the DBs. In case those frames will arrive to CPU. Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by:
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Horatiu Vultur authored
Ethernet frames can be extracted or injected to or from the device's DDR memory. There is one channel for injection and one channel for extraction. Each of these channels contain a linked list of DCBs which contains DB. The DCB contains only 1 DB for both the injection and extraction. Each DB contains a frame. Every time when a frame is received or transmitted an interrupt is generated. It is not possible to use both the FDMA and the manual injection/extraction of the frames. Therefore the FDMA has priority over the manual because of better performance values. FDMA: iperf -c 192.168.1.1 [ 5] 0.00-10.02 sec 420 MBytes 352 Mbits/sec 0 sender [ 5] 0.00-10.03 sec 420 MBytes 351 Mbits/sec receiver iperf -c 192.168.1.1 -R [ 5] 0.00-10.01 sec 528 MBytes 442 Mbits/sec 0 sender [ 5] 0.00-10.00 sec 524 MBytes 440 Mbits/sec receiver Manual: iperf -c 192.168.1.1 [ 5] 0.00-10.02 sec 93.8 MBytes 78.5 Mbits/sec 0 sender [ 5] 0.00-10.03 sec 93.8 MBytes 78.4 Mbits/sec receiver ipers -c 192.168.1.1 -R [ 5] 0.00-10.03 sec 121 MBytes 101 Mbits/sec 0 sender [ 5] 0.00-10.01 sec 118 MBytes 99.0 Mbits/sec receiver Signed-off-by:
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Horatiu Vultur authored
Expose the following functions 'lan966x_hw_offload', 'lan966x_ifh_get_src_port' and 'lan966x_ifh_get_timestamp' in lan966x_main.h so they can be accessed by FDMA. Signed-off-by:
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Horatiu Vultur authored
Add the registers that are used to configure the FDMA. Signed-off-by:
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Jonathan Neuschäfer authored
Fix a doubled word in the comment above xgmac_poll. Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20220409182147.2509788-1-j.neuschaefer@gmx.netSigned-off-by:
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YueHaibing authored
If PHYLINK is n, build fails: drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_link_ksettings': am65-cpsw-ethtool.c:(.text+0x118): undefined reference to `phylink_ethtool_ksettings_set' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_get_link_ksettings': am65-cpsw-ethtool.c:(.text+0x138): undefined reference to `phylink_ethtool_ksettings_get' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_eee': am65-cpsw-ethtool.c:(.text+0x158): undefined reference to `phylink_ethtool_set_eee' Select PHYLINK for TI_K3_AM65_CPSW_NUSS to fix this. Fixes: e8609e69 ("net: ethernet: ti: am65-cpsw: Convert to PHYLINK") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
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https://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linuxJakub Kicinski authored
Leon Romanovsky says: ==================== Mellanox shared branch that includes: * Removal of FPGA TLS code https://lore.kernel.org/all/cover.1649073691.git.leonro@nvidia.com Mellanox INNOVA TLS cards are EOL in May, 2018 [1]. As such, the code is unmaintained, untested and not in-use by any upstream/distro oriented customers. In order to reduce code complexity, drop the kernel code, clean build config options and delete useless kTLS vs. TLS separation. [1] https://network.nvidia.com/related-docs/eol/LCR-000286.pdf * Removal of FPGA IPsec code https://lore.kernel.org/all/cover.1649232994.git.leonro@nvidia.com Together with FPGA TLS, the IPsec went to EOL state in the November of 2019 [1]. Exactly like FPGA TLS, no active customers exist for this upstream code and all the complexity around that area can be deleted. [2] https://network.nvidia.com/related-docs/eol/LCR-000535.pdf * Fix to undefined behavior from Borislav https://lore.kernel.org/all/20220405151517.29753-11-bp@alien8.de * 'mlx5-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux: (23 commits) net/mlx5: Remove not-implemented IPsec capabilities net/mlx5: Remove ipsec_ops function table net/mlx5: Reduce kconfig complexity while building crypto support net/mlx5: Move IPsec file to relevant directory net/mlx5: Remove not-needed IPsec config net/mlx5: Align flow steering allocation namespace to common style net/mlx5: Unify device IPsec capabilities check net/mlx5: Remove useless IPsec device checks net/mlx5: Remove ipsec vs. ipsec offload file separation RDMA/core: Delete IPsec flow action logic from the core RDMA/mlx5: Drop crypto flow steering API RDMA/mlx5: Delete never supported IPsec flow action net/mlx5: Remove FPGA ipsec specific statistics net/mlx5: Remove XFRM no_trailer flag net/mlx5: Remove not-used IDA field from IPsec struct net/mlx5: Delete metadata handling logic net/mlx5_fpga: Drop INNOVA IPsec support IB/mlx5: Fix undefined behavior due to shift overflowing the constant net/mlx5: Cleanup kTLS function names and their exposure net/mlx5: Remove tls vs. ktls separation as it is the same ... ==================== Link: https://lore.kernel.org/r/20220409055303.1223644-1-leon@kernel.orgSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Haiyang Zhang authored
Handle XDP_REDIRECT action in netvsc driver. Also, transparently pass ndo_xdp_xmit to VF when available. Signed-off-by:
Haiyang Zhang <haiyangz@microsoft.com> Link: https://lore.kernel.org/r/1649362894-20077-1-git-send-email-haiyangz@microsoft.comSigned-off-by:
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Jakub Kicinski authored
Guillaume Nault says: ==================== ipv4: Convert several tos fields to dscp_t Continue the work started with commit a410a0cf ("ipv6: Define dscp_t and stop taking ECN bits into account in fib6-rules") and convert more structure fields and variables to dscp_t. This series focuses on struct fib_rt_info, struct fib_entry_notifier_info and their users (networking drivers). The purpose of dscp_t is to ensure that ECN bits don't influence IP route lookups. It does so by ensuring that dscp_t variables have the ECN bits cleared. Notes: * This series is entirely about type annotation and isn't supposed to have any user visible effect. * The first two patches have to introduce a few dsfield <-> dscp conversions in the affected drivers, but those are then removed when converting the internal driver structures (patches 3-5). In the end, drivers don't have to handle any conversion. ==================== Link: https://lore.kernel.org/r/cover.1649445279.git.gnault@redhat.comSigned-off-by:
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Guillaume Nault authored
Use the new dscp_t type to replace the kern_tos field of struct prestera_kern_fib_cache. This ensures ECN bits are ignored and makes it compatible with the dscp fields of struct fib_entry_notifier_info and struct fib_rt_info. This also allows sparse to flag potential incorrect uses of DSCP and ECN bits. Signed-off-by:
Guillaume Nault <gnault@redhat.com> Reviewed-by:
Yevhen Orlov <yevhen.orlov@plvision.eu> Signed-off-by:
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Guillaume Nault authored
Use the new dscp_t type to replace the tos field of struct mlxsw_sp_fib4_entry. This ensures ECN bits are ignored and makes it compatible with the dscp fields of fib_entry_notifier_info and fib_rt_info. This also allows sparse to flag potential incorrect uses of DSCP and ECN bits. Signed-off-by:
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Guillaume Nault authored
Use the new dscp_t type to replace the tos field of struct nsim_fib4_rt. This ensures ECN bits are ignored and makes it compatible with the dscp fields of struct fib_entry_notifier_info and struct fib_rt_info. This also allows sparse to flag potential incorrect uses of DSCP and ECN bits. Signed-off-by:
David Ahern <dsahern@kernel.org> Signed-off-by:
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Guillaume Nault authored
Use the new dscp_t type to replace the tos field of struct fib_entry_notifier_info. This ensures ECN bits are ignored and makes it compatible with the dscp field of struct fib_rt_info. This also allows sparse to flag potential incorrect uses of DSCP and ECN bits. Signed-off-by:
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Guillaume Nault authored
Use the new dscp_t type to replace the tos field of struct fib_rt_info. This ensures ECN bits are ignored and makes it compatible with the fa_dscp field of struct fib_alias. This also allows sparse to flag potential incorrect uses of DSCP and ECN bits. Signed-off-by:
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- 11 Apr, 2022 2 commits
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Grygorii Strashko authored
Since commit 1771afd4 ("net: cpsw: avoid alignment faults by taking NET_IP_ALIGN into account") the TI CPSW driver was switched to use correct define CPSW_HEADROOM_NA to avoid alignment faults, but there are two places left where CPSW_HEADROOM is still used (without causing issues). Hence, completely drop CPSW_HEADROOM define and use CPSW_HEADROOM_NA everywhere to avoid further mistakes in code. Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Mat Martineau says: ==================== mptcp: Miscellaneous changes for 5.19 Four separate groups of patches here: Patch 1 optimizes flag checking when releasing mptcp socket locks. Patches 2 and 3 update the packet scheduler when subflow priorities change. Patch 4 adds some pernet helper functions for MPTCP. Patches 5-8 add diag support for MPTCP listeners, including a selftest. ==================== Signed-off-by:
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