- 26 Sep, 2023 9 commits
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Swarup Laxman Kotiaklapudi authored
Fix kernel-doc warnings discovered in AMD gpu display driver. Fixes these warnings: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'overlap_only' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_gain_mode' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'background_color_bpc' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'top_gain' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_inside_gain' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_outside_gain' not described in 'mpcc_blnd_cfg'. Tested-by:
Randy Dunlap <rdunlap@infradead.org> Acked-by:
Swarup Laxman Kotiaklapudi <swarupkotikalapudi@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Philip Yang authored
On GFX v9.4.3 dGPU, applications have random timeout failure when XNACK on, dmesg log has "amdgpu: IH soft ring buffer overflow 0x900, 0x900", because dGPU mode has 272 cam entries. After increasing IH soft ring to 512 entries, no more IH soft ring overflow message and application passed. Fixes: bf80d34b ("drm/amdgpu: Increase soft IH ring size") Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Lijo Lazar authored
On a full device reset, PSP FW gets unloaded. Hence restore the partition mode by placing a new request. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Acked-by:
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Aric Cyr authored
This version brings along the following: - Use optc32 instead of optc30 in DC - Optimize OLED T7 delay - Multiple fixes for MST, register mas, and others - Update driver and IPS interop - Improve z8 watermark mask - DCN35 updates - Enable replay for DCN35 - Temporarily disable clock gating Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
There are multiple parts of the code that DC does not use anymore, and this commit drops those dead codes. Tested-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Muhammad Ahmed authored
Enable DCN low mem power by default. Tested-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by:
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Muhammad Ahmed authored
Update with extended blank Vstartup adjustment for replay. Tested-by:
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Ovidiu Bunea authored
Change DC to use optc32, which uses REG_UPDATE instead of REG_SET. REG_SET clears OTG_H_TIMING_DIV_MODE_MANUAL which must be set to 1 in some specific HDMI configurations. Tested-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by:
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Agustin Gutierrez authored
[Why] Driver doesn't need T7 delay for OLED panels, since it doesn't control power sequence. [How] This delay can be skipped to optimize resume times. Tested-by:
Swapnil Patel <swapnil.patel@amd.com> Acked-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by:
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- 20 Sep, 2023 31 commits
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Philip Yang authored
The validated_once flag is not used after the prefault was removed, The prefault was needed to ensure validate all system memory pages at least once before mapping or migrating the range to GPU. Signed-off-by:
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Lijo Lazar authored
Include subrevision and variant fileds also to IP version. Signed-off-by:
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Tao Zhou authored
Print channel index for UMC v12. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Xiaogang Chen authored
We do not need free dma address array of svm_range each time we do dma unmap for pages in svm_range as we can reuse the same array. Only free it when free svm_range. Separate these two operations and use them accordingly. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
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Lijo Lazar authored
Selectively updating feature mask is not supported in SMU v13.0.6. Remove the callback corresponding to that. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Acked-by:
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Lijo Lazar authored
Instead of neglecting fractional part, round the Q10 format values in SMU v13.0.6 metrics table. Signed-off-by:
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Sathishkumar S authored
update the query to return the number of functional instances where there is more than an instance of the requested type and for others continue to return one. v2: count must reflect the actual number of engines (Alex) v3: fix wrong number of engines for vcn (Alex) Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Stanley.Yang authored
It should first check block ras obj whether be set, it should return 0 directly if block ras obj or hw_ops is not set. If block doesn't support RAS just return 0 is fine. Changed from V1: return 0 directly if block ras obj or hw ops is not set Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Vignesh Chander authored
Host handles PG. Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Signed-off-by:
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YuBiao Wang authored
Directly use tbo's start address will miss the domain start offset. Need to use gpu_offset instead. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
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Aric Cyr authored
Acked-by:
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Anthony Koo authored
- Add new IPS ALLOW masks - Add new Replay power configuration options Tested-by:
Anthony Koo <anthony.koo@amd.com> Signed-off-by:
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Muhammad Ahmed authored
MST now recognizes both connected displays Tested-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Charlene Liu authored
Fix some non-initialized register mask and update golden setting. Tested-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
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Roman Li authored
Enable the display replay feature for DCN35. Tested-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Gabe Teeger authored
Add a config option to disable odm dispclk optimization for debug purpose. Tested-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Muhammad Ahmed authored
Disable IPS by default till it is ready. Tested-by:
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Sung Joon Kim authored
[why] Currently, driver is not aware if IPS is supported. After PMFW helps implement new message query functionality, driver will set IPS capability flag. [how] Create new SMU hook function to query IPS capability. Based on the cap, set appropriate flags to false for power-gating purposes. This will avoid keeping SMU busy and offloading tasks to DMUB/driver. Tested-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
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Duncan Ma authored
[Why] Two issues fixed: 1. Currently, driver does not allow idle prior to PSR entry. Once PSR1+IPS is enabled, there is intermittent hang due to DCN access from IrqMgr during IPS2. 2. Driver is sending multiple commands to PMFW and dmcub to exit IPS even during IPS0. [How] 1. Set driver allow optimization prior to entering PSR mode with the condition for eDP display only. Unregister all interrupts before allowing driver idle and re-register interrupts when exiting from idle. This will prevent IrqMgr to access DCN during IPS2. 2. Block sending PMFW and dmcub exit low power state commands when driver is not in idle state. Tested-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
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Charlene Liu authored
Correct z8_watermark mask from 16bit to 20bit. Also, do not set dcn35 dprefclk in clk_mgr_construct. Tested-by:
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Artem Grishin authored
[Why] The STREAM_MAPPER_CONTROL register offset was left uninitialized, causing warning in the driver log at runtime [How] A temporary solution to add it into dcn35_create_resource_pool. [TODO] Remove duplication between SE_DCN35_REG_LIST_RI in dcn35_resource.h and SE_DCN35_REG_LIST in dcn35_dio_stream_encoder.h Tested-by:
Artem Grishin <artem.grishin@amd.com> Signed-off-by:
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Wenjing Liu authored
Pipe resource interfaces were changed. Tested-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Mustapha Ghaddar authored
For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design Tested-by:
George Shen <george.shen@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by:
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Sung-huai Wang authored
set_static_screen_control has been updated for DCN3 series. Update it for DCN35. Tested-by:
Sung-huai Wang <danny.wang@amd.com> Signed-off-by:
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Sung Joon Kim authored
Call to immediate_disable_crtc was not checked before calling, exposing a potential null pointer hang. Tested-by:
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Muhammad Ahmed authored
PMFW ungate this feature, this can be enabled now Tested-by:
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Qingqing Zhuo authored
Add DCN 35 case for dc_clk_mgr_create. Tested-by:
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Charlene Liu authored
Add z8 watermarks to struct for DCN35. Tested-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Duncan Ma authored
[Why] Some of the stream encoder registers have register offset address 0. It is causing no display in some scenarios due to DIG_FE was not setup correctly and was not enabled. [How] Fix stream encoder register define list. Tested-by:
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Hamza Mahfooz authored
On eDP we can receive invalid modes from dm_update_crtc_state() for entirely new streams for which drm_mode_set_crtcinfo() shouldn't be called on. So, instead of calling drm_mode_set_crtcinfo() from within create_stream_for_sink() we can instead call it from amdgpu_dm_connector_mode_valid(). Since, we are guaranteed to only call drm_mode_set_crtcinfo() for valid modes from that function (invalid modes are rejected by that callback) and that is the only user of create_validate_stream_for_sink() that we need to call drm_mode_set_crtcinfo() for (as before commit cb841d27 ("drm/amd/display: Always pass connector_state to stream validation"), that is the only place where create_validate_stream_for_sink()'s dm_state was NULL). Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2693 Fixes: cb841d27 ("drm/amd/display: Always pass connector_state to stream validation") Tested-by:
Mark Broadworth <mark.broadworth@amd.com> Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Charlene Liu authored
Temporarily disable dchubbub clock gating, registers: .DISPCLK_R_DCHUBBUB_GATE_DIS .DCFCLK_R_DCHUBBUB_GATE_DIS need to follow up with sequence issue. Tested-by:
Leo Chen <sanchuan.chen@amd.com> Acked-by:
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