1. 27 Jul, 2020 38 commits
  2. 23 Jul, 2020 2 commits
    • Alex Deucher's avatar
      drm/amdgpu/powerplay: add some documentation about memory clock · ccda42a4
      Alex Deucher authored
      We expose the actual memory controller clock rate in Linux,
      not the effective memory clock of the DRAMs.  To translate
      it, it follows the following formula:
      
      Clock conversion (Mhz):
      HBM: effective_memory_clock = memory_controller_clock * 1
      G5:  effective_memory_clock = memory_controller_clock * 1
      G6:  effective_memory_clock = memory_controller_clock * 2
      
      DRAM data rate (MT/s):
      HBM: effective_memory_clock * 2 = data_rate
      G5:  effective_memory_clock * 4 = data_rate
      G6:  effective_memory_clock * 8 = data_rate
      
      Bandwidth (MB/s):
      data_rate * vram_bit_width / 8 = memory_bandwidth
      
      Some examples:
      G5 on RX460:
      memory_controller_clock = 1750 Mhz
      effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
      data rate = 1750 * 4 = 7000 MT/s
      memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
      
      G6 on RX5600:
      memory_controller_clock = 900 Mhz
      effective_memory_clock = 900 Mhz * 2 = 1800 Mhz
      data rate = 1800 * 8 = 14400 MT/s
      memory_bandwidth = 14400 * 192 bits / 8 = 345600 MB/s
      Acked-by: default avatarEvan Quan <evan.quan@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      ccda42a4
    • Li Heng's avatar
      drm/amdgpu: Remove redundant NULL check · cc0e7ff8
      Li Heng authored
      Fix below warnings reported by coccicheck:
      ./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:557:2-7: WARNING: NULL check before some freeing functions is not needed.
      
      Fixes: 4d55b0dd ("drm/amd/display: Add DCN3 CLK_MGR")
      Signed-off-by: default avatarLi Heng <liheng40@huawei.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      cc0e7ff8