- 21 Aug, 2009 2 commits
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Paul Mundt authored
This does a bit of rework for making the cache flushers SMP-aware. The function pointer-based flushers are renamed to local variants with the exported interface being commonly implemented and wrapping as necessary. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
All CPU-specific overloads are done at runtime now, so this common header can go away and simply be folded back in to asm/ version. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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- 20 Aug, 2009 2 commits
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Paul Mundt authored
When get_mmu_context() runs out of new ASIDs it flushes the TLB and wraps around. Despite the fact the ASIDs are tracked per-CPU, a global TLB flush was being used. Switch this over to a local one, as matches the intent. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
mapping is unused on the SMP build, trigger a build error. Move it under the ifdef. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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- 19 Aug, 2009 3 commits
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Paul Mundt authored
This fixes up the clockevents broadcasting code as detailed in commit ee348d5a ("[ARM] realview: fix broadcast tick support"). This saves us from having to do strange ordering things with the broadcast clockevent device, relying on the rating instead. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
This fixes up the build when caches are disabled, by linking in all of the cache routines directly. This paves the way for splitting out separate I and D cache disabling, similar to what sh64 had, and which we want for SH-X3 anyways. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Conflicts: arch/sh/kernel/Makefile_64
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- 18 Aug, 2009 6 commits
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Kuninori Morimoto authored
While most platforms implement LED banks in sets of 8/16/32, some use different configurations. This adds a LED mask to the heartbeat platform data to allow platforms to constrain the bitmap, which is otherwise derived from the register size. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Kuninori Morimoto authored
This patch updates the FRQCRA.IFC divisor values for SH7724. Despite not being initially documented, the / 3 mode is also support for the IFC division. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Kuninori Morimoto authored
FLLFRQ setting is needed to use correct PLL clock for kfr2409. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Matt Fleming authored
save_regs contains an SR modification without an irqflags annotation, which resulted in a missing TRACE_IRQS_OFF in the interrupt exception path on SH-3/SH4. I've also moved the TRACE_IRQS_OFF/ON annotation when returning from the interrupt to just before we call __restore_all. This seems like the most logical place to put this because the annotation is for when we restore the SR register so we should delay the annotation until as last as possible. We were also missing a TRACE_IRQS_OFF in resume_kernel when CONFIG_PREEMPT is enabled. The end result is that this fixes up the lockdep engine debugging support with CONFIG_PREEMPT enabled on all SH-3/4 parts. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm authored
This patch adds "SuperH Mobile Standby Mode [SF]" to the list of cpuidle sleep modes. If the software latency requirements from cpuidle are met together with fulfilled hardware requirements then deep sleep modes can be entered. Tested on sh7722 and sh7724 with "Sleep Mode", "Sleep Mode + SF" and "Software Standby Mode + SF" together with a multimedia work load and flood ping without packet drop. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm authored
This patch updates the exception handling in the sleep code for SuperH Mobile. With the patch applied the sleep code always rewrites the VBR and resumes from the exception vector, re-initializes hardware and jumps straight to the original interrupt vector. Tested on sh7722 and sh7724 with "Sleep Mode", "Sleep Mode + SF" and "Software Standby Mode + SF" with CONFIG_SUSPEND. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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- 16 Aug, 2009 2 commits
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Matt Fleming authored
Also, remove the "fix" to DW_CFA_def_cfa_register where we reset the frame's cfa_offset to 0. This action is incorrect when handling DW_CFA_def_cfa_register as the DWARF spec specifically states that the previous contents of cfa_offset should be used with the new register. The reason that I thought cfa_offset should be reset to 0 was because it was being assigned a bogus value prior to executing the DW_CFA_def_cfa_register op. It turns out that the bogus cfa_offset value came from interpreting .cfi_escape pseudo-ops (those used by the GNU extensions) as CFA_DW_def_cfa ops. Signed-off-by: Matt Fleming <matt@console-pimps.org>
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Matt Fleming authored
The previous hack for calculating the return address for the first frame we unwind (dwarf_unwinder_dump) didn't always work. The problem was that it assumed once it read the rule for calculating the return address, there would be no new rules for calculating it. This isn't true because the way in which the CFA is calculated can change as you progress through a function and the return address is figured out using the CFA. Therefore, the way to calculate the return address can change. So, instead of using some offset from the beginning of dwarf_unwind_stack which is just a flakey approach, and instead of executing instructions from the FDE until the return address is setup, we now figure out the pc in dwarf_unwind_stack() just before we call dwarf_cfa_execute_insns(). Signed-off-by: Matt Fleming <matt@console-pimps.org>
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- 15 Aug, 2009 25 commits
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Paul Mundt authored
Now that there is sufficient shared infrastructure, merge the Makefiles. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
This uses the BITS export as per x86 in order to allow the same Makefile to be used. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Now that the SH-5 code is more or less behaving with the new cacheflush interface, wire up the initialization code. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
These will be handled through the shared cache interface instead, and they are presently undefined anyways. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
The caches enabled case needs more work, but is presently broken regardless, so this can be done incrementally. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
This is superfluous, as the default CPU type and family are already established by the initial cpuinfo definition. Given that we are still able to probe for the CPU family even if we are not able to detect the subtype, it's preferable to let the probing code fill out what it can and leave the rest. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
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Magnus Damm authored
This patch updates the SuperH Mobile sleep assembly code with support for DBSC memory controller found in the sh7724 processor. Without this fix the memory hooked up to the sh7724 processor will never enter self-refresh mode before suspending to ram. The effect of this is that the memory contents most likeley will be lost upon resume which may or may not be what you want. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm authored
This patch updates the Solution Engine 7724 board code to use in-SoC KEYSC resources for the keyboard platform device. Using the in-SoC key scan controller fixes a crash-during-resume issue. Without this patch the KEYSC hardware block located in the board specific FPGA is used together with an external IRQ which is routed through the FPGA and handled by some board specific demux code. This board specific FPGA interrupt code does not implement desc->set_wake() so the enable_irq_wake() call in the sh_keysc driver will fail at suspend-to-ram time and the disable_irq_wake() will bomb out when resuming. Changing the platform data to use the in-SoC KEYSC hardware makes the se7724 board support code less special which is a good thing. Also, the board specific KEYSC pin setup code selects in-SoC pin functions already which makes the current FPGA platform device data look like a typo. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm authored
This patch updates the SuperH CMT driver with suspend and resume callbacks for the suspend-to-ram case. This patch stops the CMT channel at suspend time to avoid unwanted wake up events. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Magnus Damm authored
This patch updates the SuperH Mobile LCDC driver to skip over disabled channels. Without this patch suspend-to-ram operation will crash if deferred io is enabled. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
This paves the way for allowing individual CPUs to overload the individual flushing routines that they care about without having to depend on weak aliases. SH-4 is converted over initially, as it wires up pretty much everything. The majority of the other CPUs will simply use the default no-op implementation with their own region flushers wired up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
We use flush_cache_page() outright in copy_to_user_page(), and nothing else needs it, so just kill it off. SH-5 still defines its own version, but that too will go away in the same fashion once it converts over. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
All of the flush_dcache_mmap_lock()/flush_dcache_mmap_unlock() definitions are identical across all CPUs, so just provide them generically in asm/cacheflush.h. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
flush_dcache_all() is used internally by the SH-4 cache code, it is not part of the exported cache API, so make it static and don't export it. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
This migrates the alias computation and printing of probed cache parameters from the SH-4 code to the shared cpu_cache_init(). This permits other platforms with aliases to make use of the same probe logic without having to roll their own, and also produces consistent output regardless of platform. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
This provides a central point for CPU cache initialization routines. This replaces the antiquated p3_cache_init() method, which the vast majority of CPUs never cared about. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
This adds a family member to struct sh_cpuinfo, which allows us to fall back more on the probe routines to work out what sort of subtype we are running on. This will be used by the CPU cache initialization code in order to first do family-level initialization, followed by subtype-level optimizations. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
These were previous littered around tlb-nommu.c and pg-nommu.c, though at this point there are more stubs than are strictly TLB or page op related, so just consolidate them in a single nommu.c. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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