1. 26 Feb, 2009 2 commits
    • Paul Mackerras's avatar
      perfcounters: fix a few minor cleanliness issues · f3dfd265
      Paul Mackerras authored
      This fixes three issues noticed by Arnd Bergmann:
      
      - Add #ifdef __KERNEL__ and move some things around in perf_counter.h
        to make sure only the bits that userspace needs are exported to
        userspace.
      
      - Use __u64, __s64, __u32 types in the structs exported to userspace
        rather than u64, s64, u32.
      
      - Make the sys_perf_counter_open syscall available to the SPUs on
        Cell platforms.
      
      And one issue that I noticed in looking at the code again:
      
      - Wrap the perf_counter_open syscall with SYSCALL_DEFINE4 so we get
        the proper handling of int arguments on ppc64 (and some other 64-bit
        architectures).
      Reported-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      f3dfd265
    • Paul Mackerras's avatar
      perfcounters/powerpc: Add support for POWER5 processors · 742bd95b
      Paul Mackerras authored
      This adds the back-end for the PMU on the POWER5 processor.  This knows
      how to use the fixed-function PMC5 and PMC6 (instructions completed and
      run cycles).  Unlike POWER6, PMC5/6 obey the freeze conditions and can
      generate interrupts, so their use doesn't impose any extra restrictions.
      
      POWER5+ is different and is not supported by this patch.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      742bd95b
  2. 23 Feb, 2009 1 commit
    • Paul Mackerras's avatar
      perfcounters/powerpc: Make exclude_kernel bit work on Apple G5 processors · d095cd46
      Paul Mackerras authored
      Currently, setting hw_event.exclude_kernel does nothing on the PPC970
      variants used in Apple G5 machines, because they have the HV (hypervisor)
      bit in the MSR forced to 1, so as far as the PMU is concerned, the
      kernel runs in hypervisor mode.  Thus we have to use the MMCR0_FCHV
      (freeze counters in hypervisor mode) bit rather than the MMCR0_FCS
      (freeze counters in supervisor mode) bit.
      
      This checks the MSR.HV bit at startup, and if it is set, we set the
      freeze_counters_kernel variable to MMCR0_FCHV (it was initialized to
      MMCR0_FCS).  We then use that whenever we need to exclude kernel events.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      d095cd46
  3. 17 Feb, 2009 27 commits
  4. 16 Feb, 2009 8 commits
  5. 15 Feb, 2009 2 commits