- 25 Oct, 2016 40 commits
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Tom St Denis authored
Tested by reading tile/clk bits during load/idle. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Tom St Denis authored
This patch enables detecting VCE/UVD PG features and fixes the UVD powergate function. Tested on a Tonga (by reading UVD tile/clk bits during playback/idle). Signed-off-by:
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Christian König authored
Far less CPU cycles needed for this approach. v2: fix typo Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Frank Min authored
for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling. Signed-off-by:
Frank Min <Frank.Min@amd.com> Reviewed-by:
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Monk Liu authored
we found some MEC ucode leads to IB test fail or even ring test fail if Jump Table of it is not start in FW bo with page aligned address, fixed by always make JT address page aligned. we don't need to patch JT2 for MEC2, because for VI, MEC2 is a copy of MEC1, thus when converting fw_type for MEC_JT2 we just return MEC1,hw can use the same JT for both MEC1 & MEC2. above two change fixed some ring/ib test failure issue for some version of MEC ucode. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Monk Liu authored
for sriov, SMC need MEC_STORAGE reserved in fw bo. Signed-off-by:
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Frank Min authored
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Frank Min authored
for GTT memory SMC can only access it within PF space, which is not used for SRIOV case, thus for SRIOV case, we let SMC use FB space for ucode bo. Signed-off-by:
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Frank Min authored
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Monk Liu authored
for VI smc, index_0 to index_8 are all not safe, they may used by BIOS/FW, and index_11 is reserved only for driver. Signed-off-by:
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Frank Min authored
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Baoyou Xie authored
We get a few warnings when building kernel with W=1: drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smumgr.c:162:5: warning: no previous prototype for 'fiji_setup_pwr_virus' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/fiji_smc.c:2052:5: warning: no previous prototype for 'fiji_program_mem_timing_parameters' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/polaris10_smumgr.c:175:5: warning: no previous prototype for 'polaris10_avfs_event_mgr' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning: no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:92:26: warning: no previous prototype for 'cast_phw_smu7_power_state' [-Wmissing-prototypes] .... In fact, these functions are only used in the file in which they are declared and don't need a declaration, but can be made static. So this patch marks these functions with 'static'. Acked-by:
Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by:
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Baoyou Xie authored
We get 4 warnings when building kernel with W=1: drivers/gpu/drm/radeon/si.c:7850:5: warning: no previous prototype for 'si_vce_send_vcepll_ctlreq' [-Wmissing-prototypes] drivers/gpu/drm/radeon/radeon_dp_mst.c:226:21: warning: no previous prototype for 'radeon_mst_best_encoder' [-Wmissing-prototypes] drivers/gpu/drm/radeon/radeon_dp_mst.c:344:26: warning: no previous prototype for 'radeon_mst_find_connector' [-Wmissing-prototypes] drivers/gpu/drm/radeon/radeon_dp_mst.c:600:6: warning: no previous prototype for 'radeon_dp_mst_encoder_destroy' [-Wmissing-prototypes] In fact, these functions are only used in the file in which they are declared and don't need a declaration, but can be made static. So this patch marks these functions with 'static'. Reviewed-by:
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Baoyou Xie authored
We get a few warnings when building kernel with W=1: drivers/gpu/drm/radeon/radeon_clocks.c:35:10: warning: no previous prototype for 'radeon_legacy_get_engine_clock' [-Wmissing-prototypes] drivers/gpu/drm/radeon/atombios_encoders.c:75:1: warning: no previous prototype for 'atombios_get_backlight_level' [-Wmissing-prototypes] drivers/gpu/drm/radeon/r600_cs.c:2268:5: warning: no previous prototype for 'r600_cs_parse' [-Wmissing-prototypes] drivers/gpu/drm/radeon/evergreen_cs.c:2671:5: warning: no previous prototype for 'evergreen_cs_parse' [-Wmissing-prototypes] .... In fact, these functions are declared in drivers/gpu/drm/radeon/radeon_asic.h, so this patch adds missing header dependencies. Reviewed-by:
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Junwei Zhang authored
Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Junwei Zhang authored
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Christian König authored
Split VRAM allocations into 4MB blocks. v2: fix typo in comment, some suggested cleanups v3: document how to disable the feature, fix rebase issue Signed-off-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Tested-by:
Mike Lothian <mike@fireburn.co.uk> Signed-off-by:
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Christian König authored
This allows us to move scattered buffers around. v2: fix a couple of typos, handle scattered to scattered moves as well. Signed-off-by:
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Christian König authored
This allows us to map scattered VRAM BOs to the VMs. v2: fix offset handling, use pfn instead of offset, fix PAGE_SIZE != AMDGPU_GPU_PAGE_SIZE case Signed-off-by: -
Christian König authored
Otherwise the new VM code becomes confused. Signed-off-by:
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Christian König authored
Split VRAM won't have a valid offset, so just set an explicit limit when the flag is given to trigger reallocation if necessary. Signed-off-by:
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Christian König authored
Add a flag noting that a BO must be created using linear VRAM and set this flag on all in kernel users where appropriate. Hopefully I haven't missed anything. v2: add it in a few more places, fix CPU mapping. v3: rename to VRAM_CONTIGUOUS, fix typo in CS code. Signed-off-by:
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Junwei Zhang authored
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Junwei Zhang authored
Signed-off-by:
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Alex Deucher authored
Not used currently. Reviewed-by:
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Alex Deucher authored
No need to hard code the entire register to just set/clear one bit. Reviewed-by:
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Alex Deucher authored
Use an address offset like other dce code. Reviewed-by:
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Alex Deucher authored
use the hpd enum directly as an index Reviewed-by:
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Alex Deucher authored
No need to hard code the entire register to just set/clear one bit. Reviewed-by:
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Alex Deucher authored
use the hpd enum directly as an index Reviewed-by:
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Alex Deucher authored
Use an address offset like other dce code. Reviewed-by:
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Emily Deng authored
Enable multi crtcs for virtual display, user can set the number of crtcs by amdgpu module parameter virtual_display. v2: make timers per crtc v3: agd: simplify implementation Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-By:
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Alex Deucher authored
to match the other functions in that file. Reviewed-By:
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Alex Deucher authored
This reverts commit 16925c92. This is no longer necessary. Reviewed-By:
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Alex Deucher authored
No need to emulate all of the stuff for real hw. v2: warning fix Reviewed-By:
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Alex Deucher authored
We handle the virtual interrupts from a timer so no need to try an look like we are handling IV ring events. Reviewed-By:
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Alex Deucher authored
Virtual crtcs interrupts do not show up in the IV ring, so it will never be called. Reviewed-By:
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Alex Deucher authored
Never used. Reviewed-By:
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Alex Deucher authored
No need to ack non-existent interrupts. Reviewed-By:
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Alex Deucher authored
disable the real dce hw if the asic supports dce. Reviewed-By:
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