- 11 Jan, 2023 40 commits
-
-
Johan Hovold authored
Enable the eDP display on MDSS0 DP3, including backlight control. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111133128.31813-1-johan+linaro@kernel.org
-
Bjorn Andersson authored
The SA8295P ADP has, among other interfaces, six MiniDP connectors which are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3. Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers, DP PHYs and link them all together. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
-
Bjorn Andersson authored
The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes and link it together with the backlight control. Signed-off-by:
-
Bjorn Andersson authored
Define the display clock controllers, the MDSS instances, the DP phys and connect these together. Signed-off-by:
-
Bjorn Andersson authored
This reverts commit 92ad27fb, as this was applied to the wrong branch and causes merge conflicts.
-
Dmitry Baryshkov authored
14nm DSI PHY has the only supply, vcca. Drop the extra vdda-supply. Fixes: 5a134c94 ("arm64: dts: qcom: msm8996: add support for oneplus3(t)") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
-
Marijn Suijten authored
Tama has four GPIO-wired keys: two for camera focus and shutter / snapshot, and two more for volume up and down. As per the comment these used to not work because the necessary pin bias was missing, which is now set via pinctrl on pm8998_gpios. The missing bias has also been added to the existing volume down button, which receives a node name and label cleanup at the same time to be more consistent with other DTS and the newly added buttons. Its deprecated gpio-key,wakeup property has also been replaced with wakeup-source. Note that volume up is also available through the usual PON RESIN node, but unlike other platforms only triggers when the power button is held down at the same time making it unsuitable to serve as KEY_VOLUMEUP. Fixes: 30a7f99b ("arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)") Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
-
Dmitry Baryshkov authored
Drop the #clock-cells (probably a leftover from the times before the DP PHY split) Fixes: eaac4e55 ("arm64: dts: qcom: sdm845: add displayport node") Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
-
Konrad Dybcio authored
Feed GCC and SDHC_2 with the RPM XO instead of the fixed-clock one. Signed-off-by:
-
Manivannan Sadhasivam authored
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs received from endpoint devices to the CPU using GIC-ITS MSI controller. Add support for it. Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the msi-map-mask of 0xff00, all the 32 devices under these two busses can share the same Device ID. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. It should be noted that the MSIs for BDF (1:0.0) only works with Device ID of 0x5980 and 0x5a00. Hence, the IDs are swapped. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # Xperia 1 IV (WCN6855) Signed-off-by:
-
Krzysztof Kozlowski authored
Add missingh whitespace between node name/label and opening {. Signed-off-by: -
Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by:
-
Krzysztof Kozlowski authored
The bindings expect second Soundwire interrupt to be "wakeup" (Linux driver takes by index): sm8450-hdk.dtb: soundwire-controller@33b0000: interrupt-names:1: 'wakeup' was expected Fixes: 14341e76 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") Signed-off-by:
-
Eric Chanudet authored
A few descriptions including a qcom,pm8941-rtc describe two reg-names for the "rtc" and "alarm" register banks, but only one offset. For consistency with reg-names, add the "alarm" register offset. No functional change is expected from this. Signed-off-by:
Eric Chanudet <echanude@redhat.com> Reviewed-by:
-
Eric Chanudet authored
Include the dtsi to use a single pmic descriptions. Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently. Signed-off-by:
-
Eric Chanudet authored
Add the rtc block on the first pmic to enable the rtc for sa8540p-ride. Signed-off-by:
-
Eric Chanudet authored
pm8450a.dtsi was introduced for the descriptions of pmics used on sa8540p based boards. Rename the dtsi to make this relationship explicit. Signed-off-by:
-
Konrad Dybcio authored
SM8350 is one of the last SoCs whose DTSI escaped the smem node conversion. Use the newer memory-node binding instead of a memory *and* smem node. Signed-off-by:
-
Dmitry Baryshkov authored
Add includes for PMICs used on the SM8450-HDK. This makes GPIO blocks and thermal sensors available to the user of the platform. Signed-off-by:
-
Vinod Koul authored
SM8450 HDK features bunch of PMICs, add the PMICs which we have already upstream files Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
-
Dmitry Baryshkov authored
Add includes for PMICs used on the SM8450-HDK. This makes GPIO blocks and thermal sensors available to the user of the platform. Signed-off-by:
-
Vinod Koul authored
SM8450 QRD features bunch of PMICs, add the PMICs which we have already upstream files Signed-off-by:
-
Krzysztof Kozlowski authored
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. In few places adjust the name to match other nodes (e.g. xxx-regulator). Signed-off-by:
-
Owen Yang authored
Add DT for sc7280-herobrine-zombie with NVMe Signed-off-by:
Owen Yang <ecs.taipeikernel@gmail.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
-
Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
-
Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
-
Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
-
Konrad Dybcio authored
Add a fallback CCI compatible, as required by bindings. Signed-off-by:
-
Konrad Dybcio authored
As much as it hurts me, there is no FM radio chips on these devices. It seems to be present on Japanese models, but these are not available globally and differ in a few more ways anyway (such as a super high-tech NFC chip). Since it's the only subdevice of its I2C host bus, disable said bus to save some power. Signed-off-by:
-
Konrad Dybcio authored
As much as it hurts me, there is no FM radio chips on these devices. It seems to be present on Japanese models, but these are not available globally and differ in a few more ways anyway (such as a super high-tech NFC chip). Since it's the only subdevice of its I2C host bus, disable said bus to save some power. Signed-off-by:
-
Konrad Dybcio authored
As much as it hurts me, there is no FM radio chips on these devices. It seems to be present on Japanese models, but these are not available globally and differ in a few more ways anyway (such as a super high-tech NFC chip). Signed-off-by:
-
Srinivasa Rao Mandadapu authored
Set a performance state for audio clks so that the minimally correct corner voltage is picked when audio is active. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by:
-
Krzysztof Kozlowski authored
The Always On Subsystem (AOSS) QMP is not a power domain controller since commit 13578045 ("arm64: dts: qcom: sc7180: Use QMP property to control load state") and few others. In fact, it was never a power domain controller but rather control of power state of remote processors. This power state control is now handled differently, thus the AOSS QMP nodes do not have power-domain-cells: sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property From schema: Documentation/devicetree/bindings/power/power-domain.yaml AOSS QMP is an interface to the actuall AOSS subsystem responsible for some of power management functions, thus let's call the nodes as "power-management". Signed-off-by:
-
Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
-
Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 14abf8df ("arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280") Signed-off-by:
-
Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 0f9dc5f0 ("arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device") Signed-off-by:
-
Shazad Hussain authored
Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to get pcie 2a controller enabled on Qdrive3. This patch enables 4GB 64bit memory space for PCIE_2A to have BAR allocations of 64bit pref mem needed on this Qdrive3 platform with dual SoCs for root port and switch NT-EP. Hence this ranges property is overridden in sa8540p-ride.dts only. Moved tlmm node at the end as it tends to become rahter long. Link: https://lore.kernel.org/lkml/Y49k1k8ayI9%2FrK+R@hovoldconsulting.com/Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> Reviewed-by:
Brian Masney <bmasney@redhat.com> Signed-off-by:
-
Krzysztof Kozlowski authored
Order top-level nodes like memory, reserved-memory, opp-table-cpu alphabetically for easier code maintenance. No functional change (same dtx_diff, except phandle changes). Signed-off-by:
-
Krzysztof Kozlowski authored
Order top-level nodes like memory, reserved-memory, opp-table-cpu alphabetically for easier code maintenance. No functional change (same dtx_diff). Signed-off-by:
-
Rob Herring authored
'arm,kryo' is not documented and is not an Arm Ltd thing either as that is Qualcomm branding. The correct compatible is 'qcom,kryo'. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
