- 20 May, 2021 14 commits
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Vandita Kulkarni authored
Update MBUS_CTL register if the 2 mbus can be joined as per the current DDB allocation and active pipes, also update hashing mode and pipe select bits as per the sequence mentioned in the bspec. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-10-lucas.demarchi@intel.com
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Ville Syrjälä authored
The dbuf slices are going to be split across several MBUS units. The actual dbuf programming will use offsets relative to the MBUS unit. To accommodate that we shall store the MBUS relative offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[]. For crtc_state->wm.skl.ddb however we want to stick to global offsets as we use this to sanity check that the ddb allocations don't overlap between pipes. Cc: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Vandita Kulkarni authored
On adlp the two mbuses have two display pipes and two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on Mbus2. The Mbus can be joined and all the DBUFS can be used on Pipe A or B. Bspec: 49255 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
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José Roberto de Souza authored
Alderlake-P don't have programing sequences for MBUS or DBUF during display initializaiton, instead it requires programing to those registers during modeset because it to depend on the pipes left enabled. Bspec: 49213 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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José Roberto de Souza authored
ADL-P have basically the same TC connection and disconnection sequences as ICL and TGL, the major difference is the new registers. So here adding functions without the icl prefix in the name and making the new functions call the platform specific function to access the correct register. v2: - Retain DDI TC PHY ownership flag during modesetting. BSpec: 55480 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Anusha Srivatsa authored
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4. The first two are connected to combo phys while the rest are connected to TC phys. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
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Matt Roper authored
XE_LPD reduces the number of regular watermark latency levels from 8 to 6 on non-dgfx platforms. However the hardware also adds a special purpose SAGV wateramrk (and an accompanying transition watermark) that will be used by the hardware in place of the level 0 values during SAGV transitions. Bspec: 49325, 49326, 50419 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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Vandita Kulkarni authored
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by the VESA C model for DSC 1.1 v2: - Add include guard to header (Jani) - Move the big tables to a .c file (Chris, Jani, Lucas) v3: - Make tables 'static const' and add lookup functions to index into them. (Jani) v3.1: - Include missing .h file. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Vandita Kulkarni authored
Add methods to calculate rc parameters for all bpps, against the fixed arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444 formats. Our hw doesn't support YUV compression yet. The calculations used here are from VESA C model for DSC 1.1 v2: - Checkpatch fixes Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Juha-Pekka Heikkil <juha-pekka.heikkila@intel.com> Signed-off-by:
Mohammed Khajapasha <mohammed.khajapasha@intel.com> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Anusha Srivatsa authored
Finally, rename the header and source file from csr to dmc. v2: Add file rename in Documentation. - Place headers in orders. (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Anusha Srivatsa authored
No functional change. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Anusha Srivatsa authored
Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Anusha Srivatsa authored
No functional change. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Anusha Srivatsa authored
No functional change. v2: Chchpatch fixes. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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- 18 May, 2021 2 commits
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José Roberto de Souza authored
If the do while loop breaks in 'if (!sg_dma_len(sgl))' in the first iteration, err is uninitialized causing a wrong call to zap_vma_ptes(). But that is impossible to happen as a scatterlist must have at least one valid segment. Anyways to avoid more reports from static checkers initializing ret here. Fixes: b12d691e ("i915: fix remap_io_sg to verify the pgprot") Reviewed-by:
Christoph Hellwig <hch@lst.de> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by:
James Ausmus <james.ausmus@intel.com> Signed-off-by:
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Simon Rettberg authored
When resetting CACHE_MODE registers, don't enable HiZ Raw Stall Optimization on Ivybridge GT1 and Baytrail, as it causes severe glitches when rendering any kind of 3D accelerated content. This optimization is disabled on these platforms by default according to official documentation from 01.org. Fixes: ef99a60f ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals") BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3081 BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3404 BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/3071Reviewed-By:
Manuel Bentele <development@manuel-bentele.de> Signed-off-by:
Simon Rettberg <simon.rettberg@rz.uni-freiburg.de> Reviewed-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo removed invalid Fixes line] Link: https://patchwork.freedesktop.org/patch/msgid/20210426161124.2b7fd708@dellnichtsogutkiste
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- 17 May, 2021 1 commit
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Rodrigo Vivi authored
Time to get back in sync... Signed-off-by:
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- 15 May, 2021 19 commits
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José Roberto de Souza authored
Buffer compression is not usable in A stepping. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton A Taylor <clinton.a.taylor@intel.com> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> Signed-off-by:
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José Roberto de Souza authored
Implementation details are in the HSD 22011320316, requiring CD clock to be at least 307MHz to make DC states to work. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-19-matthew.d.roper@intel.com
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José Roberto de Souza authored
Adding a new hook to ADL-P just to avoid another platform check in gen12lp_init_clock_gating() but also open to it. BSpec: 54369 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
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José Roberto de Souza authored
This will allow us to better implement workarounds. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Animesh Manna authored
Respective bit for master or slave to be set for uncompressed bigjoiner in dss_ctl1 register. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Signed-off-by:
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Animesh Manna authored
For uncompressed big joiner DSC engine will not be used so will avoid compute config of DSC. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Animesh Manna authored
No need for checking dsc flag for uncompressed pipe joiner mode validation. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Mika Kahola authored
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz. For all other modes, we can enable loadgen sharing feature. BSpec: 55359 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Ville Syrjälä authored
Move intel_modeset_all_pipes() to a central place so that we can use it elsewhere as well. No functional changes. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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José Roberto de Souza authored
Alderlake P have modular FIA like TGL but it is always modular in all skus, not like TGL that we had to read a register to check if it is monolithic or modular. BSpec: 55480 BSpec: 50572 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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José Roberto de Souza authored
When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display has the control over the TC phy. The "not safe" naming is confusing using ownership make it easier to read also future platforms will have a new register that does the same job as DP_PHY_MODE_STATUS_NOT_SAFE but with the onwership name. BSpec: 49294 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Anusha Srivatsa authored
ADL-P has 3 possible refclk frequencies: 19.2MHz, 24MHz and 38.4MHz While we're at it, remove the drm_WARNs. They've never actually helped us catch any problems, but it's very easy to forget to update them properly for new platforms. BSpec: 55409, 49208 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Matt Roper authored
ADL-P further extends the bits in PLANE_WM that represent blocks and lines; we need to extend our masks accordingly. Since these bits are reserved and MBZ on earlier platforms, it's safe to use the larger bitmask on all platforms. Bspec: 50419 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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José Roberto de Souza authored
This will allow proper DDI initialization based on vbt information. Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Vandita Kulkarni authored
We need slice height to calculate few RC parameters hence assign slice height first. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Vandita Kulkarni authored
Support compression BPPs from bpc to uncompressed BPP -1. So far we have 8,10,12 as valid compressed BPPS now the support is extended. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Vandita Kulkarni authored
Move the platform specific max bpc calculation into intel_dp_dsc_compute_bpp function Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Matt Roper authored
XE_LPD continues to use the same "skylake-style" watermark programming as other recent platforms. The only change to the watermark calculations compared to Display12 is that XE_LPD now allows a maximum of 255 lines vs the old limit of 31. Due to the larger possible lines value, the corresponding bits representing the value in PLANE_WM are also extended, so make sure we read/write enough bits. Let's also take this opportunity to switch over to the REG_FIELD notation. Bspec: 49325 Bspec: 50419 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
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Matt Roper authored
The DDI naming template for display version 12 went A-C, TC1-TC6. With XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4. The XE_LPD design keeps the register offsets and bitfields relating to the TC outputs in the same location they were previously. The new "D" and "E" outputs now take the locations that were previously used by TC5 and TC6 outputs, or what we would have considered to be outputs "H" and "I" under the legacy lettering scheme. For the most part everything will just work as long as we initialize the output with the proper 'enum port' value. However we do need to take care to pick the correct AUX channel when parsing the VBT (e.g., a reference to 'AUX D' is actually asking us to use the 8th aux channel, not the fourth). We should also make sure that our encoders and aux channels are named appropriately so that it's easier to correlate driver debug messages with the bspec instructions. v2: - Update handling of TGL_TRANS_CLK_SEL_PORT. (Jose) v3: - Add hpd_pin to handle outputs D and E (Jose) - Fixed conversion of BIOS port to aux ch for TC ports (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 12 May, 2021 4 commits
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Umesh Nerlige Ramappa authored
Enable relevant OA formats for ADL_P. Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-8-matthew.d.roper@intel.com
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Clinton Taylor authored
Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we would assign the DDC pin map based on the PCH, but it can also change based on the CPU. From Bspec 20124: "The physical port to pin pair mapping are defined in the Bspec per PCH. Mapping can further change based on CPU Si used as CPU and PCH can be mixed and matched". Bspec: 20124 Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Matt Roper authored
Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by:
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Matt Roper authored
If VT-d is active, the memory bandwidth usage of the display is 5% higher. Take this into account when determining whether we can support a display configuration. Bspec: 64631 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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