- 23 Apr, 2024 6 commits
-
-
Dmitry Baryshkov authored
Instead of having a u8 or bool field unpack_align_msb, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590427/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-7-9e93226cbffd@linaro.org
-
Dmitry Baryshkov authored
Instead of having a u8 or bool field unpack_tight, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Reviewed-by:
-
Dmitry Baryshkov authored
Structures dpu_format and mdp_format are largely the same structures. In order to remove duplication between format databases, merge these two stucture definitions into the global struct msm_format. Reviewed-by:
-
Dmitry Baryshkov authored
In preparation to merger of formats databases, pull format flag definitions to mdp_format.h header, so that they are visibile to both dpu and mdp drivers. Signed-off-by:
-
Dmitry Baryshkov authored
Using bitmap for the flags results in a clumsy syntax on test_bit, replace it with unsigned long type and simple binary ops. Reviewed-by:
-
Dmitry Baryshkov authored
MDP4 and MDP5 drivers enumerate supported formats each time the plane is created. In preparation to merger of MDP DPU format databases, define precise formats list, so that changes to the database do not cause the driver to add unsupported format to the list. Reviewed-by:
-
- 22 Apr, 2024 34 commits
-
-
Dmitry Baryshkov authored
Instead of having DPU-specific defines, switch to the definitions from the mdp_common.xml.h file. This is the preparation for merged of DPU and MDP format tables. Reviewed-by:
-
Marijn Suijten authored
All other functions in dpu_hw_intf name the "self" parameter `intf`, except dpu_hw_intf_setup_timing_engine() and the recently added dpu_hw_intf_program_intf_cmd_cfg(). Clean that up for consistency. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
-
Marijn Suijten authored
Just like the active interface and writeback block in ctl_intf_cfg_v1(), and later the rest of the blocks in followup active-CTL fixes or reworks, multiple calls to this function should enable additional DSC blocks instead of overwriting the blocks that are enabled. This pattern is observed in an active-CTL scenario since DPU 5.0.0 where for example bonded-DSI uses a single CTL to drive multiple INTFs, and each encoder calls this function individually with the INTF (hence the pre-existing update instead of overwrite of this bitmask) and DSC blocks it wishes to be enabled, and expects them to be OR'd into the bitmask. The reverse already exists in reset_intf_cfg_v1() where only specified DSC blocks are removed out of the CTL_DSC_ACTIVE bitmask (same for all other blocks and ACTIVE bitmasks), leaving the rest enabled. Fixes: 77f6da90 ("drm/msm/disp/dpu1: Add DSC support in hw_ctl") Signed-off-by:
-
Marijn Suijten authored
As we can clearly see in a downstream kernel [1], flushing the slave INTF is skipped /only if/ the PPSPLIT topology is active. However, when DPU was originally submitted to mainline PPSPLIT was no longer part of it (seems to have been ripped out before submission), but this clause was incorrectly ported from the original SDE driver. Given that there is no support for PPSPLIT (currently), flushing the slave INTF should /never/ be skipped (as the `if (ppsplit && !master) goto skip;` clause downstream never becomes true). [1]: https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/blob/display-kernel.lnx.5.4.r1-rel/msm/sde/sde_encoder_phys_cmd.c?ref_type=heads#L1131-1139 Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by:
-
Marijn Suijten authored
When dual-DSI (bonded DSI) was added in commit ed9976a0 ("drm/msm/dsi: adjust dsi timing for dual dsi mode") some DBG() prints were not updated, leading to print the original mode->clock rather than the adjusted (typically the mode clock divided by two, though more recently also adjusted for DSC compression) msm_host->pixel_clk_rate which is passed to clk_set_rate() just below. Fix that by printing the actual pixel_clk_rate that is being set. Fixes: ed9976a0 ("drm/msm/dsi: adjust dsi timing for dual dsi mode") Signed-off-by:
-
Dmitry Baryshkov authored
Instead of having two functions, msm_dsi_manager_bridge_init() and msm_dsi_manager_ext_bridge_init(), merge them into msm_dsi_manager_connector_init(), moving drm_bridge_attach() to be called from the bridge's attach callback (as most other bridges do). Signed-off-by:
-
Dmitry Baryshkov authored
Currently the MSM DSI driver looks for the next bridge during msm_dsi_modeset_init(). If the bridge is not registered at that point, this might result in -EPROBE_DEFER, which can be problematic that late during the device probe process. Move next bridge acquisition to the dsi_bind state so that probe deferral is returned as early as possible. Signed-off-by:
-
Dmitry Baryshkov authored
All the bridges that are being used with the MSM DSI hosts have been converted to support DRM_BRIDGE_ATTACH_NO_CONNECTOR. Drop the fallback code and require DRM_BRIDGE_ATTACH_NO_CONNECTOR to be supported by the downstream bridges. Signed-off-by:
-
Konrad Dybcio authored
Totally useless. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Andrew Halaney <ahalaney@redhat.com> Patchwork: https://patchwork.freedesktop.org/patch/588804/ Link: https://lore.kernel.org/r/20240410-topic-msm_rw-v1-1-e1fede9ffaba@linaro.orgSigned-off-by:
-
Jon Hunter authored
The gen_header.py script is failing for older versions of python3 such as python 3.5. Two issues observed with python 3.5 are ... 1. Python 3 versions prior to 3.6 do not support the f-string format. 2. Early python 3 versions do not support the 'required' argument for the argparse add_subparsers(). Fix both of the above so that older versions of python 3 still work. Fixes: 8f7abf0b86fe ("drm/msm: generate headers on the fly") Signed-off-by:Jon Hunter <jonathanh@nvidia.com> Reviewed-by:
-
Dmitry Baryshkov authored
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A6xx header. Signed-off-by:
-
Dmitry Baryshkov authored
As a preparation to removal of a6xx.xml.h, drop the C++ part of the heder, it is not used by the kernel anyway. Signed-off-by:
-
Dmitry Baryshkov authored
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A6xx GMU header. Signed-off-by:
-
Dmitry Baryshkov authored
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A5xx header. Signed-off-by:
-
Dmitry Baryshkov authored
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A3xx and A4xx headers. Signed-off-by:
-
Dmitry Baryshkov authored
Now as the headers are generated during the build step, drop pre-generated copies of the Adreno A2xx and common headers. Signed-off-by:
-
Dmitry Baryshkov authored
Now as the headers are generated during the build step, drop pre-generated copies of the display-related headers. Signed-off-by:
-
Dmitry Baryshkov authored
Generate DRM/MSM headers on the fly during kernel build. This removes a need to push register changes to Mesa with the following manual synchronization step. Existing headers will be removed in the following commits (split away to ease reviews). Signed-off-by:
-
Dmitry Baryshkov authored
Import the gen_headers.py script from Mesa, commit b5414e716684 ("freedreno/registers: Add license header"). This script will be used to generate MSM register files on the fly during compilation. Signed-off-by: -
Dmitry Baryshkov authored
Import Adreno registers database for A6xx from the Mesa, commit 639488f924d9 ("freedreno/registers: limit the rules schema"). Signed-off-by: -
Dmitry Baryshkov authored
Import Adreno registers database for A5xx from the Mesa, commit 639488f924d9 ("freedreno/registers: limit the rules schema"). Signed-off-by: -
Dmitry Baryshkov authored
Import Adreno registers database for A2xx-A4xx from the Mesa, commit 639488f924d9 ("freedreno/registers: limit the rules schema"). Signed-off-by: -
Dmitry Baryshkov authored
Import display-related registers database from the Mesa, commit 639488f924d9 ("freedreno/registers: limit the rules schema"). The msm.xml and mdp_common.xml files were adjusted to drop subdirectory paths. Signed-off-by: -
Dmitry Baryshkov authored
Two core driver files include headers from Adreno subdir, which also brings dependency on the Adreno register headers. Rework those includes to remove unnecessary dependency. Signed-off-by:
-
Dmitry Baryshkov authored
The msm_gpummu.c implementation is used only on A2xx and it is tied to the A2xx registers. Rename the source file accordingly. Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by:
-
Dmitry Baryshkov authored
The mmss_cc.xml.h file describes bits of the MMSS clock controller on APQ8064 / MSM8960 platforms. They are not used by the driver and do not belong to the DRM MSM driver. Drop the file. Reviewed-by:
-
Dmitry Baryshkov authored
The qfprom.xml.h contains definitions for the nvmem code. They are not used in the existing code. Also if we were to use them later, we should have used nvmem cell API instead of using these defs. Drop the file. Reviewed-by:
-
Dmitry Baryshkov authored
In order to stop patching the mdp5 headers, import definitions for the writeback blocks. This part is extracted from the old Rob's patch. Co-developed-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
-
Bjorn Andersson authored
The dp_audio read and write operations uses members in struct dp_catalog for passing arguments and return values. This adds unnecessary complexity to the implementation, as it turns out after detangling the logic that no state is actually held in these variables. Clean this up by using function arguments and return values for passing the data. Reviewed-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/585350/ Link: https://lore.kernel.org/r/20240328-msm-dp-cleanup-v2-6-a5aed9798d32@quicinc.comSigned-off-by:
-
Bjorn Andersson authored
dp_catalog_panel_timing_cfg() takes 4 arguments, which are passed from the calling function through members of struct dp_catalog. No state is maintained other than across this call, so switch to function arguments to clean up the code. Reviewed-by:
-
Bjorn Andersson authored
The dp_aux write operations takes the data to be operated on through a member of struct dp_catalog, rather than as an argument to the function. No state is maintained other than across the calling of the functions, so replace this member with a function argument. Reviewed-by:
-
Bjorn Andersson authored
Throughout the Qualcomm Displayport driver a number of defines and struct members has become unused, but lingers in the code. Remove these. Reviewed-by:
-
Bjorn Andersson authored
The "desc" member of struct dp_panel is zero-initialized during allocation and never assigned, resulting in dp_ctrl_use_fixed_nvid() never returning true. This returned boolean value is passed around but never acted upon. Perform constant propagation and remove the traces of "fixed nvid". Reviewed-by:
-
Bjorn Andersson authored
The members of struct dp_debug are no longer used, so the only purpose of this struct is as a type of the return value of dp_debug_get(), to signal success/error. Drop the struct in favor of signalling the result of initialization using an int, then merge dp_debug_get() with dp_debug_init() to avoid the unnecessar boilerplate code. Signed-off-by:
-
