- 03 Oct, 2019 40 commits
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Tao Zhou authored
change struct ras_err_data *err_data to void *err_data, align with umc code and the callback's declaration in each ras block could pay no attention to the structure type Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
issue: the UMC6 h/w bug is that when MCLK is doing the switch in the middle of a page access being preempted by high priority client (e.g. DISPLAY) then UMC and the mclk switch would stuck there due to deadlock how: fixed by disabling auto PreChg for UMC to avoid high priority client preempting other client's access on the same page, thus the deadlock could be avoided v2: put the patch in callback of UMC6 v3: rename the callback to "init_registers" Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Hawking Zhang <hawking.zhang@amd.com> Signed-off-by:
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Marek Olšák authored
Never used. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
fetch both the vram type and width in one function call. This avoids having to parse the same data table twice to get the two pieces of data. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Alex Deucher authored
The index is stored in scratch register 4 after asic init. Use that index. No functional change since all asics in a family use the same type of vram (G5, G6, HBM) and that is all we use at the monent, but if we ever need to query other info, we will now have the proper index. v2: module array is variable sized, handle that. v3: fix off by one in array handling Reviewed-by:
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Alex Deucher authored
It's apparently needed in some configurations. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Shirish S authored
log the response status related error to the driver's debug log since psp response status is not 0 even though there was no problem while the command was submitted. This warning misleads, hence this change. Signed-off-by:
Shirish S <shirish.s@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Kevin Wang authored
remove duplicate macro of smu_get_uclk_dpm_states fix commit: drm/amd/powerplay: add the interface for getting ultimate frequency v3 Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Jesse Zhang authored
When compute fence did not signal, compute ring cannot detect hardware hang because its timeout value is set to be infinite by default. In SR-IOV and passthrough mode, if user does not declare custome timeout value for compute ring, then use gfx ring timeout value as default. So that when there is a ture hardware hang, compute ring can detect it. Signed-off-by:
Jesse Zhang <zhexi.zhang@amd.com> Reviewed-by:
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chen gong authored
Renoir need to use mode2 mode to implement GPU RESET Signed-off-by:
chen gong <curry.gong@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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chen gong authored
Changes to function "smu_suspend" in amdgpu_smu.c is a workaround. We should get real information about if baco is enabled or not, while we always consider APU SMU feature as enabled in current code. I know APU do not support baco mode for GPU reset, so I use "adev->flags" to skip function "smu_feature_is_enabled". Signed-off-by:
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chen gong authored
Renoir need to use mode2 mode to implement GPU RESET Signed-off-by:
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Yong Zhao authored
get_hive_id was not set. Also, adjust the function setting sequence. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
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Yong Zhao authored
Currently this function pointer is missing for GFX10. Considering it is a void function since GFX9, fix it by checking the function pointer before dereferencing it. Signed-off-by:
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Yong Zhao authored
The packet manager is not needed for non HWS mode except Hawaii, so only initialize it for Hawaii under non HWS mode. This will simplify debugging under non HWS mode for all new asics, because it eliminates one variable out of the equation in non HWS mode Signed-off-by:
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Yong Zhao authored
The dozens of printing messages are compressed into 2 lines. Signed-off-by:
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Yong Zhao authored
The message will be useful when troubleshooting the issues. Signed-off-by:
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Alex Deucher authored
Use proper helper for 32 bit. Reviewed-by:
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Le Ma authored
Otherwise non-autoload case will go into the wrong routine and fail. Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Hawking Zhang authored
For better clarification of issue. Signed-off-by:
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Le Ma authored
Front door firmware loading is done via the psp rather than the driver. Signed-off-by:
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Le Ma authored
Needs more work to enable via front door loading. Signed-off-by:
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Tianci.Yin authored
load different cp firmware according to the DID and RID Reviewed-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Allen Pais authored
alloc_workqueue is not checked for errors and as a result, a potential NULL dereference could occur. v2 (Felix Kuehling): * Fix compile error (kfifo_free instead of fifo_free) * Return proper error code Signed-off-by:
Allen Pais <allen.pais@oracle.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Alex Deucher authored
Add new sections to amdgpu.rst, fix up formatting issues, add additional documentation to each section. Acked-by:
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Alex Deucher authored
Fix DOC link name, clean up formatting in pp_dpm_* section. Acked-by:
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Alex Deucher authored
Fix parameters. Acked-by:
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Alex Deucher authored
Missing parameters, wrong comment type, etc. Acked-by:
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Alex Deucher authored
Document the new parameter. Fixes: 93065ac7 ("mm, oom: distinguish blockable mode for mmu notifiers") Acked-by:
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Alex Deucher authored
Drop extra function parameter. Acked-by:
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Harry Wentland authored
We had a couple of missing definitions and formatting errors. v2: Fix 'notifying' type Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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yu kuai authored
Fixes gcc warning: drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:431: warning: Excess function parameter 'sw' description in 'vcn_v2_5_disable_clock_gating' drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:550: warning: Excess function parameter 'sw' description in 'vcn_v2_5_enable_clock_gating' Fixes: cbead2bd ("drm/amdgpu: add VCN2.5 VCPU start and stop") Signed-off-by:
yu kuai <yukuai3@huawei.com> Signed-off-by:
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Arnd Bergmann authored
Without CONFIG_DEBUG_FS, we get a warning for an unused variable: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6020:33: error: unused variable 'source' [-Werror,-Wunused-variable] Hide the variable in an #ifdef like its only users. Fixes: 14b25846 ("drm/amd/display: add functionality to grab DPRX CRC entries.") Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Guchun Chen authored
Enable full ras by default, user does not need to enable it by boot parameter. Signed-off-by:
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Jiange Zhao authored
Add Navi12 PCI id support. v2: flag as experimental for now (Alex) Signed-off-by:
Jiange Zhao <Jiange.Zhao@amd.com> Reviewed-by:
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Tianci.Yin authored
update registers: mmUTCL1_CTRL Reviewed-by:
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Tianci.Yin authored
update registers: mmUTCL1_CTRL Reviewed-by:
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Alex Deucher authored
We can remove this later as things get closer to launch. Reviewed-by:
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Alex Deucher authored
Otherwise we may get stale data. Reviewed-by:
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Alex Deucher authored
We need to make sure the fifo is flushed before we ask the psp to process the commands. Reviewed-by:
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