- 30 Mar, 2021 1 commit
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Wang Qing authored
The TODO file here has not been updated for 15 years, and the function development described in the file have been implemented or abandoned. Its existence will mislead developers seeking to view outdated information. Signed-off-by:
Wang Qing <wangqing@vivo.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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- 29 Mar, 2021 7 commits
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Qing Zhang authored
When using the Loongson-3A4000 machine for serial port debugging, there is no /dev/ttyUSB* output, which makes the serial port unavailable, For convenience, we open this configuration. zhangqing@loongson-pc:~$ cat /sys/firmware/lefi/boardinfo Board Info Manufacturer : THTF Board Name : THTF-LS3A4000-7A1000-ML4A Family : LOONGSON3 BIOS Info Vendor : ZD tech Version : ZD tech-V2.1.1 ROM Size : 4 KB Release Date : 2020-06-29 zhangqing@loongson-pc:~$ lsusb Bus 006 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 005 Device 003: ID 093a:2510 Pixart Imaging, Inc. Optical Mouse Bus 005 Device 002: ID 0c45:760b Microdia USB Keyboard Bus 005 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 004 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 003 Device 003: ID 067b:2303 Prolific Technology, Inc. PL2303 Serial Port Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub Signed-off-by:
Qing Zhang <zhangqing@loongson.cn> Signed-off-by:
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Ilya Lipnitskiy authored
poly1305-core.S is an auto-generated file, so it should be ignored. Fixes: a11d055e ("crypto: mips/poly1305 - incorporate OpenSSL/CRYPTOGAMS optimized implementation") Signed-off-by:
Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Cc: Ard Biesheuvel <ardb@kernel.org> Signed-off-by:
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Chuanhong Guo authored
mt7621 has the following memory map: 0x0-0x1c000000: lower 448m memory 0x1c000000-0x2000000: peripheral registers 0x20000000-0x2400000: higher 64m memory detect_memory_region in arch/mips/kernel/setup.c only adds the first memory region and isn't suitable for 512m memory detection because it may accidentally read the memory area for peripheral registers. This commit adds memory detection capability for mt7621: 1. Add the highmem area when 512m is detected. 2. Guard memcmp from accessing peripheral registers: This only happens when a user decided to change kernel load address to 256m or higher address. Since this is a quite unusual case, we just skip 512m testing and return 256m as memory size. Signed-off-by:Chuanhong Guo <gch981213@gmail.com> [Minor commit message reword, make mt7621_memory_detect static] Signed-off-by:
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Ilya Lipnitskiy authored
prom_soc_init is only called from prom_init in arch/mips/ralink/prom.c, which is already annotated with __init, so annotate prom_soc_init with __init too. Signed-off-by:
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Julian Braha authored
When CAVIUM_OCTEON_SOC is enabled, and MTD is disabled, Kbuild gives the following warning: WARNING: unmet direct dependencies detected for MTD_COMPLEX_MAPPINGS Depends on [n]: MTD [=n] && HAS_IOMEM [=y] Selected by [y]: - CAVIUM_OCTEON_SOC [=y] && <choice> This is because CAVIUM_OCTEON_SOC selects MTD_COMPLEX_MAPPINGS, without selecting or depending on MTD, despite MTD_COMPLEX_MAPPINGS depending on MTD. Signed-off-by:
Julian Braha <julianbraha@gmail.com> Signed-off-by:
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Julian Braha authored
When SB1XXX_CORELIS is enabled, COMPILE_TEST is disabled, and DEBUG_KERNEL is disabled, Kbuild gives the following warning: WARNING: unmet direct dependencies detected for DEBUG_INFO Depends on [n]: DEBUG_KERNEL [=n] && !COMPILE_TEST [=n] Selected by [y]: - SB1XXX_CORELIS [=y] && SIBYTE_SB1xxx_SOC [=y] && !COMPILE_TEST [=n] This is because SB1XXX_CORELIS selects DEBUG_INFO without selecting or depending on DEBUG_KERNEL, despite DEBUG_INFO depending on DEBUG_KERNEL. Signed-off-by:
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Tiezhu Yang authored
After commit 0ebeea8c ("bpf: Restrict bpf_probe_read{, str}() only to archs where they work"), bpf_probe_read{, str}() functions were no longer available on MIPS, so there exist some errors when running bpf program: root@linux:/home/loongson/bcc# python examples/tracing/task_switch.py bpf: Failed to load program: Invalid argument [...] 11: (85) call bpf_probe_read#4 unknown func bpf_probe_read#4 [...] Exception: Failed to load BPF program count_sched: Invalid argument ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE should be restricted to archs with non-overlapping address ranges, but they can overlap in EVA mode on MIPS, so select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA in arch/mips/Kconfig, otherwise the bpf old helper bpf_probe_read() will not be available. This is similar with the commit d195b1d1 ("powerpc/bpf: Enable bpf_probe_read{, str}() on powerpc again"). Fixes: 0ebeea8c ("bpf: Restrict bpf_probe_read{, str}() only to archs where they work") Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by:
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- 25 Mar, 2021 9 commits
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Huang Pei authored
When page size larger than 16KB, arguments "vaddr + size(16KB)" in "ioremap_page_range(vaddr, vaddr + size,...)" called by "add_legacy_isa_io" is not page-aligned. As loongson64 needs at least page size 16KB to get rid of cache alias, and "vaddr" is 64KB-aligned, and 64KB is largest page size supported, rounding "size" up to PAGE_SIZE is enough for all page size supported. Fixes: 6d0068ad ("MIPS: Loongson64: Process ISA Node in DeviceTree") Signed-off-by:
Huang Pei <huangpei@loongson.cn> Acked-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
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Krzysztof Kozlowski authored
The Ralink MIPS platform does not use Common Clock Framework and does not define certain clock operations leading to compile test failures: /usr/bin/mips-linux-gnu-ld: drivers/usb/phy/phy-tegra-usb.o: in function `tegra_usb_phy_init': phy-tegra-usb.c:(.text+0x1dd4): undefined reference to `clk_get_parent' Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by:
John Crispin <john@phrozen.org> Reviewed-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
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Qing Zhang authored
Add default config for Loongson-2K1000. Signed-off-by:
Ming Wang <wangming01@loongson.cn> Signed-off-by:
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Qing Zhang authored
Add liointc-2.0 properties support, so update the maxItems and condition description. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Qing Zhang authored
Add IO interrupt controller support for Loongson-2K1000, different from the Loongson-3A series is that Loongson-2K1000 has 64 interrupt sources, 0-31 correspond to the device tree liointc0 device node, and the other correspond to liointc1 node. Signed-off-by:
Marc Zyngier <maz@kernel.org> Signed-off-by:
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Qing Zhang authored
Distinguish between Loongson-3A series CPU and Loongson-2K1000 CPU UART0. Signed-off-by:
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Qing Zhang authored
Get the fixed-clock from the CPU0 node of the device tree. Signed-off-by:
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Qing Zhang authored
Add DTB boot support, only support Loongson-2K1000 processor for now, determine whether to use the built-in DTB or the DTB from the firmware by checking the range of CKSEG0 and XKPHYS. loongson_fw_interface will be used in the future. Signed-off-by:
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Qing Zhang authored
Add DeviceTree files for Loongson-2K1000 processor, currently only supports single-core boot. Signed-off-by:
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- 24 Mar, 2021 10 commits
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Huang Pei authored
commit ba9196d2 ("MIPS: Make DIEI support as a config option") use CPU_HAS_DIEI to indicate whether di/ei is implemented correctly, without this patch, "local_irq_disable" from entry.S in 3A1000 (with buggy di/ei) lose protection of commit e97c5b60 ("MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus") Fixes: ba9196d2 ("MIPS: Make DIEI support as a config option") Signed-off-by:
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Maciej W. Rozycki authored
Enable support for the onboard PATA PIO mode3 interface, which is one of the boot devices supported by the CFE firmware with the Broadcom SWARM board. Include disk, CD-ROM and generic storage drivers. Signed-off-by:
Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by:
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Maciej W. Rozycki authored
Options have been removed and reordered since the last update, so regenerate the template so as not to interfere with actual changes. Signed-off-by:
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Christoph Hellwig authored
Various malta defconfigs enable CONFIG_IDE for the tc86c001 ide driver, hich is a Toshiba plug in card that does not make much sense to use on bigsur platforms. For all other ATA cards libata support is already enabled. Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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Christoph Hellwig authored
bigsur_defconfig enables CONFIG_IDE for the tc86c001 ide driver, which is a Toshiba plug in card that does not make much sense to use on bigsur platforms. For all other ATA cards libata support is already enabled. Signed-off-by:
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Christoph Hellwig authored
rbtx49xx_defconfig enables CONFIG_IDE for the tx4938 and tx4939 ide drivers, but those aren't actually used by the last known remaining user: https://lore.kernel.org/lkml/20210107.101729.1936921832901251107.anemo@mba.ocn.ne.jp/Signed-off-by:
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Christoph Hellwig authored
Use libata instead of the deprecated legacy ide driver in workpad_defconfig. Signed-off-by:
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Christoph Hellwig authored
sb1250_swarm_defconfig enables CONFIG_IDE but no actual host controller driver, so just drop CONFIG_IDE, CONFIG_BLK_DEV_IDECD and CONFIG_BLK_DEV_IDETAPE as they are useless. Signed-off-by:
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Bhaskar Chowdhury authored
s/packt/packet/ Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Acked-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Bhaskar Chowdhury authored
s/techically/technically/ Signed-off-by:
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- 14 Mar, 2021 2 commits
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Wang Qing authored
debugfs_create_file_unsafe does not protect the fops handed to it against file removal. DEFINE_DEBUGFS_ATTRIBUTE makes the fops aware of the file lifetime and thus protects it against removal. Signed-off-by:
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Huang Pei authored
+. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached, instread of 0xa8xx_xxxx_xxxx_xxxx +. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit +. cast CAC_BASE into u64 to silence warning on MIPS32 CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field. +. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 53, only save 53 - 12 = 41 bits, aka : bit[63:59] | 0000 00 | bit[53:12] | 0000 0000 0000 +. for CKSEG0, only save 29 - 12 = 17 bits when switching pgd, only need to save bit[53:12] or bit[28:12] into CP0 Context's bit[63:23], see folling asm generated at run time tlbmiss_handler_setup_pgd: .set push .set noreorder dsra a2, a0, 29 move a3, a0 dins a0, zero, 29, 35 daddiu a2, a2, 4 //for CKSEG0, a2 from 0xfffffffffffffffc //into 0 movn a0, a3, a2 dsll a0, a0, 11 jr ra dmtc0 a0, CP0_CONTEXT .set pop when using it on page walking dmfc0 k0, CP0_CONTEXT dins k0, zero, 0, 23 // zero badv2 ori k0, k0, (CAC_BASE >> 53) // *prefix* with bit[63:59] drotr k0, k0, 11 // kick it in the right place Signed-off-by:
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- 12 Mar, 2021 11 commits
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Paul Cercueil authored
The NT39016 panel is a fun beast, even though the documentation states that the CS line is active-low, it will work just fine if the CS line is configured as active-high, but it won't work if the CS line is forced low or forced high. Since it did actually work with the spi-cs-high property, this is not a bugfix, but we should nonetheless remove that property to match the documentation. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
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Paul Cercueil authored
The NT39016 panel is a fun beast, even though the documentation states that the CS line is active-low, it will work just fine if the CS line is configured as active-high, but it won't work if the CS line is forced low or forced high. Since it did actually work with the spi-cs-high property, this is not a bugfix, but we should nonetheless remove that property from the example to match the documentation. Signed-off-by:
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Rafał Miłecki authored
Separated function was not improving code quality much (or at all). Moreover it expected possible flash end address as argument and it was returning NVRAM size. The new code always operates on offsets which means less logic and less calculations. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Signed-off-by:
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Rafał Miłecki authored
This loop requires variable initialization, stop condition and post iteration increment. It's pretty much a for loop definition. Signed-off-by:
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Rafał Miłecki authored
This simplifies function finding NVRAM. It doesn't directly deal with NVRAM structure anymore and is a bit smaller. Signed-off-by:
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Rafał Miłecki authored
This avoids duplicating code doing casting and checking for NVRAM magic. Signed-off-by:
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Rafał Miłecki authored
1. Use "bcm47xx_" function name prefix for consistency 2. It takes flash start as argument so s/iobase/flash_start/ 3. "off" was used for finding flash end so just call it "flash_size" Signed-off-by:
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Huang Pei authored
Loongson64 allocates arrays of pglist_data statically and is located at Node 0, and cpu from Nodes other than 0 need remote access to pglist_data and zone info. Delay pglist_data allocation till run time, and make it NUMA-aware Signed-off-by:
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Qing Zhang authored
The purpose of separating loongson_system_configuration from boot_param.h is to keep the other structure consistent with the firmware. Signed-off-by:
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Qing Zhang authored
We don't need them anymore, They are uniform on all Loongson64 systems and have been fixed in DeviceTree.loongson3_platform_init is replaced with DTS + driver. Signed-off-by:
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Ilya Lipnitskiy authored
Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL lock check. The existing code checks the wrong register bit: PPLL_SW_SET is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved in the MT7620 Programming Guide. The correct bit to check for PLL lock is PPLL_LD (bit 23). Also reword the error message for clarity. Without this change it is unlikely that this driver ever worked with mainline kernel. [0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.htmlSigned-off-by:
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