1. 27 Mar, 2020 10 commits
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  3. 25 Mar, 2020 18 commits
  4. 24 Mar, 2020 1 commit
    • José Roberto de Souza's avatar
      drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ · 691f7ba5
      José Roberto de Souza authored
      dGFX has local memory so it does not have aperture or support
      CPU fences but even for iGFX it have a small number of fences.
      
      As replacement for fences to track frontbuffer modifications by CPU
      we have a software tracking that is already in used by FBC and PSR.
      PSR don't support fences so it shows that this tracking is reliable.
      
      So lets make fences a nice-to-have to activate FBC for GEN9+, this
      will allow us to enable FBC for dGFXs and iGFXs even when there is no
      available fence.
      
      We do not set fences to rotated planes but FBC only have restrictions
      against 16bpp, so adding it here.
      
      Also adding a new check for the tiling format, fences are only set
      to X and Y tiled planes but again FBC don't have any restrictions
      against tiling so adding linear as supported as well, other formats
      should be added after tested but IGT only supports drawing in thse
      3 formats.
      
      intel_fbc_hw_tracking_covers_screen() maybe can also have the same
      treatment as fences but BSpec is not clear if the size limitation is
      for hardware tracking or general use of FBC and I don't have a 5K
      display to test it, so keeping as is for safety.
      
      v2:
      - Added tiling and pixel format rotation checks
      - Changed the GEN version not requiring fences to 11 from 9, DDX
      needs some changes but it don't have support for GEN11+
      
      v3:
      - Changed back to GEN9+
      - Moved GEN test to inside of tiling_is_valid()
      
      v4:
      - moved rotation check to its own functions
      
      v5:
      - renamed rotations_is_valid to rotation_is_valid
      - moved pre-g4x rotation check to rotation_is_valid()
      
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200319211535.114625-1-jose.souza@intel.com
      691f7ba5