- 31 Jan, 2013 33 commits
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Alex Deucher authored
It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Used by all asic families from r600+. Flag for the vbios and later instances of the driver that the GPU is hung. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds further flags for fine grained reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
KMS support is out and stable for a couple of years now and the userspace code has deprecated or abandoned the old UMS interface. So make the KMS interface the default and deprecate the UMS interface in the kernel as well. v2: rebased on alex/drm-next-3.9-wip Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jerome Glisse authored
This simplify and cleanup the async dma checking. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
After refactoring the _cs logic, we ended up with many macros and constants that #define the same thing. Clean'em up. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
This patch eliminates ASIC-specific ***_cs_packet_next_reloc functions and hooks up the new common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
next_reloc function does the same thing in all ASICs with the exception of R600 which has a special case in legacy mode. Pull out the common function in preparation for refactoring. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
This function is not limited to r100, but it can dump a (raw) packet for any ASIC. Rename it accordingly and move its declaration to radeon.h Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
WAIT_REG_MEM on register does not allow the use of PFP. Enforce this restriction when checking packets sent from userland. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
vline packet parsing function for R600 and Evergreen+ are the same, except that they use different registers. Factor out the algorithm into a common function that uses register table passed from ASIC-specific caller. This reduces ASIC-specific function to (trivial) setup of register table and call into the common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
Once we factored out radeon_cs_packet_parse function, evergreen_cs_next_is_pkt3_nop and r600_cs_next_is_pkt3_nop functions became identical, so they can be factored out into a common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
We now have a common radeon_cs_packet_parse function that is good for all ASICs. Hook it up and eliminate ASIC-specific versions. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
CS packet parse functions have a lot of in common across all ASICs. Implement a common function and take care of small differences between families inside the function. This patch is a prep for major refactoring and consolidation of CS parsing code. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
Preparatory patch: patches to follow will touch a piece of code that had broken indentication, so fix it before touching it. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilija Hadzic authored
length_dw field was assigned twice. While at it, move user_ptr assignment together with all other assignments to p->chunks[i] structure to make the code more readable. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
For large VM page table updates, we can sometimes generate more packets than there is space on the ring. This happens more readily with the DMA ring since it is 64K (vs 1M for the CP). For now, switch back to the CP. For the next kernel, I have a patch to utilize IBs for VM PT updates which alleviates this problem. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=58354Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
If the requested number of DWs on the ring is larger than the size of the ring itself, return an error. In testing with large VM updates, we've seen crashes when we try and allocate more space on the ring than the total size of the ring without checking. This prevents the crash but for large VM updates or bo moves of very large buffers, we will need to break the transaction down into multiple batches. I have patches to use IBs for the next kernel. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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liu chuansheng authored
When kzalloc() failed in radeon_user_framebuffer_create(), need to call object_unreference() to match the object_reference(). Signed-off-by: liu chuansheng <chuansheng.liu@intel.com> Signed-off-by: xueminsu <xuemin.su@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
Some chips seem to need a little delay after blacking out the MC before the requests actually stop. Stop DMAR errors reported by Shuah Khan. Reported-by: Shuah Khan <shuahkhan@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Some chips seem to need a little delay after blacking out the MC before the requests actually stop. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=56139 https://bugs.freedesktop.org/show_bug.cgi?id=57567Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 30 Jan, 2013 2 commits
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Mikko Tiihonen authored
Make sure at least one RB is enabled in r6xx_remap_render_backend() to avoid an division by zero in some corner cases. See: https://bugzilla.redhat.com/show_bug.cgi?id=892233Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
Need to adjust the backend map depending on which RB is enabled. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=892233Reported-by: Mikko Tiihonen <mikko.tiihonen@iki.fi> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 29 Jan, 2013 1 commit
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Alex Deucher authored
vbios says external TMDS while the board is actually internal TMDS. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60037Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 28 Jan, 2013 2 commits
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Alex Deucher authored
Newer versions of mesa emit this. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Christopher Staite authored
Force the crtc mem requests on/off immediately rather than waiting for the double buffered updates to kick in. Seems we miss the update in certain conditions. Also handle the DCE6 case. Signed-off-by: Christopher Staite <chris@yourdreamnet.co.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 26 Jan, 2013 1 commit
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git://people.freedesktop.org/~danvet/drm-intelDave Airlie authored
Just a few small things: - 2x workaround bits from Chris to fix up the new scanline waits enabled in 3.8 on snb. People who've been struck by this on dual-screen also need to upgrade the ddx. - Dump the kernel version into i915_error_state, we've had a few mixups there recently. - Disable gfx DMAR on gen4 devices, acked by David Woodhouse. * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: dump UTS_RELEASE into the error_state iommu/intel: disable DMAR for g4x integrated gfx drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits drm/i915: Disable AsyncFlip performance optimisations
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- 25 Jan, 2013 1 commit
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Dave Airlie authored
Merge branch 'exynos-drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next Inki writes: "This pull request includes some bug fixes, code cleanups and exception codes. If there is any problem, please kindly let me know." * 'exynos-drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: drm/exynos: add check for the device power status drm/exynos: Make 'drm_hdmi_get_edid' static drm/exynos: fimd and ipp are broken on multiplatform drm/exynos: don't include plat/gpio-cfg.h drm/exynos: Remove "internal" interrupt handling drm/exynos: Add missing static specifiers in exynos_drm_rotator.c drm/exynos: Replace mdelay with usleep_range drm/exynos: Make ipp_handle_cmd_work static drm/exynos: Make g2d_userptr_get_dma_addr static drm/exynos: consider DMA_NONE flag to dmabuf import drm/exynos: free sg object if dma_map_sg is failed drm/exynos: added validation of edid for vidi connection drm/exynos: let drm handle edid allocations
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