- 10 Dec, 2020 1 commit
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Andrey Grodzovsky authored
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation and amdgpu_gem_object_funcs setting into single function called from both code paths. Fixes: d693def4 ("drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver") v2: Use use amdgpu_gem_object_create() directly v3: fix warning Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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- 09 Dec, 2020 39 commits
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Alex Deucher authored
If we need to keep the stolen vga memory, make sure it is at least as big as the legacy vga size. Acked-by:
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Alex Deucher authored
No longer used. Reviewed-by:
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Alex Deucher authored
Rather than in late_init to avoid race conditions between freeing the buffers and the initial modeset. Reviewed-by:
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Alex Deucher authored
Works using BACO. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Works now that the BACO sequence is fixed. Reviewed-by:
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Changfeng authored
When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that it can't be able to switch to mak gpu clk during compute workload. It needs to update WORKLOAD_PPLIB setting to fix this issue. Signed-off-by:
Changfeng <Changfeng.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Xiaojian Du authored
This patch is to remove one unsupported smu function, this function will set the smu feature mask to disable all smu features in exception. Because vangogh doesn't support to set the smu feature mask by driver software, so this function is invalid for vangogh. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Roman Li authored
[Why] Scatter/gather is APU feature. But in dm it is limited only to Renoir. Now we need it for Vangogh. [How] Apply system context setup in dm_init to all APUs. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Roman Li authored
[Why] Scatter/gather feature is supported on Vangogh. [How] Add GTT domain support for Vangogh to enable display buffers in system memory. Signed-off-by:
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Felix Kuehling authored
Release dmabuf reference before returning from kfd_ioctl_import_dmabuf. amdgpu_amdkfd_gpuvm_import_dmabuf takes a reference to the underlying GEM BO and doesn't keep the reference to the dmabuf wrapper. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Nirmoy Das authored
Replace hardcoded vmid number with AMDGPU_NUM_VMID macro. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
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Stanley.Yang authored
each sdma instance fw_version and feature_version should be set right value when asic type isn't between SIENNA_CICHILD and CHIP_DIMGREY_CAVEFISH Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Tao Zhou authored
Per PMFW 59.16.0. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
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Anthony Koo authored
- Add define for __forceinline Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Michael Strauss authored
[Why] New value breaks VSR on high refresh panels, reverting until a fix is developed Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Charlene Liu authored
[Why] dcn3_01 supports gpu_vm, but this is not enabled in amdgpu_dm Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Roy Chan authored
[Why] When HDCP is on, some display would introduce audio noise during HDCP handling. [How] Mute before HDCP handling when disabling core link. Unmute after HDCP when enabling core link. Signed-off-by:
Roy Chan <roy.chan@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Sung Lee authored
[Why] Without additional HostVM Latency, Renoir takes 2us longer to exit self-refresh. This causes underflow in certain cases. [How] Add table for Renoir with updated sr exit latencies for WM set A. Signed-off-by:
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Chris Park authored
[Why] At very high pixel clock, bandwidth calculation exceeds 32 bit size and overflow value. This causes the resulting selection of link rate to be inaccurate. [How] Change order of operation and use fixed point to deal with integer accuracy. Also address bug found when forcing link rate. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Qingqing Zhuo authored
[Why] With the addition of dc_lock acquire before dc_link_handle_hpd_rx_irq, there will be a deadlock situation where commit state sends a request for payload allocation on MST and wait for HPD to process DOWN_REP. [How] Move forward the MST message handling in handle_hpd_rx_irq so that it will not rely on call to dc_link_handle_hpd_rx_irq. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Wesley Chalmers authored
[Why] Currently, the offset provided to dcn30_set_disp_pattern_generator is not forwarded to OPP for display pattern generation, resulting in misaligned patterns and test failures. [How] Use the provided offset. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Judy Cai authored
[Why] Change in DCN10 to use IMMEDIATE_UPDATE mode for AFMT is not reflected in DCN30 as it uses VPG. [How] Use IMMEDIATE_UPDATE mode for DCN30 in VPG. Signed-off-by:
Judy Cai <HuiYi.Cai@amd.com> Reviewed-by:
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John Wu authored
[Why] power_down_on_boot is designed to power down HW when set mode is not called before timeout. It can happen in headless system or booting with the display is output by non-AMD GPU only. The function will be executed only if it's not seamless boot. So in seamless boot, the HW is still on. It's not necessary to check this since there's no display data in both cases. [How] Remove seamless boot checking in power_down_on_boot. Signed-off-by:
John Wu <john.wu@amd.com> Reviewed-by:
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Jing Zhou authored
[Why] Bump into calcReducedBlankingTiming because of mode query failed. In this function, timing.displayColorDepth == DISPLAY_COLOR_DEPTH_UNDEFINED. Then req_bw == 0 because of bits_per_channel == 0. So decide edp link settings, use default RBRx1 for special timing. [How] Set default bits_per_channel is 8. Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] Add support for new fw command for runtime feature detection. [How] Driver sends command through ring buffer, and fw returns data back through this command. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Dmytro Laktyushkin authored
[How & Why] Allow clk_mgr functions to be reused by making then non-static Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Qingqing Zhuo authored
[Why] Calls to disable/enable stream should be guarded with dc_lock. [How] Add dc_lock before calling into dc_link_handle_hpd_rx_irq. Signed-off-by:
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AMD\ramini authored
[Why] Signal FreeSync display that we are in Fixed Rate mode, and expand the FreeSync range to 1024. [How] Set the new bit in SB16:bit0, and augment the min and max refresh rate with 2 extra bits. Signed-off-by:
AMD\ramini <Reza.Amini@amd.com> Reviewed-by:
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Reza Amini authored
[Why] Implement feature of VSIF V3 [How] Set refresh rate MSB for extended range Signed-off-by:
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Kevin Wang authored
the smc v2_0 printer is not compatible with the smc v2_1 . 1. add smc v2_1 printer. 2. cleanup code Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Kevin Wang authored
s/direct/immediate/g amdgpu vm has renamed parameter name from 'direct' to 'immedate'. however, the trace event is not updated yet. Signed-off-by:
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Arnd Bergmann authored
Without debugfs, the compiler notices one function that is not used at all: drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c:123:12: error: unused function 'amdgpu_is_fw_attestation_supported' [-Werror,-Wunused-function] In fact the static const amdgpu_fw_attestation_debugfs_ops structure is also unused here, but that warning is currently disabled. Removing the #ifdef check does the right thing and leads to all of this code to be dropped without warning. Fixes: 19ae3330 ("drm/amdgpu: added support for psp fw attestation") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Simon Ser authored
If this function fails, it means the tiling flags didn't make sense. This likely indicates a user-space bug. Log the error alongside with the provided tiling flags to make debugging easier. Signed-off-by:
Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Michel Dänzer <michel@daenzer.net> Signed-off-by:
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Simon Ser authored
Avoid printing an error with dev_err, because user-space can trigger these at will by issuing an ioctl. Convert a DRM_DEBUG_KMS call to the more modern drm_dbg_kms macro. Signed-off-by:
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Simon Ser authored
Previously we accepted non-linear buffers for the cursor plane. This results in bad output, DC validation failures and oops. Make sure the FB uses a linear layout in the atomic check function. The GFX8- check is inspired from ac_surface_set_bo_metadata in Mesa. The GFX9+ check comes from convert_tiling_flags_to_modifier. Reviewed-by:
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Simon Ser authored
As more checks are added, the indentation makes the code harder to read. Reviewed-by:
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Arnd Bergmann authored
There is still a warning when CONFIG_DEBUG_FS is disabled: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1145:13: error: 'amdgpu_ras_debugfs_create_ctrl_node' defined but not used [-Werror=unused-function] 1145 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) Change the code again to make the compiler actually drop this code but not warn about it. Fixes: ae2bf61f ("drm/amdgpu: guard ras debugfs creation/removal based on CONFIG_DEBUG_FS") Reviewed-by:
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Alex Deucher authored
To avoid a recently added warning: Bogus possible_crtcs: [ENCODER:65:TMDS-65] possible_crtcs=0xf (full crtc mask=0x7) WARNING: CPU: 3 PID: 439 at drivers/gpu/drm/drm_mode_config.c:617 drm_mode_config_validate+0x178/0x200 [drm] In this case the warning is harmless, but confusing to users. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=209123Reviewed-by:
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