- 02 Sep, 2024 32 commits
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Alex Deucher authored
Rather than open coding it for the queue reset. Acked-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Rather than open coding it for the queue reset. Acked-by:
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Alex Deucher authored
Rather than open coding it for the queue reset. Acked-by:
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Alex Deucher authored
It's not supported under SR-IOV at the moment. Acked-by:
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Alex Deucher authored
It's not supported under SR-IOV at the moment. Acked-by:
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Alex Deucher authored
It's not supported under SR-IOV at the moment. Acked-by:
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Jiadong Zhu authored
Implement queue reset for graphic and compute queue. v2: use amdgpu_gfx_rlc funcs to enter/exit safe mode. v3: use gfx_v11_0_request_gfx_index_mutex() v4: fix mutex handling Acked-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by:
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Jiadong Zhu authored
The reset_queue api could be used from kfd or kgd. v2: add use_mmio parameter for mes_reset_legacy_queue. Acked-by:
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Jiadong Zhu authored
Add me/pipe/queue parameters for queue reset input. v2: fix build (Alex) Acked-by:
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Alex Deucher authored
Since the MES FW resets kernel compute queue always failed, this may caused by the KIQ failed to process unmap KCQ. So, before MES FW work properly that will fallback to driver executes dequeue and resets SPI directly. Besides, rework the ring reset function and make the busy ring type reset in each function respectively. Acked-by:
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Alex Deucher authored
Add ring reset callbacks for gfx and compute. Acked-by:
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Alex Deucher authored
To match other GFX IPs. Acked-by:
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Jiadong Zhu authored
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder (Jessie) Acked-by:
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Jiadong Zhu authored
Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. v2: fix up error handling (Alex) Acked-by:
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Alex Deucher authored
Add ring reset callbacks for gfx and compute. v2: fix gfx handling v3: wait for KIQ to complete Acked-by:
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Jiadong Zhu authored
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. Acked-by:
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Alex Deucher authored
Rename to gfx_v11_0_kgq_init_queue() to better align with the other naming in the file. Acked-by:
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Prike Liang authored
Since the MES FW resets kernel compute queue always failed, this may caused by the KIQ failed to process unmap KCQ. So, before MES FW work properly that will fallback to driver executes dequeue and resets SPI directly. Besides, rework the ring reset function and make the busy ring type reset in each function respectively. Acked-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along the following: - DCN35 fixes - DML2 fixes - IPS fixes - ODM fixes - Miscellaneous cleanups - MST fixes - SPL fixes Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Hansen Dsouza authored
Always allow un-gating. Follow legacy workaround for repeated dppclk dto updates Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by:
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Dillon Varone authored
PMO assumes that like timings can be synchronized, but DC only allows this if the signal types match. Reviewed-by:
Austin Zheng <austin.zheng@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Gabe Teeger authored
[what] Graphics hang observed with 3 displays connected to DP2.0 mst dock. [why] There's a mismatch in dml and dc between the assignments of hpo link encoders. [how] Add a new array in dml that tracks the current mapping of HPO stream encoders to HPO link encoders in dc. Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Gabe Teeger <Gabe.Teeger@amd.com> Signed-off-by:
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Relja Vojvodic authored
- Add interface for controlling shapness level input into DCN. - Update SPL to support custom sharpness values. - Add support for different sharpness values depending on YUV/RGB content. Reviewed-by:
Samson Tam <samson.tam@amd.com> Signed-off-by:
Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by:
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Dillon Varone authored
This reverts commit f0b7dcf2. It is causing graphics hangs. Reviewed-by:
Martin Leung <martin.leung@amd.com> Signed-off-by:
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Samson Tam authored
[Why] Certain profiles have higher HDR multiplier than SDR boost max which is not currently supported [How] Disable sharpness for these profiles Fixes: 1b0ce903 ("drm/amd/display: add improvements for text display and HDR DWM and MPO") Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] To provide option to dpia control power management [How] By adding disable_usb4_pm_support bit field in dpia_debug option to control dpia power management Reviewed-by:
Jun Lei <jun.lei@amd.com> Signed-off-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Alex Deucher authored
Add ring reset callbacks for gfx and compute. Acked-by:
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Samson Tam authored
[Why] Previous disable ODM policy due to underflow issue with sharpener. Issue is resolved after updating sharpening policy to apply to both windowed and fullscreen video [How] Remove sharpness check disabling Dynamic ODM policy Reviewed-by:
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Leo Li authored
Backlight updates require aux and/or register access. Therefore, driver needs to disallow IPS beforehand. So, acquire the dc lock before calling into dc to update backlight - we should be doing this regardless of IPS. Then, while the lock is held, disallow IPS before calling into dc, then allow IPS afterwards (if it was previously allowed). Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Daniel Sa authored
[Why] Some asserts are always hit on startup/Pnp when they should only be used to indicate when something has gone wrong. [How] Ignore result of getting function from bios cmd table for newer asics. Reviewed-by:
Daniel Sa <Daniel.Sa@amd.com> Signed-off-by:
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Nicholas Susanto authored
[Why] Setting min dispclk to 50Mhz outside clock lowering function causes unnecessary calls to SMU to lower dispclk and causes dentist hangs when there is no stream on the pipes. [How] Move the set minimum dispclk logic inside the lowering dispclk if statement. Fixes: 23444132 ("DCN35 set min dispclk to 50Mhz") Reviewed-by:
Nicholas Susanto <Nicholas.Susanto@amd.com> Signed-off-by:
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Prike Liang authored
Implement the compute pipe reset, and the driver will fallback to pipe reset when queue reset fails. The pipe reset only deactivates the queue which is scheduled in the pipe, and meanwhile the MEC pipe will be reset to the firmware _start pointer. So, it seems pipe reset will cost more cycles than the queue reset; therefore, the driver tries to recover by doing queue reset first. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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- 29 Aug, 2024 8 commits
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Alex Deucher authored
This adds allocation latency, but aligns better with user expectations. The latency should improve with the drm buddy clearing patches that Arun has been working on. In addition this fixes the high CPU spikes seen when doing wipe on release. v2: always set AMDGPU_GEM_CREATE_VRAM_CLEARED (Christian) Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3528 Fixes: a68c7eaa ("drm/amdgpu: Enable clear page functionality") Acked-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> (v1) Signed-off-by:
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Jack Xiao authored
For mes11 old firmware has issue to map legacy queue, add a flag to switch mes to map legacy queue. Fixes: f9d8c5c7 ("drm/amdgpu/gfx: enable mes to map legacy queue support") Reported-by:
Andrew Worsley <amworsley@gmail.com> Link: https://lists.freedesktop.org/archives/amd-gfx/2024-August/112773.htmlSigned-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Yifan Zhang authored
ih1 is not initialized for APUs. Don't drain it or NULL pointer error will be triggered. Fixes: 6ef29715 ("drm/amdkfd: Change kfd/svm page fault drain handling") Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Alex Deucher authored
When MES is enabled KIQ is not available. Return an error when someone uses the debugfs preempt test interface in that case. Acked-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by:
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Alex Deucher authored
When MES is enabled KIQ is not available. Return an error when someone uses the debugfs preempt test interface in that case. Acked-by:
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Leo Li authored
[Why] DCN IPS interoperates with other system idle power features, such as Zstates. On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a hard hang. We observe this on systems where the SBIOS allows Z8. Though there is a SBIOS fix, there's no guarantee that users will get it any time soon, or even install it. A workaround is needed to prevent this from rearing its head in the wild. [How] For DCN35, check the pmfw version to determine whether the SBIOS has the fix. If not, set IPS1+RCG as the deepest possible state in all cases except for s0ix and display off (DPMS). Otherwise, enable all IPS Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Sunil Khatri authored
log message "Dumping IP State Completed" needs to be logged only once when state dumping is complete. Hence moving it out of the for loop. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Acked-by:
Trigger Huang <Trigger.Huang@amd.com> Signed-off-by:
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Victor Zhao authored
[background] when unloading amdgpu driver right after running a workload, drain_workqueue is causing "Fence fallback timer expired on ring sdma0.0". Under sriov, this issue will cause sriov full access timeout and a reset happening. move drain_workqueue before shutdown is set to allow ih process and before enter full access under sriov to avoid full access time cost. Signed-off-by:
Victor Zhao <Victor.Zhao@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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