1. 09 May, 2016 21 commits
    • Yanjiang Jin's avatar
      MIPS: oprofile: Fix a preemption issue · fa0c879f
      Yanjiang Jin authored
      Use boot_cpu_type() instead of current_cpu_type() in oprofile_arch_init()
      to avoid the below warning, cpu_type is normally consistent in a MIPS SMP
      system.  There are a few exceptions such as SGI servers where it is
      possible to mix R10000, R12000, R14000 and R16000 within certain
      constraints.  Let's not worry about those now.
      
      BUG: using smp_processor_id() in preemptible [00000000] code: insmod/952
      caller is oprofile_arch_init+0x30/0x194 [oprofile]
      CPU: 5 PID: 952 Comm: insmod Not tainted 4.1.13-WR8.0.0.0_standard #1
      Stack : ffffffff80c10000 0000000000000001 8000000025bf0790 ffffffff80e10000
      	  ffffffff80e50000 ffffffff80254e2c ffffffff80b64428 ffffffff80e10790
      	  0000000000000000 ffffffff801caeb8 0000000000000045 0000000000000005
      	  ffffffff80c10000 ffffffff801cb798 0000000000000000 ffffffff80e30000
      	  0000000000000000 ffffffff801ff1c0 ffffffff80e2d2f8 000000000000000b
      	  ffffffff801cbba0 ffffffff80e107b0 ffffffff80a77828 0000000000000005
      	  00000000000003b8 ffffffff80e2d2f8 800000040ad39960 ffffffff801f9950
      	  0000000000000124 80000004093b7990 80000004093b7ab8 ffffffff80925108
      	  ffffffff80b69a07 ffffffff80a6f0d0 8000000407240e00 ffffffff801cc934
      	  000000000000005d ffffffff80159080 0000000000000005 00000000000003b8
      	  ...
      Call Trace:
      [<ffffffff80159080>] show_stack+0xe8/0x108
      [<ffffffff80925108>] dump_stack+0x8c/0xd8
      [<ffffffff80606570>] check_preemption_disabled+0x110/0x118
      [<ffffffffc0086104>] oprofile_arch_init+0x30/0x194 [oprofile]
      [<ffffffffc008602c>] oprofile_init+0x2c/0xc0 [oprofile]
      [<ffffffff80100550>] do_one_initcall+0xa0/0x1c0
      [<ffffffff80921e04>] do_init_module+0x80/0x1d8
      [<ffffffff801fd0d4>] load_module+0x1b74/0x2278
      [<ffffffff801fdab4>] SyS_finit_module+0xcc/0xf0
      [<ffffffff80165884>] handle_sysn32+0x44/0x70
      
      [ralf@linux-mips.org: Correct commit message.]
      Signed-off-by: default avatarYanjiang Jin <yanjiang.jin@windriver.com>
      Cc: rric@kernel.org
      Cc: jinyanjiang@gmail.com
      Cc: linux-mips@linux-mips.org
      Cc: oprofile-list@lists.sf.net
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/11769/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      fa0c879f
    • Huacai Chen's avatar
      MIPS: Loongson-3: Fix build error after ld-version.sh modification · 820880cd
      Huacai Chen authored
      Commit d5ece1cb ("Fix ld-version.sh to handle large 3rd version
      part") modifies the ld version description. This causes a build error
      on Loongson-3, so fix it.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J . Hill <sjhill@realitydiluted.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/12890/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      820880cd
    • Huacai Chen's avatar
      MIPS: Loongson-3: Reserve 32MB for RS780E integrated GPU · 3484de7b
      Huacai Chen authored
      Due to datasheet, reserving 0xff800000~0xffffffff (8MB below 4GB) is
      not enough for RS780E integrated GPU's TOM (top of memory) registers
      and MSI/MSI-x memory region, so we reserve 0xfe000000~0xffffffff (32MB
      below 4GB).
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J . Hill <sjhill@realitydiluted.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/12889/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      3484de7b
    • Huacai Chen's avatar
      MIPS: Reserve nosave data for hibernation · a95d0692
      Huacai Chen authored
      After commit 92923ca3 ("mm: meminit: only set page reserved
      in the memblock region"), the MIPS hibernation is broken. Because pages
      in nosave data section should be "reserved", but currently they aren't
      set to "reserved" at initialization. This patch makes hibernation work
      again.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J . Hill <sjhill@realitydiluted.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/12888/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      a95d0692
    • Andreas Ruprecht's avatar
      MIPS: Sibyte: Fix Kconfig dependencies of SIBYTE_BUS_WATCHER · 54292850
      Andreas Ruprecht authored
      Commit 6793f55c ("MIPS: sibyte: Amend dependencies for
      SIBYTE_BUS_WATCHER") changed the dependencies for
      SIBYTE_BUS_WATCHER to make it visible only if SIBYTE_BCM112X
      or SIBYTE_SB1250 are enabled.
      
      In the code in arch/mips/sibyte/common/bus_watcher, however,
      a #if defined() check suggests that this functionality should
      also be available for SIBYTE_BCM1x55 and SIBYTE_BCM1x80.
      
      Make it selectable by extending the dependencies of
      SIBYTE_BUS_WATCHER in arch/mips/sibyte/Kconfig.
      Reported-by: default avatarJonas Rabenstein <jonas.rabenstein@studium.uni-erlangen.de>
      Signed-off-by: default avatarAndreas Ruprecht <andreas.ruprecht@fau.de>
      Cc: valentinrothberg@gmail.com
      Cc: stefan.hengelein@fau.de
      Cc: pebolle@tiscali.nl
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/10736/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      54292850
    • James Hogan's avatar
      MIPS: I6400: Icache fills from dcache · 47f2ac50
      James Hogan authored
      Coherence Manager 3 (CM3) as present in I6400 can fill icache lines
      effectively from dirty dcaches, so there is no need to flush dirty lines
      from dcaches through to L2 prior to icache invalidation.
      
      Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc
      evaluates to true, which avoids those dcache flushes.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
      Cc: Manuel Lauss <manuel.lauss@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12180/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      47f2ac50
    • James Hogan's avatar
      MIPS: c-r4k: Sync icache when it fills from dcache · b2a3c5be
      James Hogan authored
      It is still necessary to handle icache coherency in flush_cache_range()
      and copy_to_user_page() when the icache fills from the dcache, even
      though the dcache does not need to be written back. However when this
      handling was added in commit 2eaa7ec2 ("[MIPS] Handle I-cache
      coherency in flush_cache_range()"), it did not do any icache flushing
      when it fills from dcache.
      
      Therefore fix r4k_flush_cache_range() to run
      local_r4k_flush_cache_range() without taking into account whether icache
      fills from dcache, so that the icache coherency gets handled. Checks are
      also added in local_r4k_flush_cache_range() so that the dcache blast
      doesn't take place when icache fills from dcache.
      
      A test to mmap a page PROT_READ|PROT_WRITE, modify code in it, and
      mprotect it to VM_READ|VM_EXEC (similar to case described in above
      commit) can hit this case quite easily to verify the fix.
      
      A similar check was added in commit f8829cae ("[MIPS] Fix aliasing
      bug in copy_to_user_page / copy_from_user_page"), so also fix
      copy_to_user_page() similarly, to call flush_cache_page() without taking
      into account whether icache fills from dcache, since flush_cache_page()
      already takes that into account to avoid performing a dcache flush.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
      Cc: Manuel Lauss <manuel.lauss@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12179/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b2a3c5be
    • James Hogan's avatar
      MIPS: Enable ptrace hw watchpoints on MIPS R6 · 679eb637
      James Hogan authored
      HARDWARE_WATCHPOINTS isn't being enabled for CPU_MIPSR6, even though it
      has an identical hardware watchpoint interface to CPU_MIPSR2, which
      prevents ptrace watchpoints from being loaded when executing a ptraced
      process even though the watchpoints are described in /proc/cpuinfo.
      
      Enable HARDWARE_WATCHPOINTS for CPU_MIPSR6 too.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12727/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      679eb637
    • James Hogan's avatar
      MIPS: Fix watchpoint restoration · a7e89326
      James Hogan authored
      Commit f51246ef ("MIPS: Get rid of finish_arch_switch().") moved the
      __restore_watch() call from finish_arch_switch() (i.e. after resume()
      returns) to before the resume() call in switch_to(). This results in
      watchpoints only being restored when a task is descheduled, preventing
      the watchpoints from being effective most of the time, except due to
      chance before the watchpoints are lazily removed.
      
      Fix the call sequence from switch_to() through to
      mips_install_watch_registers() to pass the task_struct pointer of the
      next task, instead of using current. This allows the watchpoints for the
      next (non-current) task to be restored without reintroducing
      finish_arch_switch().
      
      Fixes: f51246ef ("MIPS: Get rid of finish_arch_switch().")
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 4.3.x-
      Patchwork: https://patchwork.linux-mips.org/patch/12726/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      a7e89326
    • James Hogan's avatar
      MIPS: Avoid using unwind_stack() with usermode · 81a76d71
      James Hogan authored
      When showing backtraces in response to traps, for example crashes and
      address errors (usually unaligned accesses) when they are set in debugfs
      to be reported, unwind_stack will be used if the PC was in the kernel
      text address range. However since EVA it is possible for user and kernel
      address ranges to overlap, and even without EVA userland can still
      trigger an address error by jumping to a KSeg0 address.
      
      Adjust the check to also ensure that it was running in kernel mode. I
      don't believe any harm can come of this problem, since unwind_stack() is
      sufficiently defensive, however it is only meant for unwinding kernel
      code, so to be correct it should use the raw backtracing instead.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Reviewed-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 3.15+
      Patchwork: https://patchwork.linux-mips.org/patch/11701/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      (cherry picked from commit d2941a975ac745c607dfb590e92bb30bc352dad9)
      81a76d71
    • James Hogan's avatar
      MIPS: Don't unwind to user mode with EVA · a816b306
      James Hogan authored
      When unwinding through IRQs and exceptions, the unwinding only continues
      if the PC is a kernel text address, however since EVA it is possible for
      user and kernel address ranges to overlap, potentially allowing
      unwinding to continue to user mode if the user PC happens to be in the
      kernel text address range.
      
      Adjust the check to also ensure that the register state from before the
      exception is actually running in kernel mode, i.e. !user_mode(regs).
      
      I don't believe any harm can come of this problem, since the PC is only
      output, the stack pointer is checked to ensure it resides within the
      task's stack page before it is dereferenced in search of the return
      address, and the return address register is similarly only output (if
      the PC is in a leaf function or the beginning of a non-leaf function).
      
      However unwind_stack() is only meant for unwinding kernel code, so to be
      correct the unwind should stop there.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Reviewed-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 3.15+
      Patchwork: https://patchwork.linux-mips.org/patch/11700/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      a816b306
    • Florian Fainelli's avatar
      MIPS: BMIPS: Fill in current_cpu_data.core · f6cc0ee9
      Florian Fainelli authored
      Read the core ID in bmips_smp_finish() for BMIPS5000 CPUs to get appropriate
      processor parenting in set_cpu_sibling_map().
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Cc: john@phrozen.org
      Cc: cernekee@gmail.com
      Cc: jon.fraser@broadcom.com
      Cc: jaedon.shin@gmail.com
      Cc: dragan.stancevic@gmail.com
      Cc: jogo@openwrt.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12380/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f6cc0ee9
    • Florian Fainelli's avatar
      MIPS: BMIPS: Remove maxcpus from BCM97435SVMB DTS · 904c3b49
      Florian Fainelli authored
      Now that SMP properly works on 7435, do not restrict the number of core,
      unleash them all.
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Cc: john@phrozen.org
      Cc: cernekee@gmail.com
      Cc: jon.fraser@broadcom.com
      Cc: jaedon.shin@gmail.com
      Cc: dragan.stancevic@gmail.com
      Cc: jogo@openwrt.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12379/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      904c3b49
    • Florian Fainelli's avatar
      MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435 · a5b143ec
      Florian Fainelli authored
      7435 has 4 7038 L1 base register address for each of its Core + TP (for a total
      of 4 threads of execution), add the two missing cells for Core 1. We are
      providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they
      are, and we can later decide to remap these in software to provide proper
      interrupt affinity/parenting.
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Cc: john@phrozen.org
      Cc: cernekee@gmail.com
      Cc: jon.fraser@broadcom.com
      Cc: jaedon.shin@gmail.com
      Cc: dragan.stancevic@gmail.com
      Cc: jogo@openwrt.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12378/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      a5b143ec
    • Ralf Baechle's avatar
      MIPS: BMIPS: Make whitespacely correct. · f241265f
      Ralf Baechle authored
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f241265f
    • Florian Fainelli's avatar
      MIPS: BMIPS: Add Whirlwind (BMIPS5200) initialization code · 21b30c00
      Florian Fainelli authored
      Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this
      would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX
      and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor
      id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to
      bring them online.
      
      Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some
      additional changes in the L1 interrupt area to work properly with interrupt
      affinity.
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: john@phrozen.org
      Cc: cernekee@gmail.com
      Cc: jon.fraser@broadcom.com
      Cc: jaedon.shin@gmail.com
      Cc: dragan.stancevic@gmail.com
      Cc: jogo@openwrt.org
      Patchwork: https://patchwork.linux-mips.org/patch/12377/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      21b30c00
    • Florian Fainelli's avatar
      MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200 · cbbda6e7
      Florian Fainelli authored
      BMIPS5000 have a PrID value of 0x5A00 and BMIPS5200 have a PrID value of
      0x5B00, which, masked with 0x5A00, returns 0x5A00. Update all conditionals on
      the PrID to cover both variants since we are going to need this to enable
      BMIPS5200 SMP. The existing check, masking with 0xFF00 would not cover
      BMIPS5200 at all.
      
      Fixes: 68e6a783 ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)")
      Fixes: 6465460c ("MIPS: BMIPS: change compile time checks to runtime checks")
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Cc: john@phrozen.org
      Cc: cernekee@gmail.com
      Cc: jogo@openwrt.org
      Cc: jaedon.shin@gmail.com
      Cc: jfraser@broadcom.com
      Cc: pgynther@google.com
      Cc: dragan.stancevic@gmail.com
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12279/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      cbbda6e7
    • Paul Burton's avatar
      MIPS: Don't BUG_ON when no IPI domain is found · 578bffc8
      Paul Burton authored
      Commit fbde2d7d ("MIPS: Add generic SMP IPI support") introduced
      code that BUG_ON's in the case of a kernel that supports IPI domains but
      does not have one at runtime. This case is possible on Malta where for
      IPIs we may use either the GIC (which has an IPI IRQ domain
      implementation) or core-local software interrupts between VPEs (which do
      not currently have an IPI IRQ domain implementation). We can not know
      which will be used until runtime when we know whether a GIC is actually
      present, and if we run on a system with multiple VPEs and no GIC then
      the BUG_ON is hit.
      
      Commit 19fb5818 ("IPS: Fix broken malta qemu") worked around this
      for the single-core single-VPE case typically seen using QEMU, but does
      not catch the multi-VPE case. This patch removes the insufficient CPU
      presence check that was added and works around the bug differently,
      effectively reverting that commit.
      
      A simple way to reproduce this bug is by using QEMU, which partially
      implements the MT ASE but does not implement the GIC as of version 2.5.
      Using "-cpu 34Kf -smp 2" will present a system with 2 VPEs in one core &
      no GIC, hitting the BUG_ON.
      
      Given that we're post-merge-window on the way to v4.6, avoid this by
      just returning from mips_smp_ipi_init when no IPI IRQ domain is found.
      Ideally at some point all IPI implementations would be converted to the
      same IPI IRQ domain interface & we'd be able to restore the check.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Qais Yousef <qsyousef@gmail.com>
      Fixes: fbde2d7d ("MIPS: Add generic SMP IPI support")
      Fixes: 19fb5818 ("IPS: Fix broken malta qemu")
      Reverts: 19fb5818 ("IPS: Fix broken malta qemu")
      Cc: Qais Yousef <qsyousef@gmail.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Alex Smith <alex.smith@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/13007/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      578bffc8
    • James Hogan's avatar
      MIPS: Fix siginfo.h to use strict posix types · 5daebc47
      James Hogan authored
      Commit 85efde6f ("make exported headers use strict posix types")
      changed the asm-generic siginfo.h to use the __kernel_* types, and
      commit 3a471cbc ("remove __KERNEL_STRICT_NAMES") make the internal
      types accessible only to the kernel, but the MIPS implementation hasn't
      been updated to match.
      
      Switch to proper types now so that the exported asm/siginfo.h won't
      produce quite so many compiler errors when included alone by a user
      program.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Christopher Ferris <cferris@google.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 2.6.30-
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/12477/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      5daebc47
    • Corey Minyard's avatar
      MIPS: Fix crash registers on non-crashing CPUs · c80e1b62
      Corey Minyard authored
      As part of handling a crash on an SMP system, an IPI is send to
      all other CPUs to save their current registers and stop.  It was
      using task_pt_regs(current) to get the registers, but that will
      only be accurate if the CPU was interrupted running in userland.
      Instead allow the architecture to pass in the registers (all
      pass NULL now, but allow for the future) and then use get_irq_regs()
      which should be accurate as we are in an interrupt.  Fall back to
      task_pt_regs(current) if nothing else is available.
      Signed-off-by: default avatarCorey Minyard <cminyard@mvista.com>
      Cc: David Daney <ddaney@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/13050/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      c80e1b62
    • Nikolay Martynov's avatar
      mips: Fix CPC_BASE_ADDR mask to match datasheet · e03ac9f0
      Nikolay Martynov authored
      According to 'MIPS32® interAptivTM Multiprocessing
      System Programmer’s Guide' CPC_BASE_ADDR takes bits [31:15].
      
      This change is tested ith mt7621 which wasn't working without it.
      Signed-off-by: default avatarNikolay Martynov <mar.kolya@gmail.com>
      Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/11766/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e03ac9f0
  2. 08 May, 2016 1 commit
  3. 07 May, 2016 7 commits
  4. 06 May, 2016 11 commits