- 07 Sep, 2020 38 commits
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Matthias Schiffer authored
As with GPIO, UART and others, allow specifying the device index via the aliases node in the device tree. On embedded devices, there is often a combination of removable (e.g. SD card) and non-removable MMC devices (e.g. eMMC). Therefore the index might change depending on * host of removable device * removable card present or not This makes it difficult to hardcode the root device, if it is on the non-removable device. E.g. if SD card is present eMMC will be mmcblk1, if SD card is not present at boot, eMMC will be mmcblk0. Alternative solutions like PARTUUIDs do not cover the case where multiple mmcblk devices contain the same image. This is a common issue on devices that can boot both from eMMC (for regular boot) and SD cards (as a temporary boot medium for development). When a firmware image is installed to eMMC after a test boot via SD card, there will be no reliable way to refer to a specific device using (PART)UUIDs oder LABELs. The demand for this feature has led to multiple attempts to implement it, dating back at least to 2012 (see https://www.spinics.net/lists/linux-mmc/msg26586.html for a previous discussion from 2014). All indices defined in the aliases node will be reserved for use by the respective MMC device, moving the indices of devices that don't have an alias up into the non-reserved range. If the aliases node is not found, the driver will act as before. This is a rebased and cleaned up version of https://www.spinics.net/lists/linux-mmc/msg26588.html . Based-on-patch-by:
Sascha Hauer <s.hauer@pengutronix.de> Link: https://lkml.org/lkml/2020/8/5/194Signed-off-by:
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20200901085004.2512-2-matthias.schiffer@ew.tq-group.comSigned-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Matthias Schiffer authored
As for I2C and SPI, it now is possible to reserve a fixed index for mmc/mmcblk devices. Signed-off-by:
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Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200831102324.12566-1-wsa+renesas@sang-engineering.comSigned-off-by:
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Krzysztof Kozlowski authored
There might be multiple reset GPIOs but dtschema has trouble parsing it if there are no maxItems: arch/arm/boot/dts/exynos5250-snow.dt.yaml: mmc3_pwrseq: reset-gpios: [[20, 2, 1], [20, 1, 1]] is too long From schema: Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200831161147.13515-2-krzk@kernel.orgSigned-off-by:
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Krzysztof Kozlowski authored
The i.MX 8 DTSes use two compatibles so update the binding to fix dtbs_check warnings like: arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: mmc@30b40000: compatible: ['fsl,imx8mn-usdhc', 'fsl,imx7d-usdhc'] is too long From schema: Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: mmc@30b40000: compatible: Additional items are not allowed ('fsl,imx7d-usdhc' was unexpected) arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dt.yaml: mmc@30b40000: compatible: ['fsl,imx8mn-usdhc', 'fsl,imx7d-usdhc'] is too long Signed-off-by: -
Stefan Wahren authored
The emmc2 interface on the bcm2711 supports DDR modes for eMMC devices running at 3.3V. This allows to run eMMC module with 3.3V signaling voltage at DDR52 mode on the Raspberry Pi 4 using a SD adapter: clock: 52000000 Hz actual clock: 50000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 8 (mmc DDR52) signal voltage: 0 (3.30 V) driver type: 0 (driver type B) Link: https://github.com/raspberrypi/linux/issues/3802Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Link: https://lore.kernel.org/r/1598651234-29826-1-git-send-email-stefan.wahren@i2se.comSigned-off-by:
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Chun-Hung Wu authored
CQHCI_ENABLE bit in CQHCI_CFG should be disabled after msdc_cqe_disable(), and should be enabled before msdc_ceq_enable() for MTK platform. Add hook functions for cqhci_host_ops->pre_enable() and cqhci_host_ops->post_disable(). Signed-off-by:
Chun-Hung Wu <chun-hung.wu@mediatek.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1598520783-25250-3-git-send-email-chun-hung.wu@mediatek.comSigned-off-by:
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Chun-Hung Wu authored
Add pre_enable() and post_disable() for cqhci_host_ops. Add hook functions before cqhci enable and after cqhci disable for platforms need them. Signed-off-by:
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Veerabhadrarao Badiganti authored
On sc7180 target, issues are observed with HS400 mode due to a hardware limitation. If sdcc clock is dynamically gated and ungated, the very next command is failing with command CRC/timeout errors. To mitigate this issue, DLL phase has to be restored whenever sdcc clock is gated dynamically. The restore_dll_config ensures this. Enabling this flag with this change. And simply re-using the sdm845 target configuration for this flag. Signed-off-by:
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Tested-by:
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Wolfram Sang authored
After all the previous refactorization, we can now populate mmc_ops directly and don't need a layer inbetween. The NULL-pointer check and the error printout are already done by the MMC core. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by:
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Wolfram Sang authored
SDHI needs to reset the SCC only, not the whole IP core. So, if tuning fails, don't handle specifics in the generic TMIO core, but in the specific drivers. For SDHI, we need to move around the reset routine a bit. It is not modified. Signed-off-by:
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Wolfram Sang authored
Some TMIO variants need specific actions in their reset routine, but they are all based on a generic reset routine. So, the optional 'reset' callback will now only take care of the additional stuff and we will have a generic function around it. Less code, easier to maintain, and much more readable. Code in tmio_mmc.c is untested but in my TC6387XB datasheet the SDIO part is reset independently from the SD part, too. Signed-off-by:
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Wolfram Sang authored
After Yamada-san's refactorization introducing 'tmio_mmc_host_alloc', we can populate mmc_ops directly and don't need a layer inbetween. Signed-off-by:
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Wolfram Sang authored
This reverts commit a87852c6. It did fix the issue, but was building on top of already wrong assumptions. The driver missed that 'hw_reset' was only for resetting remote HW (card) and not for the IP core. Since we fixed that in a previous patch, we can now remove this patch to make it clear that 'reset' is for resetting the IP core only. Also, cancelling DMA will only be called when actually needed again. It will also allow for further cleanups and better readability. Note that in addition to the revert, the call in 'tmio_mmc_execute_tuning' will be converted, too, to maintain the current behaviour. Signed-off-by:
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Wolfram Sang authored
This driver got the usage of 'hw_reset' wrong and missed that it is used to reset the remote HW (card) only, not the local one (controller). Move everything to the proper 'reset' callback. Also, add the generic reset code from TMIO, so we will ensure the same behaviour (it will get refactored away in a later patch). This also means we need to drop MMC_CAP_HW_RESET because this is currently not supported by our hardware. Signed-off-by:
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Faiz Abbas authored
There is a one time delay because of a card detect debounce timer in the controller IP. This timer runs as soon as power is applied to the module regardless of whether a card is present or not and any writes to SDHCI_POWER_ON will return 0 before it expires. This timeout has been measured to be about 1 second in am654x and j721e. Write-and-read-back in a loop on SDHCI_POWER_ON for a maximum of 1.5 seconds to make sure that the controller actually powers on. Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200825170015.32285-1-faiz_abbas@ti.comSigned-off-by:
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Alex Dewar authored
There seems to be no particular reason to only test for ARM, so allow for build-testing on other platforms to increase coverage. Build-tested on x86 with allyesconfig. Signed-off-by:
Alex Dewar <alex.dewar90@gmail.com> Link: https://lore.kernel.org/r/20200824171854.406157-1-alex.dewar90@gmail.comSigned-off-by:
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Haibo Chen authored
Value assigned to a variable(err) is never used, so remove it. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
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Tian Tao authored
Use kobj_to_dev() instead of container_of() Signed-off-by:
Tian Tao <tiantao6@hisilicon.com> Link: https://lore.kernel.org/r/1598230956-58523-1-git-send-email-tiantao6@hisilicon.comSigned-off-by:
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Lars Povlsen authored
This adds the eMMC driver for the Sparx5 SoC. It is based upon the designware IP, but requires some extra initialization and quirks. Signed-off-by:
Lars Povlsen <lars.povlsen@microchip.com> Acked-by:
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Lars Povlsen authored
The Sparx5 SDHCI controller is based on the Designware controller IP. Signed-off-by:
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Madhuparna Bhowmik authored
via_save_pcictrlreg() should be called with host->lock held as it writes to pm_pcictrl_reg, otherwise there can be a race condition between via_sd_suspend() and via_sdc_card_detect(). The same pattern is used in the function via_reset_pcictrl() as well, where via_save_pcictrlreg() is called with host->lock held. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by:
Madhuparna Bhowmik <madhuparnabhowmik10@gmail.com> Link: https://lore.kernel.org/r/20200822061528.7035-1-madhuparnabhowmik10@gmail.comSigned-off-by:
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Wolfram Sang authored
MMC_CAP_HW_RESET means that the controller is capable of resetting the eMMC device via RST_n signal, not a reset of the controller. Two drivers got this wrong, so let's make it more clear. Signed-off-by:
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Adrian Hunter authored
Some Intel BYT based host controllers support the setting of latency tolerance. Accordingly, implement the PM QoS ->set_latency_tolerance() callback. The raw register values are also exposed via debugfs. Intel EHL controllers require this support. Signed-off-by:
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Wolfram Sang authored
When reading the test description, I thought a correction of the xfer_size was tested, which is not the case. It is tested that the xfer_size is correct. Use 'proper xfer_size' to remove this ambiguity. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200817115838.2981-1-wsa@kernel.orgSigned-off-by:
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Tobias Schramm authored
Previously the cycle timeout was converted to a microsecond value but then incorrectly treated as a nanosecond timeout. This patch changes the code to convert both the nanosecond timeout and the cycle timeout to a microsecond value and use that directly. Signed-off-by:
Tobias Schramm <t.schramm@manjaro.org> Link: https://lore.kernel.org/r/20200814185011.3252020-1-t.schramm@manjaro.orgSigned-off-by:
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Pali Rohár authored
For SDIO functions, SDIO cards and SD COMBO cards are exported revision number and info strings from CISTPL_VERS_1 structure. Revision number should indicate compliance of standard and info strings should contain product information in same format as product information for PCMCIA cards. Product information for PCMCIA cards should contain following strings in this order: Manufacturer, Product Name, Lot number, Programming Conditions. Note that not all SDIO cards export all those info strings in that order as described in PCMCIA Metaformat Specification. Signed-off-by:
Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20200727133837.19086-5-pali@kernel.orgSigned-off-by:
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Pali Rohár authored
This simplify code for generating sdio config attributes and allows easily define new sdio attributes. Signed-off-by:
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Pali Rohár authored
They should indicate compliance of standard. Signed-off-by:
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Pali Rohár authored
Before parsing CISTPL_VERS_1 structure check that its size is at least two bytes to prevent buffer overflow. Signed-off-by:
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Haibo Chen authored
According to IC suggestion, everytime before sending the tuning command, need to reset the usdhc, so to reset the tuning circuit, to let every tuning command work well for the manual tuning method. For standard tuning method, IC already add the reset operation in the hardware logic. Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a debug message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200810080247.47024-1-colin.king@canonical.comSigned-off-by:
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Lad Prabhakar authored
Document SDHI controller for RZ/G2H (R8A774E1) SoC, which is compatible with R-Car Gen3 SoC family. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200809192001.19156-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Guo Ren authored
Synopsys DesignWare MMC controller could be used in RISC-V and C-SKY architectures. Signed-off-by:
Guo Ren <guoren@linux.alibaba.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/1596887102-9743-1-git-send-email-guoren@kernel.orgSigned-off-by:
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Krzysztof Kozlowski authored
Remove empty comment to fix W=1 compile warning: drivers/mmc/host/s3cmci.c:400: warning: Cannot understand * on line 400 - I thought it was a doc line Signed-off-by: -
Faiz Abbas authored
Add binding documentation for mmc host controllers present on TI's J7200 SOC Signed-off-by:
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Alexander A. Klimov authored
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by:Alexander A. Klimov <grandmaster@al2klimov.de> Acked-by:
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Linus Torvalds authored
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- 06 Sep, 2020 2 commits
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git://git.kernel.dk/linux-blockLinus Torvalds authored
Pull more io_uring fixes from Jens Axboe: "Two followup fixes. One is fixing a regression from this merge window, the other is two commits fixing cancelation of deferred requests. Both have gone through full testing, and both spawned a few new regression test additions to liburing. - Don't play games with const, properly store the output iovec and assign it as needed. - Deferred request cancelation fix (Pavel)" * tag 'io_uring-5.9-2020-09-06' of git://git.kernel.dk/linux-block: io_uring: fix linked deferred ->files cancellation io_uring: fix cancel of deferred reqs with ->files io_uring: fix explicit async read/write mapping for large segments -
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommuLinus Torvalds authored
Pull iommu fixes from Joerg Roedel: - three Intel VT-d fixes to fix address handling on 32bit, fix a NULL pointer dereference bug and serialize a hardware register access as required by the VT-d spec. - two patches for AMD IOMMU to force AMD GPUs into translation mode when memory encryption is active and disallow using IOMMUv2 functionality. This makes the AMDGPU driver work when memory encryption is active. - two more fixes for AMD IOMMU to fix updating the Interrupt Remapping Table Entries. - MAINTAINERS file update for the Qualcom IOMMU driver. * tag 'iommu-fixes-v5.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/vt-d: Handle 36bit addressing for x86-32 iommu/amd: Do not use IOMMUv2 functionality when SME is active iommu/amd: Do not force direct mapping when SME is active iommu/amd: Use cmpxchg_double() when updating 128-bit IRTE iommu/amd: Restore IRTE.RemapEn bit after programming IRTE iommu/vt-d: Fix NULL pointer dereference in dev_iommu_priv_set() iommu/vt-d: Serialize IOMMU GCMD register modifications MAINTAINERS: Update QUALCOMM IOMMU after Arm SMMU drivers move
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