- 06 Dec, 2023 6 commits
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Michael Strauss authored
[WHY] Many DCN generations only have two HPO link encoders and therefore only support driving a max of two DP2 PHYs. DP2 MST hubs currently can not pass 3x display validation as each downstream sink is enumerated as separate DP2 output. [HOW] Count MST hubs once by treating only 1st remote sink in topology as an encoder. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Relja Vojvodic authored
[why] When querying DML for a vlevel after pipes have been split or merged the ODM policy would revert to a default policy, which could cause the query to use the incorrect ODM status. In this case ODM 2to1 was validated, but the last DML query would assume no ODM and return the incorrect vlevel. [how] Added ODM check to apply the correct ODM policy before querying DML. Tested-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Relja Vojvodic <relja.vojvodic@amd.com> Signed-off-by:
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Charlene Liu authored
Fix issue when override level bigger than default. Levels 5, 6, and 7 had zero stutter latency, this is because override level being initialized after stutter latency inits. Tested-by:
Syed Hassan <syed.hassan@amd.com> Reviewed-by:
Allen Pan <allen.pan@amd.com> Acked-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
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Alvin Lee authored
Optimize fast validation cases to only validate the highest voltage level. This works because during fast validation we only care if the mode can be supported or not (at any vlevel). Tested-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Bokun Zhang authored
- Move VCN4's fw_shared initialization to a separated function. This way, the function can be reused at different locations. Signed-off-by:
Bokun Zhang <bokun.zhang@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Jiadong Zhu authored
Disable MCBP(mid command buffer preemption) by default as old Mesa hangs with it. We shall not enable the feature that breaks old usermode driver. Fixes: 50a7c876 ("drm/amdgpu: enable mcbp by default on gfx9") Signed-off-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Acked-by:
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- 05 Dec, 2023 1 commit
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.8-2023-12-01: amdgpu: - Add new 64 bit sequence number infrastructure. This will ultimately be used for user queue synchronization. - GPUVM updates - Misc code cleanups - RAS updates - DCN 3.5 updates - Rework PCIe link speed handling - Document GPU reset types - DMUB fixes - eDP fixes - NBIO 7.9 updates - NBIO 7.11 updates - SubVP updates - DCN 3.1.4 fixes - ABM fixes - AGP aperture fix - DCN 3.1.5 fix - Fix some potential error path memory leaks - Enable PCIe PMEs - Add XGMI, PCIe state dumping for aqua vanjaram - GFX11 golden register updates - Misc display fixes amdkfd: - Migrate TLB flushing logic to amdgpu - Trap handler fixes - Fix restore workers handling on suspend and reset - Fix possible memory leak in pqm_uninit() radeon: - Fix some possible overflows in command buffer checking - Check for errors in ring_lock From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231201181743.5313-1-alexander.deucher@amd.comSigned-off-by:
Dave Airlie <airlied@redhat.com>
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- 30 Nov, 2023 8 commits
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Mario Limonciello authored
During hibernate sequence the source context might not have a clk_mgr. So don't use it to look for DML2 support. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2980 Fixes: 7966f319 ("drm/amd/display: Introduce DML2") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Nikita Zhandarovich authored
In the unlikely event of radeon_ring_lock() failing, its errno return value should be processed. This patch checks said return value and prints a debug message in case of an error. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 48c0c902 ("drm/radeon/kms: add support for CP setup on SI") Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Nikita Zhandarovich authored
It may be possible, albeit unlikely, to encounter integer overflow during the multiplication of several unsigned int variables, the result being assigned to a variable 'size' of wider type. Prevent this potential behaviour by converting one of the multiples to unsigned long. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 0242f74d ("drm/radeon: clean up CS functions in r100.c") Signed-off-by:
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Nikita Zhandarovich authored
While improbable, there may be a chance of hitting integer overflow when the result of radeon_get_ib_value() gets shifted left. Avoid it by casting one of the operands to larger data type (u64). Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 1729dd33 ("drm/radeon/kms: r600 CS parser fixes") Signed-off-by:
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Yang Wang authored
enable MCA debug mode on APU device by default. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Likun Gao authored
For some SKU, rlc firmware should use different one compared with the normal rlc firmware. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Yang Wang authored
Use amdgpu_ip_version() helper function to check ip version. The ip version contains other information, use the helper function to avoid reading wrong value. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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ZhenGuo Yin authored
[Why] Golden registers are PF-only registers on gfx11. RLCG interface will return "out-of-range" under SRIOV VF. [How] Skip access gfx11 golden registers under SRIOV. Reviewed-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
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- 29 Nov, 2023 25 commits
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Lijo Lazar authored
The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by:
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Lijo Lazar authored
Add support to read state of XGMI links in aquavanjaram SOC. Signed-off-by:
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Lijo Lazar authored
Add support to read aqua vanjaram PCIE register state Signed-off-by:
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Lijo Lazar authored
Add reg_state attribute to fetch the register snapshot of different IPs like XGMI, WAFL,PCIE and USR. To get a snapshot for a particular IP 1) Open the sysfs file 2) Seek to the offset as defined in amdgpu_sysfs_reg_offset 3) Read Signed-off-by:
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Alex Deucher authored
This header defines the reg state structures exposed via sysfs for umr debugging. v2: add content type Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Add DSC granular throughput adjustment - Allow DTBCLK disable for DCN35 - Update Fixed VS/PE Retimer Sequence - Block dcn315 dynamic crb allocation when unintended - Update dcn315 lpddr pstate latency - Fix some HostVM parameters in DML Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Acked-by:
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Taimur Hassan authored
[Why] A number of DML parameters related to HostVM were either missing or being set incorrectly, which may cause inaccuracies in calculating margins and determining BW limitations. [How] Correct these values where needed and populate the missing values. Cc: stable@vger.kernel.org Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why/How] Update DSC DPCD parsing to take granular throughput adjustment into consideration. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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ZhenGuo Yin authored
[Why] Memory leaks of gang_ctx_bo and wptr_bo. [How] Free gang_ctx_bo and wptr_bo in pqm_uninit. v2: add a common function pqm_clean_queue_resource to free queue's resources. v3: reset pdd->pqd.num_gws when destorying GWS queue. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Candice Li authored
Check smu v13_0_0 SKU type to select EEPROM I2C address. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] DTBCLK is enabled on idle and it will burn power. [How] There's a few issues here: - Always enabling DTBCLK on clock manager init - Setting refclk when DTBCLK is supposed to be disabled - Not applying the correct calculated version refclk, but instead the base value which might be zero On dtbclk_en change we'll message PMFW to enable or disable the clock accordingly. The DTBDTO will be then based on refclk, but it will be set to the default fixed value if there was nothing calculated in DML despite the clock being considered enabled. Reviewed-by:
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Anthony Koo authored
- Add a new dmub command in enum dmub_cmd_cab_type Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Felix Kuehling authored
Make restore workers freezable so we don't have to explicitly flush them in suspend and GPU reset code paths, and we don't accidentally try to restore BOs while the GPU is suspended. Not having to flush restore_work also helps avoid lock/fence dependencies in the GPU reset case where we're not allowed to wait for fences. A side effect of this is, that we can now have multiple concurrent threads trying to signal the same eviction fence. Rework eviction fence signaling and replacement to account for that. The GPU reset path can no longer rely on restore_process_worker to resume queues because evict/restore workers can run independently of it. Instead call a new restore_process_helper directly. This is an RFC and request for testing. v2: - Reworked eviction fence signaling - Introduced restore_process_helper v3: - Handle unsignaled eviction fences in restore_process_bos Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
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Michael Strauss authored
[WHY/HOW] Add a new AUX sequence provided by vendor to improve interop with specific display configurations. Reviewed-by:
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Dmytro Laktyushkin authored
[WHY/HOW] Limit the dynamic crb to dual stream configs that include eDP Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Tested-by:
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Mario Limonciello authored
When dGPU is put into BOCO it may be in D3cold but still able send PME on display hotplug event. For this to work it must be enabled as wake source from D3. When runpm is enabled use pci_wake_from_d3() to mark wakeup as enabled by default. Cc: stable@vger.kernel.org # 6.1+ Signed-off-by:
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Lu Yao authored
For 'AMDGPU_FAMILY_SI' family cards, in 'si_common_early_init' func, init 'didt_rreg' and 'didt_wreg' to 'NULL'. But in func 'amdgpu_debugfs_regs_didt_read/write', using 'RREG32_DIDT' 'WREG32_DIDT' lacks of relevant judgment. And other 'amdgpu_ip_block_version' that use these two definitions won't be added for 'AMDGPU_FAMILY_SI'. So, add null pointer judgment before calling. Reviewed-by:
Lu Yao <yaolu@kylinos.cn> Signed-off-by:
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Dinghao Liu authored
When kzalloc() for smu_table->ecc_table fails, we should free the previously allocated resources to prevent memleak. Fixes: edd79420 ("drm/amd/pm: add message smu to get ecc_table v2") Signed-off-by:
Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by:
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Alex Deucher authored
This worked by luck if the GART aperture ended up at 0. When we ended up moving GART on some chips, the GART aperture ended up offsetting the AGP address since the resource->start is a GART offset, not an MC address. Fix this by moving the AGP address setup into amdgpu_bo_gpu_offset_no_check(). v2: check mem_type before checking agp v3: check if the ttm bo has a ttm_tt allocated yet Fixes: 67318cb8 ("drm/amdgpu/gmc11: set gart placement GC11") Tested-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reported-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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RutingZhang authored
checkpatch complains that: WARNING: braces {} are not necessary for single statement blocks + if (pool->base.irqs != NULL) { + dal_irq_service_destroy(&pool->base.irqs); + } Fixed it by removing unnecessary braces to fix the coding style issue. Signed-off-by:RutingZhang <u202112078@hust.edu.cn> Reviewed-by:
Dongliang Mu <dzm91@hust.edu.cn> Signed-off-by:
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Dmytro Laktyushkin authored
[WHY/HOW] Increase the pstate latency to improve ac/dc transition Reviewed-by:
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Hamza Mahfooz authored
On recent versions of DMUB firmware, if we want to completely disable ABM we have to pass ABM_LEVEL_IMMEDIATE_DISABLE as the requested ABM level to DMUB. Otherwise, LCD eDP displays are unable to reach their maximum brightness levels. So, to fix this whenever the user requests an ABM level of 0 pass ABM_LEVEL_IMMEDIATE_DISABLE to DMUB instead. Also, to keep the user's experience consistent map ABM_LEVEL_IMMEDIATE_DISABLE to 0 when a user tries to read the requested ABM level. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
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Lijo Lazar authored
Refactor code such that ras block decides the default mca debug mode, and not swsmu block. By default mca debug mode is set to false. v2: squash in uninitialized value fix (Alex) Signed-off-by:
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Aric Cyr authored
This version brings along the following: - DCN314 fixes - DCN32 fixes - DCN35 fixes - DML2 fixes - eDP fixes - HDR fixes - MST fixes - Replay fixes - SubVP support for more configs Acked-by:
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Anthony Koo authored
- Add a tracing framework, to measure duration, execution count and longest duration of main loop/vsync interrupt work GPINT command is used to start/stop the measurements. Acked-by:
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