- 10 Apr, 2015 3 commits
-
-
Jason Cooper authored
-
Jason Cooper authored
-
Jason Cooper authored
-
- 02 Apr, 2015 4 commits
-
-
Jason Cooper authored
-
Jason Cooper authored
-
Geert Uytterhoeven authored
The IRQC module clock is managed through Runtime PM and PM Domains. If wake-up is enabled, this clock must not be disabled during system suspend. Hence implement irq_chip.irq_set_wake(), which increments/decrements the clock's enable_count when needed. This fixes wake-up by gpio-keys on r8a73a4/ape6evm. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Link: https://lkml.kernel.org/r/1427889606-18671-1-git-send-email-geert+renesas@glider.beSigned-off-by:
Jason Cooper <jason@lakedaemon.net>
-
Gregory CLEMENT authored
On the Armada 370/XP SoCs, in standby mode the SoC stay powered and it is possible to wake-up from any interrupt sources. This patch adds flag to the MPIC irqchip driver to let linux know this. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1427724278-12379-5-git-send-email-gregory.clement@free-electrons.comSigned-off-by:
-
- 29 Mar, 2015 2 commits
-
-
Markos Chandras authored
We add new functions to start and stop the GIC counter since there are no guarantees the counter will be running after a CPU reset. The GIC counter is stopped by setting the 29th bit on the GIC Config register and it is started by clearing that bit. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: <linux-kernel@vger.kernel.org> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Link: https://lkml.kernel.org/r/1427113923-9840-2-git-send-email-markos.chandras@imgtec.comSigned-off-by:
-
Thierry Reding authored
Tegra210 uses the same legacy interrupt controller as older generations but it adds a sixth instance. Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://lkml.kernel.org/r/1427106379-14037-1-git-send-email-thierry.reding@gmail.comSigned-off-by:
-
- 23 Mar, 2015 4 commits
-
-
Baruch Siach authored
The digicolor_set_gc() routine is only called from __init annotated digicolor_of_init(). Annotate digicolor_set_gc() with __init as well to save a few bytes at run time. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Link: https://lkml.kernel.org/r/a3b57ecdbe0b07f55c20c07ff98f1f694275722d.1427009985.git.baruch@tkos.co.ilSigned-off-by:
-
Geert Uytterhoeven authored
The external IRQ controller has a functional clock, which is used for power management. Document it. Fix a typo in the r8a73a4 SoC name while we're at it. Signed-off-by:
-
Geert Uytterhoeven authored
This is just enough to let pm_clk_*() enable the functional clock, and manage it for suspend/resume, if present. Before, it was assumed enabled by the bootloader or reset state. Signed-off-by:
-
Geert Uytterhoeven authored
Signed-off-by:
-
- 18 Mar, 2015 2 commits
-
-
Marc Zyngier authored
Document the fact that some Exynos PMUs are capable of acting as an interrupt controller. Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088693-15724-3-git-send-email-marc.zyngier@arm.comSigned-off-by:
-
Marc Zyngier authored
Exynos has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the PMU block is actually the first interrupt controller in the chain for RTC, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs may not even boot. Also, I strongly suspect that there is more than two wake-up interrupts on these platforms, but I leave it to the maintainers to fix their mess. Signed-off-by:
-
- 15 Mar, 2015 16 commits
-
-
Jason Cooper authored
-
Jason Cooper authored
-
Stephen Boyd authored
In a uniprocessor implementation the interrupt processor targets registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately gic_get_cpumask() will print a critical message saying GIC CPU mask not found - kernel will fail to boot. if these registers all read as zero, but there won't actually be a problem on uniprocessor systems and the kernel will boot just fine. Skip this check if we're running a UP kernel or if we detect that the hardware only supports a single processor. Acked-by:
Nicolas Pitre <nico@linaro.org> Acked-by:
Felipe Balbi <balbi@ti.com> Acked-by:
Nishanth Menon <nm@ti.com> Acked-by:
Stefan Agner <stefan@agner.ch> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Link: https://lkml.kernel.org/r/1426141291-21641-1-git-send-email-sboyd@codeaurora.orgSigned-off-by:
-
Marc Zyngier authored
OMAP4/5 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the WUGEN HW block, kernels with this patch applied won't have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. On a platform with this patch applied, the system looks like this: root@bacon-fat:~# cat /proc/interrupts CPU0 CPU1 16: 0 0 WUGEN 37 gp_timer 19: 233799 155916 GIC 27 arch_timer 23: 0 0 WUGEN 9 l3-dbg-irq 24: 1 0 WUGEN 10 l3-app-irq 27: 282 0 WUGEN 13 omap-dma-engine 44: 0 0 4ae10000.gpio 13 DMA 294: 0 0 WUGEN 20 gpmc 297: 506 0 WUGEN 56 48070000.i2c 298: 0 0 WUGEN 57 48072000.i2c 299: 0 0 WUGEN 61 48060000.i2c 300: 0 0 WUGEN 62 4807a000.i2c 301: 8 0 WUGEN 60 4807c000.i2c 308: 2439 0 WUGEN 74 OMAP UART2 312: 362 0 WUGEN 83 mmc2 313: 502 0 WUGEN 86 mmc0 314: 13 0 WUGEN 94 mmc1 350: 0 0 PRCM pinctrl, pinctrl 406: 35155709 0 GIC 109 ehci_hcd:usb1 407: 0 0 WUGEN 7 palmas 409: 0 0 WUGEN 119 twl6040 410: 0 0 twl6040 5 twl6040_irq_ready 411: 0 0 twl6040 0 twl6040_irq_th IPI0: 0 1 CPU wakeup interrupts IPI1: 0 0 Timer broadcast interrupts IPI2: 95334 902334 Rescheduling interrupts IPI3: 0 0 Function call interrupts IPI4: 479 648 Single function call interrupts IPI5: 0 0 CPU stop interrupts IPI6: 0 0 IRQ work interrupts IPI7: 0 0 completion interrupts Err: 0 Acked-by:Tony Lindgren <tony@atomide.com> Signed-off-by:
-
Marc Zyngier authored
Add a binding for the OMAP4/5 wake-up generator, which acts as an interrupt controller feeding into the GIC. Acked-by:
-
Marc Zyngier authored
Nobody will regret it. Acked-by:
-
Marc Zyngier authored
The only user of the so called "routable domain" functionality now being fixed, let's clean up the GIC. Acked-by:
-
Marc Zyngier authored
Make it look like a real interrupt controller. Acked-by:
-
Marc Zyngier authored
Support for the TI crossbar used on the DRA7 family of chips is implemented as an ugly hack on the side of the GIC. Converting it to stacked domains makes it slightly more palatable, as it results in a cleanup. Unfortunately, as the DT bindings failed to acknowledge the fact that this is actually yet another interrupt controller (the third, actually), we have yet another breakage. Oh well. Acked-by:
-
Marc Zyngier authored
This proves to be useful with stacked domains, when the current domain doesn't implement wake-up, but expect the parent to do so. Acked-by:
-
Marc Zyngier authored
Now that all DTs have been updated, entierely drop support for the non-DT code. This is likely to break platforms that do not update their DT, so print a warning at boot time. Signed-off-by:
-
Marc Zyngier authored
Signed-off-by:
-
Marc Zyngier authored
Describe the legacy interrupt controller in every tegra DTSI files, and make it the parent of most interrupts. Signed-off-by:
-
Marc Zyngier authored
If we detect that our DT has a LIC node, don't setup gic_arch_extn, and skip tegra_legacy_irq_syscore_init as well. This is only a temporary measure until that code is removed for good. Acked-by:
-
Marc Zyngier authored
Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked IRQ domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by:
-
Marc Zyngier authored
The GIC is now always initialized from DT on tegra, and there is no point in keeping non-DT init code. Acked-by:
-
- 08 Mar, 2015 6 commits
-
-
Maxime Ripard authored
In order to let the Performance Monitoring Unit interrupts flowing in the MPIC, we need to unmask these interrupts in the Coherency Fabric Local Interrupt Mask Register. Since this register is a CPU-local register, unmasking this interrupt needs to be done on the boot CPU when the driver initializes, but also on the secondary CPU when they are brought up. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
-
Ezequiel Garcia authored
This commit introduces a helper function is_percpu_irq(), to be used when interrupts are mapped to decide which ones are set as per CPU. This change will allow to extend the list of per cpu interrupts in a less intrusive fashion; also, it makes the code slightly more readable by keeping a list of the per CPU interrupts. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by:
-
Ezequiel Garcia authored
The irqchip driver called armada_xp_mpic_smp_cpu_init() when CONFIG_SMP=Y to initialize some per cpu registers. The function is called on each CPU by calling it explicitly on the boot CPU and then using a CPU notifier for the non boot CPUs. This commit removes the CONFIG_SMP constrain, so the per cpu registers are also initialized when CONFIG_SMP=N, which is the right thing to do. Signed-off-by:
-
Stefan Agner authored
Add binding documentation for CPU configuration and interrupt router submodule of the Miscellaneous System Control Module. The MSCM is used in all variants of Freescale Vybrid SoC's. Acked-by:
-
Stefan Agner authored
This adds support for Vybrid's interrupt router. On VF6xx models, almost all peripherals can be used by either of the two CPU's, the Cortex-A5 or the Cortex-M4. The interrupt router routes the peripheral interrupts to the configured CPU. This IRQ chip driver configures the interrupt router to route the requested interrupt to the CPU the kernel is running on. The driver makes use of the irqdomain hierarchy support. The parent is given by the device tree. This should be one of the two possible parents either ARM GIC or the ARM NVIC interrupt controller. The latter is currently not yet supported. Note that there is no resource control mechnism implemented to avoid concurrent access of the same peripheral. The user needs to make sure to use device trees which assign the peripherals orthogonally. However, this driver warns the user in case the interrupt is already configured for the other CPU. This provides a poor man's resource controller. Acked-by:
-
Maxime Ripard authored
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt controller. Yet, it still has to handle some per-cpu interrupt. To do so, it is chained with the GIC using a per-cpu interrupt. However, the current code only call irq_set_chained_handler, which is called and enable that interrupt only on the boot CPU, which means that the parent per-CPU interrupt is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to actually work as expected. This was not seen until now since the only MPIC PPI users were the Marvell timers that were not working, but not used either since the system use the ARM TWD by default, and the ethernet controllers, that are faking there interrupts as SPI, and don't really expect to have interrupts on the secondary cores anyway. Add a CPU notifier that will enable the PPI on the secondary cores when they are brought up. Cc: <stable@vger.kernel.org> # 3.15+ Signed-off-by:
-
- 07 Mar, 2015 1 commit
-
-
Jason Cooper authored
-
- 03 Mar, 2015 2 commits
-
-
Geert Uytterhoeven authored
Signed-off-by:
-
Lee Jones authored
Signed-off-by:
Lee Jones <lee.jones@linaro.org> Link: https://lkml.kernel.org/r/1424272444-16230-4-git-send-email-lee.jones@linaro.orgSigned-off-by:
-
