1. 09 Feb, 2016 2 commits
  2. 04 Feb, 2016 2 commits
    • Jarkko Nikula's avatar
      spi: pxa2xx: Fix too early chipselect deassert · 7a8d44bc
      Jarkko Nikula authored
      There is a chance that chipselect is deasserted too early while the last
      clock cycle is still running. Protocol analyzers will see this as a failed
      last byte. This is more likely to occur with slow bitrates, for instance
      at 25 kbps.
      
      Reason for this is when using SPI mode 0 that both SPI host controller and
      SPI slave will drive the data lines at the falling edge of clock signal
      and sample at the rising edge. Receive FIFO gets the last bit now at the
      rising edge and code sees transfer to be finished either by the interrupt
      in PIO mode or by the DMA completion in DMA mode.
      
      The SSP Time Out register SSTO should take care of delaying the
      completion but it does not seems to have effect at least on Intel
      Skylake and Broxton even when using long enough values. Depending on
      timing code may get into point where chipselect is deasserted while the
      last clock cycle is still running at its second half cycle.
      
      Fix this by adding a wait loop in giveback() that waits until SSP becomes
      idle before deasserting the chipselect.
      Reported-by: default avatarWeifeng Voon <weifeng.voon@intel.com>
      Signed-off-by: default avatarJarkko Nikula <jarkko.nikula@linux.intel.com>
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      7a8d44bc
    • Jarkko Nikula's avatar
      spi: pxa2xx: Update comment in int_transfer_complete() · 07550df0
      Jarkko Nikula authored
      The register writes here actually don't stop the SSP but clean and
      disable interrupts and set the receive FIFO inactivity timeout to zero.
      Signed-off-by: default avatarJarkko Nikula <jarkko.nikula@linux.intel.com>
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      07550df0
  3. 27 Jan, 2016 1 commit
  4. 24 Jan, 2016 35 commits