- 26 Feb, 2015 1 commit
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Laurent Pinchart authored
Add DT nodes for the ADV7511 HDMI encoder and its HDMI output connector. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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- 25 Feb, 2015 6 commits
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Kazuya Mizuguchi authored
HSUSB uses hp_clk rather than mp_clk for H/W register access. Signed-off-by:
Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> [horms: updated changelog] Signed-off-by:
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Kazuya Mizuguchi authored
HSUSB uses hp_clk rather than mp_clk for H/W register access. Signed-off-by:
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Kuninori Morimoto authored
r8a7791 SDHI ch0/ch1 has SD_DMACR which is located in 0x324. This patch updates register size Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
r8a7790 SDHI ch0/ch1 has SD_DMACR which is located in 0x324. This patch updates register size Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
Add references to the transmit and receive DMA channels in the three SDHI nodes. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Laurent Pinchart authored
Add references to the transmit and receive DMA channels in the four SDHI nodes. Signed-off-by:
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- 23 Feb, 2015 33 commits
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Sergei Shtylyov authored
Define the generic R8A7794 parts of the SDHI[012] device nodes. Based on the orginal patch by Shinobu Uehara <shinobu.uehara.xc@renesas.com>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
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Sergei Shtylyov authored
Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7790 device tree. Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by:
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Sergei Shtylyov authored
Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7791 device tree. Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by:
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Sergei Shtylyov authored
Define the Henninger board dependent part of the CAN0 device node. Signed-off-by:
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Sergei Shtylyov authored
Define the generic R8A7791 parts of the CAN0/1 device nodes. Signed-off-by:
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Sergei Shtylyov authored
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by:
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Sergei Shtylyov authored
Define the generic R8A7790 parts of the CAN0/1 device nodes. Signed-off-by:
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Sergei Shtylyov authored
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by:
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Niklas Söderlund authored
Configure the pinmux on kzm9d to use the serial connector for uart1. Signed-off-by:
Niklas Söderlund <niso@kth.se> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
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Niklas Söderlund authored
With this information all GPIOs can make use of the PFC functionality. Signed-off-by:
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Wolfram Sang authored
Documentation says the last register is at 0x184 (CAxCPUCMCR), so use proper length. Current APMU code accesses CAxCPUnCR which is currently outside of the remapped area. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Wolfram Sang authored
Documentation says the last register is at 0x184 (CAxCPUCMCR), so use proper length. Current APMU code accesses CAxCPUnCR which is currently outside of the remapped area. Signed-off-by:
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Laurent Pinchart authored
Add DT nodes for the ADV7511 HDMI encoder and its HDMI output connector and configure the DISP pin group that drives the HDMI transmitter DE pin. Signed-off-by:
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Simon Horman authored
There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. Fixes: 59e79895 ("ARM: shmobile: r8a7791: Add clocks") Reported-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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Simon Horman authored
* Correct base address of SD3 div6 clk. * Update div6 clock node labels There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. This has no run-time affect as the clock nodes are not currently used. Fixes: 8e181633 ("ARM: shmobile: r8a7794: Add SDHI clocks to device tree") Reported-by:
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Laurent Pinchart authored
Enable the ethernet controller for the Alt board. Pin muxing entries are currently left out as r8a7794 pin control support isn't available yet. We thus rely on the boot loader to configure ethernet pins for now. Signed-off-by:
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Laurent Pinchart authored
Add a DT node for the on-SoC ethernet controller device. Signed-off-by:
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Laurent Pinchart authored
Add the six IPMMU instances found in the r8a7794 to DT with a disabled status. Signed-off-by:
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Laurent Pinchart authored
Add the seven IPMMU instances found in the r8a7791 to DT with a disabled status. Signed-off-by:
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Laurent Pinchart authored
Add the six IPMMU instances found in the r8a7790 to DT with a disabled status. Signed-off-by:
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Laurent Pinchart authored
Instantiate the two system DMA controllers in the r8a7794 device tree. Signed-off-by:
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Geert Uytterhoeven authored
Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by:
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Geert Uytterhoeven authored
Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by:
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Ulrich Hecht authored
Specifies clock sources and register bits. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> [geert: Drop renesas,src-shift/renesas,src-width, pad to 4 or 8 parents] Signed-off-by:
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Geert Uytterhoeven authored
This clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM. Signed-off-by:
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Laurent Pinchart authored
Enable the kzm9g touchscreen controller in the board's DT file. Signed-off-by:
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Geert Uytterhoeven authored
Add a DT node for the R2025D real-time clock, which is connected to i2c0. Signed-off-by:
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Geert Uytterhoeven authored
Add a DT node for the ADXL345 three-axis digital accelerometer sensor, which is connected to i2c0. As trivial i2c devices are matched against the first compatible entry only, compatibility is declared with "adi,adxl34x" only for now. Signed-off-by:
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Geert Uytterhoeven authored
Add a DT node for the AK8975 magnetometer sensor, which is connected to i2c0. Signed-off-by:
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Geert Uytterhoeven authored
While at it rename the ak4648 node to "codec" to describe the device's function instead of its model, and move its device-specific property after its generic properties. Signed-off-by:
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Laurent Pinchart authored
The sh73a0 INTC can't mask interrupts properly most likely due to a hardware bug. Set the control-parent property to delegate masking to the parent interrupt controller. Signed-off-by:
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Ulrich Hecht authored
This adds the remaining DIV6 clocks and all possible parents for the SUB clock. Signed-off-by:
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Linus Torvalds authored
.. after extensive statistical analysis of my G+ polling, I've come to the inescapable conclusion that internet polls are bad. Big surprise. But "Hurr durr I'ma sheep" trounced "I like online polls" by a 62-to-38% margin, in a poll that people weren't even supposed to participate in. Who can argue with solid numbers like that? 5,796 votes from people who can't even follow the most basic directions? In contrast, "v4.0" beat out "v3.20" by a slimmer margin of 56-to-44%, but with a total of 29,110 votes right now. Now, arguably, that vote spread is only about 3,200 votes, which is less than the almost six thousand votes that the "please ignore" poll got, so it could be considered noise. But hey, I asked, so I'll honor the votes.
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