- 15 Dec, 2020 23 commits
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Alex Deucher authored
In preparation for systems that support d3cold on dGPUs independent of PX/HG. No functional change intended. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Souptick Joarder authored
Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5: warning: no previous prototype for 'amdgpu_dm_crtc_atomic_set_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5: warning: no previous prototype for function 'amdgpu_dm_crtc_atomic_set_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5: warning: no previous prototype for 'amdgpu_dm_crtc_atomic_get_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5: warning: no previous prototype for function 'amdgpu_dm_crtc_atomic_get_property' [-Wmissing-prototypes] As these functions are only used inside amdgpu_dm.c, these can be made static. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Anthony Koo authored
- Add new aux_channel_type - Changed port_index to instance in dmub_cmd_dp_aux_control_data - Change aux_return_code_type to sync up with driver - param for ramping abm based on backlight level Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
[Why] Typo in MPCC visual confirmation. [How] Fix to correct values. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Felipe authored
[Why] The OGAM LUT precision was accumulating too much error in the higher end. [How] Instead of calculating all points of the LUT in relation to the previous ones, perform a full calculation in one of the intermediate segments to stop error propagation. Signed-off-by:
Felipe Clark <Felipe.Clark@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Aric Cyr authored
[Why] FP2 is not double buffered and must wait for VACTIVE before programming. [How] Only update when there is a full update we should change FP2 to avoid delay every flip. Signed-off-by:
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Jake Wang authored
[Why] For certain timings, Renoir may underflow due to sr exit latency being too slow. [How] Updated wm table for renoir. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Martin Leung authored
[Why] race condition of programming FP2 wrt pipe locking and vactive state can cause underflow/black screen [How] Enforce the FP2 is only programmed during vactive, and unlock pipe soon afterwards. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Leo (Hanghong) Ma authored
[Why] We are missing the DP info frame update on dcn30, and this will lead to DP SDPs not being sent; [How] Add the DP info frame update for dcn30; Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Eric Bernstein authored
[Why] dcn30_link_encoder_validate_output_with_stream was a static function. [How] remove the static define and include it in the header. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Wayne Lin authored
[Why] Find out when we try to disable CRC calculation, crc generation is still enabled. Main reason is that dc_stream_configure_crc() will never get called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE. [How] Add checking condition that when source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE, we should also call dc_stream_configure_crc() to disable crc calculation. Also, clean up crc window when disable crc calculation. Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aric Cyr authored
[Why] Many VR headsets require a HSYNC width of 4, but DCN has default minimum of 8. [How] Change the arbitrary minimum HSYNC width to 4 to match DCN20. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Max Tseng authored
[Why] some DP_SEC register defs and masks are missing. [How] add the missing defs and masks. Signed-off-by:
Max Tseng <chuan-yu.tseng@amd.com> Reviewed-by:
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Victor Lu authored
[Why] There is a warning that triggers when pstate takes too long. Pstate can take up to ~200us on Linux without hanging but it is currently set to 40us. [How] Change the timeout for the warning to be 180us on Linux. Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
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Stanley.Yang authored
skip load smu and sdma fw on sriov due to sos, ta and asd fw have been skipped for SIENNA_CICHLID. V2: move asic check into smu11 Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Flora Cui authored
CONFIG_DRM_AMD_DC_DCN3_0 is retired. drop it Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Likun Gao authored
S0ix only makes sense on APUs since they are part of the platform, so only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag to deal with the related situation. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Xiaomeng Hou authored
Without doing the soft reset, register mmSDMA0_GFX_RB_WPTR's value could not be reset to 0 when sdma block resumes. That would cause the ring buffer's read and write pointers not equal and ring test fail. So add the soft reset step. Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Evan Quan authored
These are supported by Sienna Cichlid and should be taken into consideration during DS control. Signed-off-by:
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Evan Quan authored
This is needed for Sienna Cichlid. Signed-off-by:
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Evan Quan authored
This is needed for Sienna Cichlid. Signed-off-by:
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Evan Quan authored
Fulfill the UMD PSTATE profiling clocks of sienna cichlid. Signed-off-by:
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- 10 Dec, 2020 16 commits
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Xiaomeng Hou authored
RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW is unaware of RLC being halted and will continue sending messages, which would eventually cause an ACPI hang. Use the system_feature_control interface to notify SMU the status of RLC (Normal/OFF) thus enable/disable DPM feature. Signed-off-by:
Lazar Lijo <Lijo.Lazar@amd.com> Signed-off-by:
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Xiaomeng Hou authored
Add new PMFW message to notify RLC engine status. Signed-off-by:
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Alex Deucher authored
It's only used when CONFIG_DRM_AMD_DC_DCN is set. Fixes and set but not used warning. Acked-by:
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Evan Quan authored
The "COMPUTE" was wrongly spelled as "CUSTOM". Signed-off-by:
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Evan Quan authored
Fulfill the 2nd usb2.0 port workaround for sienna cichlid. Signed-off-by:
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Evan Quan authored
The workaround is needed by sienna cichlid. Signed-off-by:
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Evan Quan authored
Used for determining 2ND_USB20PORT support from firmware_capability. Signed-off-by:
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Evan Quan authored
That will help to determine whether 2ND_USB20_PORT workaround is needed for Sienna Cichlid. Signed-off-by:
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Evan Quan authored
New SMC message was introduced for gpo control on sienna cichlid. Signed-off-by:
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Evan Quan authored
Correct the power limit setting for SMU V11 asics. Signed-off-by:
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Evan Quan authored
Enable power source switch on Sienna Cichlid. Signed-off-by:
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Jiansong Chen authored
Correct pipe offset calculation in is_pipe_enabled function, it should be done in queues. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
After refactor our amdgpu_dm_atomic_commit, this function only invoke drm_atomic_helper_commit. For this reason, this commit drops amdgpu_dm_atomic_commit and add drm_atomic_helper_commit directly in the atomic_commit hook. v2: squash in warning fix (Alex) Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Christian König authored
The text output should not be more than a page, so only print the first 32 page table entries. If we need all of them we can still look into the binary trace. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
amd-drm-next-5.11-2020-12-09: amdgpu: - SR-IOV fixes - Navy Flounder updates - Sienna Cichlid updates - Dimgrey Cavefish updates - Vangogh updates - Misc SMU fixes - Misc display fixes - Last big hunk of W=1 warning fixes - Cursor validation fixes - CI BACO updates From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201210045344.21566-1-alexander.deucher@amd.comSigned-off-by:
Dave Airlie <airlied@redhat.com>
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Andrey Grodzovsky authored
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation and amdgpu_gem_object_funcs setting into single function called from both code paths. Fixes: d693def4 ("drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver") v2: Use use amdgpu_gem_object_create() directly v3: fix warning Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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- 09 Dec, 2020 1 commit
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
* Shutdown hook for GPU (to ensure GPU is idle before iommu goes away) * GPU cooling device support * DSI 7nm and 10nm phy/pll updates * Additional sm8150/sm8250 DPU support (merge_3d and DSPP color processing) * Various DP fixes * A whole bunch of W=1 fixes from Lee Jones * GEM locking re-work (no more trylock_recursive in shrinker!) * LLCC (system cache) support * Various other fixes/cleanups Signed-off-by:
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