- 08 Sep, 2021 3 commits
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Lee Shawn C authored
VDSC engine can process only 1 pixel per Cd clock. In case VDSC is used and max slice count == 1, max supported pixel clock should be 100% of CD clock. Then do min_cdclk and pixel clock comparison to get proper min cdclk. v2: - Check for dsc enable and slice count ==1 then allow to double confirm min cdclk value. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: William Tseng <william.tseng@intel.com> Signed-off-by:
Lee Shawn C <shawn.c.lee@intel.com> Reviewed-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Acked-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Lee Shawn C authored
According to chapter "Sending Commands to the Panel" in bspec #29738 and #49188. If driver try to send DCS long pakcet, we have to program TX payload register at first. And configure TX header HW register later. DSC long packet would not be sent properly if we don't follow this sequence. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: William Tseng <william.tseng@intel.com> Signed-off-by:
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Lee Shawn C authored
Driver should wait for free header or payload buffer in FIFO. It would be good to wait a while for HW to release credit before give it up to write to HW. Without sending initailize command sets completely. It would caused MIPI display can't light up properly. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: William Tseng <william.tseng@intel.com> Signed-off-by:
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- 07 Sep, 2021 10 commits
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José Roberto de Souza authored
Frontbuffer rendering will be dropped for modern platforms but before that we to prepare DRRS for it. intel_drrs_flush and intel_drrs_invalidate will not be called for platforms that will not support frontbuffer rendering so DRRS needs another way to be notified about to page flips so it can change between high and low refresh rates as needed. Reviewed-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210903221036.34770-3-jose.souza@intel.com
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José Roberto de Souza authored
Both functions are pretty much equal, with minor changes that can be handled by a single parameter. v3: - not scheduling work from invalidate operations Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
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José Roberto de Souza authored
It started as a code style fix for the lines above 100 col but it turned out to simplifications to intel_drrs_set_state(). Now it receives the desired refresh rate type, high or low. v3: - Fixed the mode refesh rate debug message Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
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Jani Nikula authored
We can finally remove the extra caching in ddi_port_info. Good riddance. v2: Rebased Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Jani Nikula authored
Avoid extra caching of the data. This is slightly more subtle than one would think. For one thing, we explicitly ignore 0 value in child device ddc pin; this is specified as N/A and does not warrant a warning. For another, we start looking for ddc pin collisions in sanitize using unmapped pin numbering. v2: Check !devdata in intel_bios_alternate_ddc_pin() Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Jani Nikula authored
Move code around to avoid a forward declaration in the future. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid extra caching of the data. v2: Check for !info->devdata in intel_bios_port_aux_ch() (Ankit) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid extra caching of the data. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid extra caching of the data. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid extra caching of the data. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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- 02 Sep, 2021 8 commits
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Animesh Manna authored
Added HBR3 support for ADL_P and ADL_S platform. Bspec: 53597, 53720, 49185, 55409 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Jani Nikula authored
Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP can do 8.1 GHz on combo phy. Bspec: 49182, 49205, 49202 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Animesh Manna authored
Only higher voltage sku can support HBR3 so a condition check added in max source rate calculation for ehl/jsl. Bspec: 32247, 20598 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Jani Nikula authored
Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz. Bspec: 20584, 20598, 49180, 49201 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Matt Atwood authored
intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to use before intel_encoder->type is set. This causes incorrect max source rate to be used for display 11+. On EHL and JSL, HBR3 is used instead of HBR2, and on the other affected platforms, HBR2 is used instead of HBR3. Move intel_dp_set_source_rates() to after intel_encoder->type is set. Add comment to intel_dp_is_edp() describing unsafe usages. Cleanup intel_dp_init_connector() while at it. Note: The same change was originally added as commit 680c45c7 ("drm/i915/dp: Correctly advertise HBR3 for GEN11+"), but later reverted due to issues in CI in commit d3913019 ("Revert "drm/i915/dp: Correctly advertise HBR3 for GEN11+""). Cc: Uma Shankar <uma.shankar@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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Jani Nikula authored
Clean up the LPSP capability printout. No functional changes. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Jani Nikula authored
Clean up the LPSP status printout. No functional changes. Reviewed-by:
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Jani Nikula authored
Accidentally dropped the else in a rebase fail, causing the DG2 max rate to be overwritten later in the if ladder. Fixes: e752d1f9 ("drm/i915/dg2: add DG2 UHBR source rates") Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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- 01 Sep, 2021 3 commits
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Vandita Kulkarni authored
Enable MIPI DSI support on ADL-P platform. The esc clock changes, WA changes are taken care in the previous patches. As per the Bspec the seq remains to be same as TGL. Signed-off-by:
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Vandita Kulkarni authored
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband" field to account for the repeaters on the HS Request/Ready PPI signaling between the Display engine and the DPHY. v2: Fix build issue. v3: Align to new naming (Jani) Signed-off-by:
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Vandita Kulkarni authored
Xelpd supports larger small joiner ram. Signed-off-by:
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- 30 Aug, 2021 5 commits
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José Roberto de Souza authored
We had a mix of intel_edp_drrs_*(), intel_dp_drrs_*() and intel_dp_set_drrs_state(), so properly renaming all functions to keep the same pattern. While at it, also dropping intel_dp_set_drrs_state from the documentation as it is a static function. v3: - dropping documentation style comment in static function (intel_drrs_set_state) Reviewed-by:
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José Roberto de Souza authored
intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce some lines from it. Reviewed-by:
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José Roberto de Souza authored
At this point is sure that HSW and BDW will never have PSR enabled by default, so here dropping it from device info and cleaning up code. v2: - enable psr support for display 9 Reviewed-by:
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Animesh Manna authored
UHBR modes has higher link rate and added new values for programming mpll of SNPS phy. No change in sequence, only the pll parameters are different for UHBR modes. Reviewed-by:
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Jani Nikula authored
Apparently the last reader of i915->active_pipes was removed with commit ef79d62b ("drm/i915: Encapsulate dbuf state handling harder"), and now it's only ever written to. Remove it completely. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 27 Aug, 2021 5 commits
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Jani Nikula authored
These shouldn't happen, but in the off chance they do, we'll want a warning rather than panic. Reviewed-by:
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Jani Nikula authored
This fairly detailed stuff that really has no place in intel_display.c. Combine the calls into one to avoid exposing both. Reviewed-by:
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Jani Nikula authored
Accept slight duplication in the fdi link train hooks in exchange for simplification in ilk_pch_enable(). This lets us make ivb_update_fdi_bc_bifurcation() static again, now in intel_fdi.c. Reviewed-by:
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Jani Nikula authored
Move FDI related functions to intel_fdi.c. Don't bother with renaming as we'll make the functions static shortly. Reviewed-by:
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Jani Nikula authored
Move FDI related functions to intel_fdi.c. Rename to have intel_fdi prefix while at it. Reviewed-by:
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- 26 Aug, 2021 5 commits
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Rodrigo Vivi authored
Merge tag 'drm-misc-intel-oob-hotplug-v1' of git://git.kernel.org/pub/scm/linux/kernel/git/hansg/linux into drm-intel-next Topic branch for drm-misc / drm-intel for OOB hotplug support for Type-C connectors Signed-off-by:
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Jani Nikula authored
The tables should be const arrays of const pointers, not just arrays of const pointers. Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Jani Nikula authored
Follow the usual naming conventions. Also pull HAS_GMCH() check to intel_panel_fitting(). No functional changes. Cc: Lyude Paul <lyude@redhat.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Jani Nikula authored
Follow the usual naming conventions. As a drive-by cleanup, also pass intel_connector instead of drm_connector to intel_backlight_setup(). No functional changes. Cc: Lyude Paul <lyude@redhat.com> Reviewed-by:
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Jani Nikula authored
In a long overdue refactoring, split out backlight code to new intel_backlight.[ch]. Simple code movement, leave renames for follow-up work. No functional changes. Cc: Lyude Paul <lyude@redhat.com> Reviewed-by:
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- 25 Aug, 2021 1 commit
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Matt Roper authored
The memory latency values returned by pcode on DG2 are in units of "2 usec" rather than 1 usec on all other platforms. I.e., we need to double the value returned by pcode to obtain the true latency value. The bspec wording here was a bit ambiguous as to whether it wanted us to multiply or divide the pcode value by two, but we confirmed offline with the hardware team that we need to double the value the pcode gives us; this change is intended to support a larger range of potential latency values. Bspec: 49326 Signed-off-by:
Harish Chegondi <harish.chegondi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210820225710.401136-1-matthew.d.roper@intel.com
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