- 03 Jul, 2024 1 commit
-
-
Danila Tikhonov authored
Add the DSI host found on SM7150. Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601231/Signed-off-by:
Rob Clark <robdclark@chromium.org>
-
- 02 Jul, 2024 2 commits
-
-
Rob Clark authored
Fixes a sparse "different address spaces" error. Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406280050.syeEwLTE-lkp@intel.com/Signed-off-by:
-
Rob Clark authored
The __build_asserts() function only exists to have a place to put build-time asserts. Reported-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601606/
-
- 01 Jul, 2024 2 commits
-
-
Daniil Titov authored
This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), SDM439 (650 MHz). Signed-off-by:
Daniil Titov <daniilt971@gmail.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Barnabás Czémán <trabarni@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/601411/Signed-off-by:
-
Abhinav Kumar authored
On QCM2290 chipset DPU does not support UBWC. Add a dpu cap to indicate this and do not expose compressed formats in this case. changes since RFC: - use ubwc enc and dec version of mdss_data instead of catalog to decide if ubwc is supported Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by:
-
- 29 Jun, 2024 7 commits
-
-
Akhil P Oommen authored
To simplify, introduce the new gmu_chipid for a740 & a750 GPUs. Signed-off-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by:
-
Akhil P Oommen authored
Add support in drm/msm driver for the Adreno X185 gpu found in Snapdragon X1 Elite chipset. Signed-off-by:
-
Akhil P Oommen authored
Document Adreno X185 GMU in the dt-binding specification. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/601395/Signed-off-by:
-
Neil Armstrong authored
Disable the call to qcom_scm_gpu_init_regs() for a730 and a740 after init failures on the HDK8550 and HDK8450 platforms: msm_dpu ae01000.display-controller: failed to load adreno gpu msm_dpu ae01000.display-controller: failed to bind 3d00000.gpu (ops a3xx_ops [msm]): -5 msm_dpu ae01000.display-controller: adev bind failed: -5 While debugging, it happens the call to: qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ) returns -5 and makes the gpu fail to initialize. Remove the scm call since it's not done downstream either and works fine without. Fixes: 14b27d5d ("drm/msm/a7xx: Initialize a750 "software fuse"") Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/600972/Signed-off-by:
-
Neil Armstrong authored
The gpulist has twice the a6xx gpulist, replace the second one with the a7xx gpulist. Solves: msm_dpu ae01000.display-controller: Unknown GPU revision: 7.3.0.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.10.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.20.1 on SM8450, SM8550 & SM8560. Fixes: 8ed322f6 ("drm/msm/adreno: Split up giant device table") Signed-off-by:
-
Konrad Dybcio authored
Commit f6ebff4fe810 ("drm/msm/adreno: De-spaghettify the use of memory barriers") made some fixups relating to write arrival, ensuring that the GPU's memory interface has *really really really* been told to come out of reset. That in turn rendered the hacky commit being reverted no longer necessary. Get rid of it. This reverts commit b7753280 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init") Signed-off-by: -
Konrad Dybcio authored
Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the latter can be a giant pain point, and it has been as part of this driver. Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of readl/writel, which include r/w (respectively) barriers. Replace the barriers with a readback (or drop altogether where possible) that ensures the previous writes have exited the write buffer (as the CPU must flush the write to the register it's trying to read back). Signed-off-by:
-
- 25 Jun, 2024 6 commits
-
-
Rob Clark authored
Merge remote-tracking branch 'qcom/20240430-a750-raytracing-v3-2-7f57c5ac082d@gmail.com' into msm-next-robclark Merge qcom drivers to pick up dependency for SMEM based speedbin. Signed-off-by: -
Krzysztof Kozlowski authored
dtschema v2024.4, v2024.5 and maybe earlier do not select device nodes for given binding validation if the schema contains compatible list with pattern and a const fallback. This leads to binding being a no-op - not being applied at all. Issue should be fixed in the dtschema but for now add a work-around do the binding can be used against DTS validation. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240623-qcom-adreno-dts-bindings-driver-v2-4-9496410de992@linaro.orgSigned-off-by:
-
Krzysztof Kozlowski authored
Regex for newer Adreno compatibles can be simpler. Suggested-by:
Conor Dooley <conor@kernel.org> Signed-off-by:
-
Krzysztof Kozlowski authored
All devices should (and actually do) have same order of entries, if possible. That's the case for reg/reg-names, so define the reg-names in top-level to enforce that. Acked-by:
-
Krzysztof Kozlowski authored
We expect each schema with variable number of clocks, to have the widest constrains in top-level "properties:". This is more readable and also makes binding stricter, if there is no "if:then:" block for given variant. Acked-by:
-
Dmitry Baryshkov authored
The frame event callback is always set to dpu_crtc_frame_event_cb() (or to NULL) and the data is always either the CRTC itself or NULL (correpondingly). Thus drop the event callback registration, call the dpu_crtc_frame_event_cb() directly and gate on the dpu_enc->crtc assigned using dpu_encoder_assign_crtc(). Signed-off-by:
-
- 24 Jun, 2024 15 commits
-
-
Daniil Titov authored
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only difference from existing msm8916 configuration is number of phy and io_start addresses. Signed-off-by:
-
Barnabás Czémán authored
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. Reviewed-by:
-
Daniil Titov authored
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937. Signed-off-by:
-
Barnabás Czémán authored
Add the compatible for the MDP5 found on MSM8937. Reviewed-by:
-
Barnabás Czémán authored
Remove MDP_CAP_SRC_SPLIT from msm8x53_config because it is not referenced in downstream. Fixes: fb25d447 ("drm/msm/mdp5: Add configuration for MDP v1.16") Signed-off-by:
-
Jani Nikula authored
Prefer the struct drm_edid based functions for reading the EDID and updating the connector. Simplify the flow by updating the EDID property when the EDID is read instead of at .get_modes. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/593976/ Link: https://lore.kernel.org/r/93d6c446ed4831dadfb4a77635a67cf5f27e19ff.1715691257.git.jani.nikula@intel.comSigned-off-by:
-
Barnabás Czémán authored
CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts, so better to skip CTL irq callback register/unregister make dpu_ctl_cfg be able to define without intr_start. Signed-off-by:
-
Dmitry Baryshkov authored
Rename dpu_hw_setup_vsync_source functions to make the names match the implementation: on DPU 5.x the TOP only contains timer setup, while 3.x and 4.x used MDP_VSYNC_SEL register to select TE source. Signed-off-by:
-
Dmitry Baryshkov authored
Make the DPU driver use the TE source specified in the DT. If none is specified, the driver defaults to the first GPIO (mdp_vsync_p). Signed-off-by:
-
Dmitry Baryshkov authored
Allow board's device tree to specify the vsync source (aka TE source). If the property is omitted, the display controller driver will use the default setting. Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/598740/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-6-67a0116b5366@linaro.org
-
Dmitry Baryshkov authored
The struct msm_display_info has is_te_using_watchdog_timer field which is neither set anywhere nor is flexible enough to specify different sources. Replace it with the field specifying the vsync source using enum dpu_vsync_source. Reviewed-by:
-
Dmitry Baryshkov authored
Setting vsync source makes sense only for DSI CMD panels. Pull the is_cmd_mode condition out of the function into the calling code, so that it becomes more explicit. Reviewed-by:
-
Dmitry Baryshkov authored
Neither disp-enable-gpios nor disp-te-gpios are defined in the schema. None of the board DT files use those GPIO pins. Drop them from the driver. Reviewed-by:
-
Dmitry Baryshkov authored
Add enum dpu_vsync_source instead of a series of defines. Use this enum to pass vsync information. Reviewed-by:
-
Dmitry Baryshkov authored
Command mode panels provide TE signal back to the DSI host to signal that the frame display has completed and update of the image will not cause tearing. Usually it is connected to the first GPIO with the mdp_vsync function, which is the default. In such case the property can be skipped. Acked-by:
Rob Herring (Arm) <robh@kernel.org> Signed-off-by:
-
- 23 Jun, 2024 5 commits
-
-
Abhinav Kumar authored
clear_pending_flush() ctl op is always assigned irrespective of the DPU hardware revision. Hence there is no needed to check whether the op has been assigned before calling it. Drop the checks across the driver for clear_pending_flush() and also update its documentation that it is always expected to be assigned. changes in v2: - instead of adding more validity checks just drop the one for clear_pending_flush - update the documentation for clear_pending_flush() ctl op - update the commit text reflecting these changes changes in v3: - simplify the documentation of clear_pending_flush Fixes: d7d0e73f ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Reported-by:
Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/464fbd84-0d1c-43c3-a40b-31656ac06456@moroto.mountain/T/Signed-off-by:
-
Danila Tikhonov authored
Add support for MDSS on SM7150. Signed-off-by:
-
Danila Tikhonov authored
Document the MDSS hardware found on the Qualcomm SM7150 platform. Signed-off-by:
-
Danila Tikhonov authored
Add definitions for the display hardware used on the Qualcomm SM7150 platform. Signed-off-by:
-
Danila Tikhonov authored
Document the DPU hardware found on the Qualcomm SM7150 platform. Signed-off-by:
-
- 22 Jun, 2024 2 commits
-
-
Jonathan Marek authored
Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Reviewed-by:
Jun Nie <jun.nie@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/596236/ Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-6-2ab1d334c657@linaro.orgSigned-off-by:
-
Jonathan Marek authored
Video mode DSC won't work if this field is not set correctly. Set it to fix video mode DSC (for slice_per_pkt==1 cases at least). Fixes: 08802f51 ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by:
-
