- 13 Sep, 2022 38 commits
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Alvin Lee authored
[Description] Leverage SW cursor fall back for SubVP when the cursor is too big. We want to take advantage of being able to fallback to SW cursor when possible because it's not worth it to disable MCLK switching because the cursor is slightly too big. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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JinZe.Xu authored
[Why] link type is not assigned before check dpia_mst_dsc_always_on conditions. Tested-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by:
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Nagulendran, Iswara authored
[HOW&WHY] Revert a previous commit by moving DSC programming back to before link enablement. Tested-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Acked-by:
Nagulendran, Iswara <Iswara.Nagulendran@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] Update MBLK calculation according to hardware doc. For DCC case we were not allocation enough MALL due to an inaccurate MBLK calculation. Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Aurabindo Pillai authored
This reverts commit a4f1b042 since returning false in case of SubVP results in no cursor being visible on desktop as there is no sw cursor fallback path on all platforms. Tested-by:
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Chris Park authored
[Why] I2C register name starts with 1, unlike other registers that start with 0. This creates a problem with the new register macro refactoring when I2C HW objects are created in an array. [How] Correct I2C register offset by making a new macro to account for array offset. Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Signed-off-by:
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Aric Cyr authored
[why] Conditionals in the DML basic math functions significantly impact mode enumeration. [how] Remove conditionals for floor/ceil operations which are used frequently in DML and add an assertion for invalid callers using zero granuality. Fix existing callers that rely on 0 granularity. Tested-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Candice Li authored
No need to reset error status since only umc ras supported on psp v13_0_0. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Candice Li authored
Set correct EEPROM I2C address for smu v13_0_0. Signed-off-by:
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John Clements authored
copy ras driver to psp if present Signed-off-by:
John Clements <john.clements@amd.com> Reviewed-by:
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Alex Deucher authored
Was missing before and would have resulted in a write to a non-existant register. Normally APUs don't use HDP, but other asics could use this code and APUs do use the HDP when used in passthrough. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Jingyu Wang authored
Remove "default n" options. If the "default" line is removed, it defaults to 'n'. Signed-off-by:
Jingyu Wang <jingyuwang_vip@163.com> Signed-off-by:
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Jilin Yuan authored
Delete the redundant word 'in'. Signed-off-by:
Jilin Yuan <yuanjilin@cdjrlc.com> Signed-off-by:
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Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_amdkfd_gpuvm.c Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_amdkfd.c Signed-off-by:
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Jingyu Wang authored
This is a patch to the amdgpu_sync.c file that fixes some warnings found by the checkpatch.pl tool Signed-off-by:
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Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_acpi.c Signed-off-by:
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zhang songyi authored
Return the sdma_v6_0_start() directly instead of storing it in another redundant variable. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
zhang songyi <zhang.songyi@zte.com.cn> Signed-off-by:
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ye xingchen authored
Return the value radeon_drm_ioctl() directly instead of storing it in another redundant variable. Reported-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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ye xingchen authored
Return the value ci_load_smc_ucode() directly instead of storing it in another redundant variable. Reported-by:
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Yang Li authored
Conditional statements have no effect to next process.So remove it. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2028Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yang Li authored
The result of relational operation is Boolean, and the question mark expression is redundant. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2027Reported-by:
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Yang Li authored
This if statement is the content of the for statement above it. It should be indented. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2026Reported-by:
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Vignesh Chander authored
both get_xgmi_hive and put_xgmi_hive can be skipped since the reset domain is not necessary for VF Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Reviewed-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by:
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Philip Yang authored
migrate_vma_setup shows below warning because we don't hold another process mm mmap_lock. We should use current vmf->vma->vm_mm instead, the caller already hold current mmap lock inside CPU page fault handler. WARNING: CPU: 10 PID: 3054 at include/linux/mmap_lock.h:155 find_vma Call Trace: walk_page_range+0x76/0x150 migrate_vma_setup+0x18a/0x640 svm_migrate_vram_to_ram+0x245/0xa10 [amdgpu] svm_migrate_to_ram+0x36f/0x470 [amdgpu] do_swap_page+0xcfe/0xec0 __handle_mm_fault+0x96b/0x15e0 handle_mm_fault+0x13f/0x3e0 do_user_addr_fault+0x1e7/0x690 Fixes: e1f84eef ("drm/amdkfd: handle CPU fault on COW mapping") Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Yang Wang authored
align TMR BO size TO tmr size is not necessary, modify the size to 1M to avoid re-create BO fail when serious VRAM fragmentation. v2: add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
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Candice Li authored
Enable full reset for RAS supported configuration on gc v11_0_0. v2: simplify the code. Signed-off-by:
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Candice Li authored
Only check MCUMC_STATUS for CE counter for umc v8_10. Signed-off-by:
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Charlene Liu authored
[why] update header files, and remove not used register access marco Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
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Philip Yang authored
Prefaulting potentially allocates system memory pages before a migration. This adds unnecessary overhead. Instead we can skip unallocated pages in the migration and just point migrate->dst to a 0-initialized VRAM page directly. Then the VRAM page will be inserted to the PTE. A subsequent CPU page fault will migrate the page back to system memory. Signed-off-by:
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Philip Yang authored
If CPU page fault in a page with zone_device_data svm_bo from another process, that means it is COW mapping in the child process and the range is migrated to VRAM by parent process. Migrate the parent process range back to system memory to recover the CPU page fault. Signed-off-by:
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wangjianli authored
Delete the redundant word 'to'. Signed-off-by:
wangjianli <wangjianli@cdjrlc.com> Signed-off-by:
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shaoyunl authored
For SRIOV configuration, host driver control the reset method(either FLR or heavier chain reset). The host will notify the guest individually with FLR message if individual GPU within the hive need to be reset. So for guest side, no need to use hive->reset_domain to replace the original per device reset_domain Signed-off-by:
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Tom St Denis authored
The 10.3 GC headers were missing most of the pwrdec block. This patch adds the registers and bits present in the 10.1 header but based on the contents of the 10.3 specs. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Rajneesh Bhardwaj authored
Recently introduced change to allocate doorbells only when the first queue is created or mapped for CPU / GPU access, did not consider Checkpoint Restore scenario completely. This fix allows the CRIU restore operation by extending the doorbell optimization to CRIU restore scenario. Fixes: 16f00131 ("drm/amdkfd: Allocate doorbells only when needed") Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Hamza Mahfooz authored
Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs struct. Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
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Lijo Lazar authored
As per PCIE Base Spec r4.0 Section 6.18 'Software must not enable LTR in an Endpoint unless the Root Complex and all intermediate Switches indicate support for LTR.' This fixes the Unsupported Request error reported through AER during ASPM enablement. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216455 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182 ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Reported-by:
Gustaw Smolarczyk <wielkiegie@gmail.com> Signed-off-by:
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Guchun Chen authored
To avoid hardware intermittent failures. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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- 12 Sep, 2022 2 commits
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2022-09-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709" The intent of Wa_14015141709 was to inform us that userspace can no longer control object-level preemption as it has on past platforms (i.e., by twiddling register bit CS_CHICKEN1[0]). The description of the workaround in the spec wasn't terribly well-written, and when we requested clarification from the hardware teams we were told that on the kernel side we should also probably stop setting FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the hardware to honor the settings in per-context register CS_CHICKEN1. It turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a mistake; even though CS_CHICKEN1[0] is non-operational and useless to userspace, there are other bits in the register that do still work and might need to be adjusted by userspace in the future (e.g., to implement other workarounds that show up). If we don't set FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would not take effect. Even more details at: https://lists.freedesktop.org/archives/intel-gfx/2022-September/305478.html Driver Changes: - Align GuC/HuC firmware versioning scheme to kernel practices (John) - Fix #6639: h264 hardware video decoding broken in 5.19 on Intel(R) Celeron(R) N3060 (Nirmoy) - Meteorlake (MTL) enabling (Matt R) - GuC SLPC improvements (Vinay, Rodrigo) - Add thread execution tuning setting for ATS-M (Matt R) - Don't start PXP without mei_pxp bind (Juston) - Remove leftover verbose debug logging from GuC error capture (John) - Abort suspend on low system memory conditions (Nirmoy, Matt A, Chris) - Add DG2 Wa_16014892111 (Matt R) - Rename ggtt_view as gtt_view (Niranjana) - Consider HAS_FLAT_CCS() in needs_ccs_pages (Matt A) - Don't try to disable host RPS when this was never enabled. (Rodrigo) - Clear stalled GuC CT request after a reset (Daniele) - Remove runtime info printing from GuC time stamp logging (Jani) - Skip Bit12 fw domain reset for gen12+ (Sushma, Radhakrishna) - Make GuC log sizes runtime configurable (John) - Selftest improvements (Daniele, Matt B, Andrzej) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YxshfqUN+vDe92Zn@jlahtine-mobl.ger.corp.intel.com
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.1-2022-09-08: amdgpu: - Mode2 reset for RDNA2 - Lots of new DC documentation - Add documentation about different asic families - DSC improvements - Aldebaran fixes - Misc spelling and grammar fixes - GFXOFF stats support for vangogh - DC frame size fixes - NBIO 7.7 updates - DCN 3.2 updates - DCN 3.1.4 Updates - SMU 13.x updates - Misc bug fixes - Rework DC register offset handling - GC 11.x updates - PSP 13.x updates - SDMA 6.x updates - GMC 11.x updates - SR-IOV updates - PSP fixes for TA unloading - DSC passthrough support - Misc code cleanups amdkfd: - ISA fixes for some GC 10.3 IPs - Misc code cleanups radeon: - Delayed work flush fix - Use time_after for some jiffies calculations drm: - DSC passthrough aux support Signed-off-by:
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