- 27 Aug, 2018 40 commits
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Anthony Koo authored
This issue occurs if refresh rate range is very small and lfc is not used. When frame spikes occur, refresh rate becomes fixed and will not restore properly Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Anthony Koo authored
Signed-off-by:
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Anthony Koo authored
Remove dependency on internal sink map and instead use existing stream and plane state Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Harry Wentland authored
Add code to tear down freesync modules when disabled. Signed-off-by:
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Feifei Xu authored
With PSP firmware loading, TMR mc address is supposed to be used. Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Evan Quan authored
Added psp fw loading support for vega20 2nd UVD instance. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Michel Dänzer authored
Fixes: "drm/scheduler: rename gpu_scheduler.c to sched_main.c" Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Christian König authored
Further demangle ring from entity handling. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
Further unmangle amdgpu.h. Signed-off-by:
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Christian König authored
Not needed any more. Signed-off-by:
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Christian König authored
Not needed any more since that is now done by the scheduler. Signed-off-by:
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Christian König authored
Start to use the scheduler load balancing for userspace compute command submissions. Signed-off-by:
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Christian König authored
Start to use the scheduler load balancing for userspace SDMA command submissions. Signed-off-by:
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Christian König authored
Instead of the fixed round robin use let the scheduler balance the load of page table updates. Signed-off-by:
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James Zhu authored
With PSP firmware loading, TMR mc address is supposed to be used. Signed-off-by:
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Christian König authored
Better match the naming of the other components. Signed-off-by:
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Christian König authored
Cleanup coding style in sched_entity.c Signed-off-by:
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Christian König authored
This is complex enough on it's own. Move it into a separate C file. Signed-off-by:
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Christian König authored
Return -ENOMEM when allocating the rq_list fails. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Dan Carpenter authored
We accidentally left out the size of the amdgpu_bo_list struct. It could lead to memory corruption on 32 bit systems. You'd have to pick the absolute maximum and set "num_entries == 59652323" then size would wrap to 16 bytes. Fixes: 920990cb ("drm/amdgpu: allocate the bo_list array after the list") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Bas Nieuwenhuizen <basni@chromium.org> Signed-off-by:
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Rex Zhu authored
Also ajust the gfx domain voltage on Tonga when user overdriver the voltage. For Tonga, Driver do not update user's setting to voltage table in smu, we only pick up a minimum value from voltage table that not less than the user's setting. v2: fix a typo Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
Cancel the delay work to avoid the corner case that ib test was not running when suspend Reviewed-by:
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Alex Deucher authored
Now that PSP and SMU support is in place. Signed-off-by: -
Feifei Xu authored
Enlarge the PSP TMR SIZE to 4M for dual UVD fw front-door loading. Signed-off-by:
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Evan Quan authored
Updated vega20 SDMA0 and SDMA1 golden settings. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Feifei Xu authored
Update the goldensettings for vega20. Signed-off-by:
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Evan Quan authored
Run AFLL BTC after upload pptable and before enabling all smu features. Signed-off-by:
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Evan Quan authored
The latest SMU fw removes the limitation that required UCLK >= DCEFCLK. Signed-off-by:
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Evan Quan authored
Otherwise there may be potential SMU performance issues. Signed-off-by:
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Evan Quan authored
The argument was set wrongly. Fast/slow switch was asked when there is actually a slow/fast switch needed. Signed-off-by:
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Evan Quan authored
For vega20, there are two UVD rings which share one powerplay instance. Under some case(two rings used parallel), the uvd dpm is disabled twice which causes the SMC hang. Signed-off-by:
Rex Zhu <rezhu@amd.com> Signed-off-by:
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Evan Quan authored
SOC voltage is not able to switch and forced to low 0.8V when running HEVC. Thus the test failed. Signed-off-by:
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Evan Quan authored
Set fclk ss as enabled on default. Signed-off-by:
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Likun Gao authored
Modified the vega20 load type to psp now that psp support is implemented. v2: squash in fixes history (Alex) Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Feifei Xu authored
Add psp 11.0 code for vega20 and enable it. PSP is the security processor for the GPU. It handles firmware loading and GPU resets among other things. v2: whitespace fix, enable support, adjust reg includes (Alex) Signed-off-by:
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Evan Quan authored
Signed-off-by:
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Evan Quan authored
UVD, VCE and SOC clocks need to be taken into consideration. Also, the thresholds need be updated correspondingly when stable power state is selected. Signed-off-by:
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Evan Quan authored
UVD, VCE and Socclk also need to be taken into consideration when setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq. Signed-off-by:
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Evan Quan authored
Add support for the new SMU firmware interface for clock adjustment. Signed-off-by:
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Evan Quan authored
The initialized overdrive settings are taken from vbios and SMU( by PPSMC_MSG_TransferTableSmu2Dram). Signed-off-by:
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