- 10 Jan, 2023 11 commits
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Abel Vesa authored
Add base dtsi for SM8550 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, interconnect, thermal sensor, cpu cooling maps and SMMU nodes which helps boot to shell with console on boards with this SoC. Co-developed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-3-abel.vesa@linaro.org
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Bjorn Andersson authored
Merge the TCSR clock binding, to gain the Devicetree include file.
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Abel Vesa authored
Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Bjorn Andersson authored
Merge branch 'icc-sm8550-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.3 Merge the immutable SM8550 interconnect branch, to gain the include file from the binding.
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Dmitry Baryshkov authored
Add silicon specific compatible qcom,sm8450-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8450 against the yaml documentation. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Add silicon specific compatible qcom,sm8150-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8150 against the yaml documentation. Signed-off-by:
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Krzysztof Kozlowski authored
Each board should define pin drive/bias for used busses. All boards using SPI0 (db845c and cheza) already do it, so drop the bias/drive strength from SoC DTSI. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Krzysztof Kozlowski authored
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by:
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Krzysztof Kozlowski authored
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: dd6459a0 ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts") Reported-by:
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Krzysztof Kozlowski authored
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: 89a32a4e ("arm64: dts: qcom: db845c: add analog audio support") Reported-by:
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Quentin Schulz authored
The reset line is active low for the Goodix touchscreen controller so let's fix the polarity in the Device Tree node. Signed-off-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com> Tested-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
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- 02 Jan, 2023 7 commits
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Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8350-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8250-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Soundwire is a bus and VA-macro requires a supply, thus both are expected to be explicitly enabled and populated by board DTS. The HDK8450 already enables Soundwire devices, except swr4 which as a result of this commit will stay disabled. Signed-off-by:
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- 29 Dec, 2022 22 commits
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Krzysztof Kozlowski authored
Node names should be generic so use consistently speaker-amp for CS35L41 speaker amplifier. Signed-off-by:
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Krzysztof Kozlowski authored
Bindings expect GCC clocks in other order: sm8450-hdk.dtb: clock-controller@100000: clock-names:1: 'sleep_clk' was expected Signed-off-by:
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Krzysztof Kozlowski authored
Neither qcom,sm8250-lpass-va-macro bindings nor the driver use "clock-frequency" property. Signed-off-by:
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Krzysztof Kozlowski authored
The node names should be generic and the bindings expect "bus" for simple-bus nodes: msm8996-mtp.dtb: agnoc@0: $nodename:0: 'agnoc@0' does not match '^bus(@[0-9a-f]+)?$' Signed-off-by:
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Marijn Suijten authored
Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware connected to them, leaving the rest disabled to save on power. For this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to be connected to Serial Engines on GPU DMA 1 / QUP 1. Beyond this downstream only defines a UART console available on Serial Engine 4 which also resides on QUP 0. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Martin Botka <martin.botka@somainline.org> Reviewed-by:
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Marijn Suijten authored
Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines. QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap in the middle (ranging from 5-9 with SPI 7 missing). Both QUPs have 5 I2C Serial Engines. [Marijn: Add iommus, reword patch description, reorder all properties, sort based on address, use QCOM_GPI_ constants, drop dma cells from 5 to 3] Signed-off-by:
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Martin Botka authored
Add pin setup for SPI/I2C Serial Engines that are supported under the Qualcomm Universal Peripheral found on SM6125. [Un-nest pins, remove duplicate pins= properties, follow new node naming conventions, fix qup_14 -> qup14 function typo] Signed-off-by:
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Marijn Suijten authored
- Remove autorepeat (leave key repetition to userspace); - Remove unneeded status = "okay" (this is the default); - Remove unneeded linux,input-type <EV_KEY> (this is the default for gpio-keys); - Allow the interrupt line for this button to be disabled; - Use a full, descriptive node name; - Set proper bias on the GPIO via pinctrl; - Sort properties; - Replace deprecated gpio-key,wakeup property with wakeup-source. Fixes: 82e17838 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II") Signed-off-by:
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Martin Botka authored
Add nodes for GPI DMA hosts on SM6125. [Marijn: reorder properties, use sdm845 fallback compatible, disable by default, use 3 instead of 5 dma cells] Signed-off-by:
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AngeloGioacchino Del Regno authored
Add an IOMMU context to the USB DWC3 controller, required to get USB functionality upon enablement of apps_smmu. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Marijn Suijten authored
When enabling the APPS SMMU the mainline driver reconfigures the SMMU from its bootloader configuration, losing the stream mapping for (among which) the SDHCI hardware and breaking its ADMA feature. This feature can be disabled with: sdhci.debug_quirks=0x40 But it is of course desired to have this feature enabled and working through the SMMU. Signed-off-by: -
Martin Botka authored
Add a node for the APPS SMMU, to which various devices such as USB and storage nodes are connected. [Marijn: add the new, generic, "qcom,smmu-500" compatible, add patch description, reorder # properties] Signed-off-by:
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Marijn Suijten authored
Reorder the clocks and corresponding names to match the QUSB2 phy schema, fixing the following CHECK_DTBS errors: arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:0: 'cfg_ahb' was expected From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:1: 'ref' was expected From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml Fixes: cff4bbaf ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: -
Marijn Suijten authored
Ensure the eMMC and SD Card always have a predictable slot index by predetermining them via aliases. Signed-off-by:
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Marijn Suijten authored
Sony's seine board features an SD Card slot on SDHCI 2, that is to be powered by l5 and l22. The card detect pin is already biased via updates on the generic sdc2_*_state pinctrl nodes. As usual regulator voltages are decreased to the maximum voted by the downstream driver for safety. SDHCI 2 is the only hardware block feeding off of these. Signed-off-by:
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Marijn Suijten authored
While SDHCI 1 appears to work out of the box, we cannot rely on the bootloader-enabled regulators nor expect them to remain enabled (e.g. when finally dropping pd_ignore_unused). Provide it the necessary l24 and l11 regulators now that PM6125 regulators have been made available on this board. As usual regulator voltages are decreased to the maximum voted by the downstream driver for safety. No other hardware feeds off of these regulators anyway (except UFS, which isn't used on the seine board in favour of a DV6DMB eMMC card connected to SDHCI 1). Signed-off-by:
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Marijn Suijten authored
Document the use of l7, l10 and l15 in the High Speed Qualcomm USB2 PHY, in order to keep the regulators voted on when USB is active. Signed-off-by:
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Marijn Suijten authored
Configure PM6125 regulators based on availability and voltages defined downstream, to allow powering up (and/or keeping powered) other hardware blocks going forward. Signed-off-by:
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Marijn Suijten authored
Pinctrl states typically collate multiple related pins. In the case of gpio-keys there's no hardware-defined relation at all except all pins representing a key; and especially on Sony's lena board there's only one pin regardless. Flatten it similar to other boards [1]. As a drive-by fix, clean up the label string. [1]: https://lore.kernel.org/linux-arm-msm/11174eb6-0a9d-7df1-6f06-da4010f76453@linaro.org/ Fixes: 2b8bbe98 ("arm64: dts: qcom: sm6350-lena: Include pm6350 and configure buttons") Signed-off-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sm8250-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8250 against the yaml documentation. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sdm845-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sdm845 against the yaml documentation. Reviewed-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sdm660-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sdm660 against the yaml documentation. Signed-off-by:
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