- 14 Feb, 2021 14 commits
-
-
Taniya Das authored
Add support for RPMH clocks on SC7280 SoCs. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1612977230-11566-3-git-send-email-tdas@codeaurora.orgSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
-
Taniya Das authored
Add bindings and update documentation for clock rpmh driver on SC7280. Signed-off-by:
-
Vinod Koul authored
Add the GDSC found in GCC for SM8350 SoC Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210210161649.431741-1-vkoul@kernel.orgSigned-off-by:
-
AngeloGioacchino Del Regno authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SDM630 and SDM660 SoCs. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-10-angelogioacchino.delregno@somainline.orgReviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
AngeloGioacchino Del Regno authored
The GPUCC manages the clocks for the Adreno GPU found on the SDM630, SDM636, SDM660 SoCs. Signed-off-by:
-
AngeloGioacchino Del Regno authored
In the previous commit ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops) were generalized in order to be able to reuse the same ops for more than just one clock for one SoC: follow the change here in the MSM8996 MMCC. Signed-off-by: -
AngeloGioacchino Del Regno authored
The function clk_gfx3d_determine_rate is selecting different PLLs to manage the GFX3D clock source in a special way: this one needs to be ping-pong'ed on different PLLs to ensure stability during frequency switching (set a PLL rate, let it stabilize, switch the RCG to the new PLL) and fast frequency transitions. This technique is currently being used in the MSM8996 SoC and the function was assuming that the parents were always at a specific index in the parents list, which is TRUE, if we use this only on the MSM8996 MMCC. Unfortunately, MSM8996 is not the only SoC that needs to ping-pong the graphics RCG, so choices are: 1. Make new special ops just to hardcode *again* other indexes, creating code duplication for (imo) no reason; or 2. Generalize this function, so that it becomes usable for a range of SoCs with slightly different ping-pong configuration. In this commit, the second road was taken: define a new "special" struct clk_rcg2_gfx3d, containing the ordered list of parents to ping-pong the graphics clock on, and the "regular" rcg2 clock structure in order to generalize the clk_gfx3d_determine_rate function and make it working for other SoCs. As for the function itself it is left with the assumption that we need to ping-pong over three parents. The reasons for this are: 1. The initial model was MSM8996, which has 3 parents for the graphics clock pingpong; 2. The other example that was taken into consideration is the SDM630/636/660 SoC gpu clock controller, which is ping-ponging over two dynamic clocked and one fixed clock PLL. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Document the multimedia clock controller found on SDM630/660. Signed-off-by:
-
Martin Botka authored
Add a driver for the multimedia clock controller found on SDM660 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by:
Martin Botka <martin.botka@somainline.org> Co-developed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
-
AngeloGioacchino Del Regno authored
This clock is critical for any access to the GPU: gating it will crash the system when the GPU has been initialized (so, you cannot gate it unless you deinit the Adreno completely). So, to achieve a working state with GPU on, set the CLK_IS_CRITICAL flag to this clock. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Similarly to MSM8998, any access to the MMSS depends on this clock. Gating it will crash the system when RPMCC inits mmssnoc_axi_rpm_clk. Signed-off-by:
-
AngeloGioacchino Del Regno authored
The GPU PLL0 is not a fixed PLL and the rate can be set on it: this is necessary especially on boards which bootloader is setting a very low rate on this PLL before booting Linux, which would be unsuitable for postdividing to reach the maximum allowed Adreno GPU frequency of 710MHz (or, actually, even 670MHz..) on this SoC. To allow setting rates on the GPU PLL0, also define VCO boundaries and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider. With this change, the Adreno GPU is now able to scale through all the available frequencies. Signed-off-by:
-
AngeloGioacchino Del Regno authored
The GPU GX GDSC has GPU_GX_BCR reset and gfx3d_clk CXC, as stated on downstream kernels (and as verified upstream, because otherwise random lockups happen). Also, add PWRSTS_RET and NO_RET_PERIPH: also as found downstream, and also as verified here, to avoid GPU related lockups it is necessary to force retain mem, but *not* peripheral when enabling this GDSC (and, of course, the inverse on disablement). With this change, the GPU finally works flawlessly on my four different MSM8998 devices from two different manufacturers. Signed-off-by:
-
AngeloGioacchino Del Regno authored
In some rare occasions, we want to only set the RETAIN_MEM bit, but not the RETAIN_PERIPH one: this is seen on at least SDM630/636/660's GPU-GX GDSC, where unsetting and setting back the RETAIN_PERIPH bit will generate chaos and panics during GPU suspend time (mainly, the chaos is unaligned access). For this reason, introduce a new NO_RET_PERIPH flag to the GDSC driver to address this corner case. Signed-off-by:
-
- 08 Feb, 2021 26 commits
-
-
AngeloGioacchino Del Regno authored
This GDSC enables (or cuts!) power to the Multimedia Subsystem IOMMU (mmss smmu), which has bootloader pre-set secure contexts. In the event of a complete power loss, the secure contexts will be reset and the hypervisor will crash the SoC. To prevent this, and get a working multimedia subsystem, set this GDSC as always on. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Hardware clock gating is supported on some of the clocks declared in there: ignoring that it does exist may lead to unstabilities on some firmwares. Add the HWCG registers where applicable to stop potential crashes. This was verified on a smartphone shipped with a recent MSM8998 firmware, which will experience random crashes without this change. Signed-off-by:
-
AngeloGioacchino Del Regno authored
All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs and not generic alphas: this was producing bad effects over the entire clock tree of MSM8998, where any GPLL child clock was declaring a false clock rate, due to their parent also showing the same. The issue resides in the calculation of the clock rate for the specific Alpha PLL type, where Fabia has a different register layout; switching the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate (calculation) reading. While at it, also make these PLLs fixed since their rate is supposed to *never* be changed while the system runs, as this would surely crash the entire SoC. Now all the children of all the PLLs are also complying with their specified clock table and system stability is improved. Fixes: b5f5f525 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by:
-
AngeloGioacchino Del Regno authored
The GPU IOMMU depends on this clock and the hypervisor will crash the SoC if this clock gets disabled because the secure contexts that have been set on this IOMMU by the bootloader will become unaccessible (or they get reset). Mark this clock as critical to avoid this issue when the Adreno GPU is enabled. Signed-off-by:
-
AngeloGioacchino Del Regno authored
To achieve CPR-Hardened functionality this clock must be on: add it in order to be able to get it managed by the CPR3 driver. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Add new clock definition to gcc-msm8998 dt-bindings Signed-off-by:
-
AngeloGioacchino Del Regno authored
This clock enables the GPLL0 output to the multimedia subsystem clock controller. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Add new clock definition to gcc-msm8998 dt-bindings. Signed-off-by:
-
Bryan O'Donoghue authored
This commit adds a regulator supply hook to mmcx-reg missing from - mvs0c_gdsc - mvs1c_gdsc - mvs0_gdsc - mvs1_gdsc Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by:
-
Bryan O'Donoghue authored
This patch adds the missing video_cc_mvs0_clk entry to videocc-sm8250 replicating in upstream the explicit entry for this clock in downstream. Signed-off-by:
-
Bryan O'Donoghue authored
This patch adds the missing video_cc_mvs0_div_clk_src entry to videocc-sm8250 replicating in upstream the explicit entry for this clock in downstream. Signed-off-by:
-
Bryan O'Donoghue authored
Two indexes need to be added to videocc-sm8250.h for venus to function properly. Rather than adding the missing indexes when used we add them separately here to keep checkpatch.pl happy. Signed-off-by:
-
Vivek Aknurwar authored
This adds Global Clock controller (GCC) driver for SM8350 SoC Signed-off-by:
Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by:
Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-6-vkoul@kernel.orgSigned-off-by:
-
Vinod Koul authored
Add device tree bindings for global clock controller on SM8350 SoCs. Reviewed-by:
-
Vivek Aknurwar authored
Lucid 5LPE is a slightly different Lucid PLL with different offsets and porgramming sequence so add support for these Signed-off-by:
-
Vinod Koul authored
Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but with different registers. Modularize these by moving out latch and latch ack bits so that we can reuse the function. Suggested-by:
-
Vinod Koul authored
Driver uses regval variable for holding register values, replace with a shorter one val Suggested-by:
-
Bjorn Andersson authored
Add clocks, resets and some of the GDSC provided by the global clock controller found in the Qualcomm SC8180x platform. Signed-off-by:
-
Bjorn Andersson authored
Add devicetree binding for the global clock controller found in the Qualcomm SC8180x platform. Signed-off-by:
-
Taniya Das authored
There are intermittent GDSC power-up failures observed for titan top gdsc, which requires the XO clock. Thus mark all the MM XO clocks always enabled from probe. Fixes: 8d402594 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Signed-off-by:
-
Bjorn Andersson authored
Add clocks provides by RPMH in the Qualcomm SC8180x platform. Signed-off-by:
-
Bjorn Andersson authored
Add Qualcomm SC8180x to the list of compatibles for the RPMHCC binding. Signed-off-by:
-
Srinivas Kandagatla authored
For some reason global GFM_MASK ended up with bit 1 instead of bit 0. Remove the global GFM_MASK and reuse mux_mask field. Fixes: a2d8f507 ("clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks") Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210119113851.18946-1-srinivas.kandagatla@linaro.orgSigned-off-by:
-
Manivannan Sadhasivam authored
Add a driver for the SDX55 APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL This is required for enabling CPU frequency scaling on SDX55-based platforms. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-6-manivannan.sadhasivam@linaro.org [sboyd@kernel.org: Fix unused ret in probe by hardcoding it] Signed-off-by:
-
Manivannan Sadhasivam authored
Add support for PLL found in Qualcomm SDX55 platforms which is used to provide clock to the Cortex A7 CPU via a mux. This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by:
-
Manivannan Sadhasivam authored
Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm platforms like SDX55. Signed-off-by:
-
