bnx2x_main.c 324 KB
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/* bnx2x_main.c: Broadcom Everest network driver.
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 *
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 * Copyright (c) 2007-2009 Broadcom Corporation
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
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 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
 * Written by: Eliezer Tamir
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 * Based on code from Michael Chan's bnx2 driver
 * UDP CSUM errata workaround by Arik Gendelman
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 * Slowpath and fastpath rework by Vladislav Zolotarov
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 * Statistics and Link management by Yitchak Gertner
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 *
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>  /* for dev_info() */
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
#include <linux/time.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
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#include <linux/if_vlan.h>
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#include <net/ip.h>
#include <net/tcp.h>
#include <net/checksum.h>
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#include <net/ip6_checksum.h>
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#include <linux/workqueue.h>
#include <linux/crc32.h>
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#include <linux/crc32c.h>
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#include <linux/prefetch.h>
#include <linux/zlib.h>
#include <linux/io.h>

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#include "bnx2x.h"
#include "bnx2x_init.h"
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#include "bnx2x_init_ops.h"
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#include "bnx2x_dump.h"
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#define DRV_MODULE_VERSION	"1.48.114-1"
#define DRV_MODULE_RELDATE	"2009/07/29"
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#define BNX2X_BC_VER		0x040200
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#include <linux/firmware.h>
#include "bnx2x_fw_file_hdr.h"
/* FW files */
#define FW_FILE_PREFIX_E1		"bnx2x-e1-"
#define FW_FILE_PREFIX_E1H		"bnx2x-e1h-"

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/* Time in jiffies before concluding the transmitter is hung */
#define TX_TIMEOUT		(5*HZ)
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static char version[] __devinitdata =
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	"Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
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	DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

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MODULE_AUTHOR("Eliezer Tamir");
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MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
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MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);

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static int multi_mode = 1;
module_param(multi_mode, int, 0);
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MODULE_PARM_DESC(multi_mode, " Multi queue mode "
			     "(0 Disable; 1 Enable (default))");

static int num_rx_queues;
module_param(num_rx_queues, int, 0);
MODULE_PARM_DESC(num_rx_queues, " Number of Rx queues for multi_mode=1"
				" (default is half number of CPUs)");

static int num_tx_queues;
module_param(num_tx_queues, int, 0);
MODULE_PARM_DESC(num_tx_queues, " Number of Tx queues for multi_mode=1"
				" (default is half number of CPUs)");
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static int disable_tpa;
module_param(disable_tpa, int, 0);
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MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
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static int int_mode;
module_param(int_mode, int, 0);
MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");

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static int poll;
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module_param(poll, int, 0);
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MODULE_PARM_DESC(poll, " Use polling (for debug)");
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static int mrrs = -1;
module_param(mrrs, int, 0);
MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");

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static int debug;
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module_param(debug, int, 0);
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MODULE_PARM_DESC(debug, " Default debug msglevel");

static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
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static struct workqueue_struct *bnx2x_wq;
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enum bnx2x_board_type {
	BCM57710 = 0,
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	BCM57711 = 1,
	BCM57711E = 2,
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};

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/* indexed by board_type, above */
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static struct {
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	char *name;
} board_info[] __devinitdata = {
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	{ "Broadcom NetXtreme II BCM57710 XGb" },
	{ "Broadcom NetXtreme II BCM57711 XGb" },
	{ "Broadcom NetXtreme II BCM57711E XGb" }
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};

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static const struct pci_device_id bnx2x_pci_tbl[] = {
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
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	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
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	{ 0 }
};

MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);

/****************************************************************************
* General service functions
****************************************************************************/

/* used only at init
 * locking is done by mcp
 */
static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
{
	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
	pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
			       PCICFG_VENDOR_ID_OFFSET);
}

static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
{
	u32 val;

	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
	pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
			       PCICFG_VENDOR_ID_OFFSET);

	return val;
}

static const u32 dmae_reg_go_c[] = {
	DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
	DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
	DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
	DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
};

/* copy command into DMAE command memory and set DMAE command go */
static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
			    int idx)
{
	u32 cmd_offset;
	int i;

	cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
	for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
		REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));

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		DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
		   idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
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	}
	REG_WR(bp, dmae_reg_go_c[idx], 1);
}

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void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
		      u32 len32)
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{
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	struct dmae_command *dmae = &bp->init_dmae;
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	u32 *wb_comp = bnx2x_sp(bp, wb_comp);
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	int cnt = 200;

	if (!bp->dmae_ready) {
		u32 *data = bnx2x_sp(bp, wb_data[0]);

		DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
		   "  using indirect\n", dst_addr, len32);
		bnx2x_init_ind_wr(bp, dst_addr, data, len32);
		return;
	}

	mutex_lock(&bp->dmae_mutex);
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	memset(dmae, 0, sizeof(struct dmae_command));

	dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
			DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
			DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
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			(BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
			(BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
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	dmae->src_addr_lo = U64_LO(dma_addr);
	dmae->src_addr_hi = U64_HI(dma_addr);
	dmae->dst_addr_lo = dst_addr >> 2;
	dmae->dst_addr_hi = 0;
	dmae->len = len32;
	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
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	dmae->comp_val = DMAE_COMP_VAL;
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	DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
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	   DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
		    "dst_addr [%x:%08x (%08x)]\n"
	   DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
	   dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
	   dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
	   dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
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	DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
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	   bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
	   bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);

	*wb_comp = 0;

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	bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
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	udelay(5);
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	while (*wb_comp != DMAE_COMP_VAL) {
		DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);

		if (!cnt) {
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			BNX2X_ERR("DMAE timeout!\n");
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			break;
		}
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		cnt--;
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		/* adjust delay for emulation/FPGA */
		if (CHIP_REV_IS_SLOW(bp))
			msleep(100);
		else
			udelay(5);
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	}
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	mutex_unlock(&bp->dmae_mutex);
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}

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void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
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{
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	struct dmae_command *dmae = &bp->init_dmae;
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	u32 *wb_comp = bnx2x_sp(bp, wb_comp);
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	int cnt = 200;

	if (!bp->dmae_ready) {
		u32 *data = bnx2x_sp(bp, wb_data[0]);
		int i;

		DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
		   "  using indirect\n", src_addr, len32);
		for (i = 0; i < len32; i++)
			data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
		return;
	}

	mutex_lock(&bp->dmae_mutex);
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	memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
	memset(dmae, 0, sizeof(struct dmae_command));

	dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
			DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
			DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
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			(BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
			(BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
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	dmae->src_addr_lo = src_addr >> 2;
	dmae->src_addr_hi = 0;
	dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
	dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
	dmae->len = len32;
	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
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	dmae->comp_val = DMAE_COMP_VAL;
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	DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
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	   DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
		    "dst_addr [%x:%08x (%08x)]\n"
	   DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
	   dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
	   dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
	   dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);

	*wb_comp = 0;

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	bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
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	udelay(5);
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	while (*wb_comp != DMAE_COMP_VAL) {

		if (!cnt) {
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			BNX2X_ERR("DMAE timeout!\n");
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			break;
		}
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		cnt--;
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		/* adjust delay for emulation/FPGA */
		if (CHIP_REV_IS_SLOW(bp))
			msleep(100);
		else
			udelay(5);
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	}
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	DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
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	   bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
	   bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
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	mutex_unlock(&bp->dmae_mutex);
}

/* used only for slowpath so not inlined */
static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
{
	u32 wb_write[2];

	wb_write[0] = val_hi;
	wb_write[1] = val_lo;
	REG_WR_DMAE(bp, reg, wb_write, 2);
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}

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#ifdef USE_WB_RD
static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
{
	u32 wb_data[2];

	REG_RD_DMAE(bp, reg, wb_data, 2);

	return HILO_U64(wb_data[0], wb_data[1]);
}
#endif

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static int bnx2x_mc_assert(struct bnx2x *bp)
{
	char last_idx;
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	int i, rc = 0;
	u32 row0, row1, row2, row3;

	/* XSTORM */
	last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
			   XSTORM_ASSERT_LIST_INDEX_OFFSET);
	if (last_idx)
		BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);

	/* print the asserts */
	for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {

		row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
			      XSTORM_ASSERT_LIST_OFFSET(i));
		row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
			      XSTORM_ASSERT_LIST_OFFSET(i) + 4);
		row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
			      XSTORM_ASSERT_LIST_OFFSET(i) + 8);
		row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
			      XSTORM_ASSERT_LIST_OFFSET(i) + 12);

		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
			BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
				  " 0x%08x 0x%08x 0x%08x\n",
				  i, row3, row2, row1, row0);
			rc++;
		} else {
			break;
		}
	}

	/* TSTORM */
	last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
			   TSTORM_ASSERT_LIST_INDEX_OFFSET);
	if (last_idx)
		BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);

	/* print the asserts */
	for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {

		row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
			      TSTORM_ASSERT_LIST_OFFSET(i));
		row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
			      TSTORM_ASSERT_LIST_OFFSET(i) + 4);
		row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
			      TSTORM_ASSERT_LIST_OFFSET(i) + 8);
		row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
			      TSTORM_ASSERT_LIST_OFFSET(i) + 12);

		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
			BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
				  " 0x%08x 0x%08x 0x%08x\n",
				  i, row3, row2, row1, row0);
			rc++;
		} else {
			break;
		}
	}

	/* CSTORM */
	last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
			   CSTORM_ASSERT_LIST_INDEX_OFFSET);
	if (last_idx)
		BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);

	/* print the asserts */
	for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {

		row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
			      CSTORM_ASSERT_LIST_OFFSET(i));
		row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
			      CSTORM_ASSERT_LIST_OFFSET(i) + 4);
		row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
			      CSTORM_ASSERT_LIST_OFFSET(i) + 8);
		row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
			      CSTORM_ASSERT_LIST_OFFSET(i) + 12);

		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
			BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
				  " 0x%08x 0x%08x 0x%08x\n",
				  i, row3, row2, row1, row0);
			rc++;
		} else {
			break;
		}
	}

	/* USTORM */
	last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
			   USTORM_ASSERT_LIST_INDEX_OFFSET);
	if (last_idx)
		BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);

	/* print the asserts */
	for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {

		row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
			      USTORM_ASSERT_LIST_OFFSET(i));
		row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
			      USTORM_ASSERT_LIST_OFFSET(i) + 4);
		row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
			      USTORM_ASSERT_LIST_OFFSET(i) + 8);
		row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
			      USTORM_ASSERT_LIST_OFFSET(i) + 12);

		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
			BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
				  " 0x%08x 0x%08x 0x%08x\n",
				  i, row3, row2, row1, row0);
			rc++;
		} else {
			break;
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		}
	}
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	return rc;
}
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static void bnx2x_fw_dump(struct bnx2x *bp)
{
	u32 mark, offset;
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	__be32 data[9];
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	int word;

	mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
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	mark = ((mark + 0x3) & ~0x3);
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	printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n", mark);
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	printk(KERN_ERR PFX);
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	for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
		for (word = 0; word < 8; word++)
			data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
						  offset + 4*word));
		data[8] = 0x0;
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		printk(KERN_CONT "%s", (char *)data);
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	}
	for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
		for (word = 0; word < 8; word++)
			data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
						  offset + 4*word));
		data[8] = 0x0;
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		printk(KERN_CONT "%s", (char *)data);
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	}
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	printk(KERN_ERR PFX "end of fw dump\n");
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}

static void bnx2x_panic_dump(struct bnx2x *bp)
{
	int i;
	u16 j, start, end;

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	bp->stats_state = STATS_STATE_DISABLED;
	DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");

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	BNX2X_ERR("begin crash dump -----------------\n");

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	/* Indices */
	/* Common */
	BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
		  "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
		  "  spq_prod_idx(%u)\n",
		  bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
		  bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);

	/* Rx */
	for_each_rx_queue(bp, i) {
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		struct bnx2x_fastpath *fp = &bp->fp[i];

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		BNX2X_ERR("fp%d: rx_bd_prod(%x)  rx_bd_cons(%x)"
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			  "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
			  "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
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			  i, fp->rx_bd_prod, fp->rx_bd_cons,
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			  le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
			  fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
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		BNX2X_ERR("      rx_sge_prod(%x)  last_max_sge(%x)"
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			  "  fp_u_idx(%x) *sb_u_idx(%x)\n",
			  fp->rx_sge_prod, fp->last_max_sge,
			  le16_to_cpu(fp->fp_u_idx),
			  fp->status_blk->u_status_block.status_block_index);
	}
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	/* Tx */
	for_each_tx_queue(bp, i) {
		struct bnx2x_fastpath *fp = &bp->fp[i];
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		BNX2X_ERR("fp%d: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
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			  "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
			  i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
			  fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
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		BNX2X_ERR("      fp_c_idx(%x)  *sb_c_idx(%x)"
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			  "  tx_db_prod(%x)\n", le16_to_cpu(fp->fp_c_idx),
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			  fp->status_blk->c_status_block.status_block_index,
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			  fp->tx_db.data.prod);
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	}
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	/* Rings */
	/* Rx */
	for_each_rx_queue(bp, i) {
		struct bnx2x_fastpath *fp = &bp->fp[i];
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		start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
		end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
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		for (j = start; j != end; j = RX_BD(j + 1)) {
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			u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
			struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];

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			BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
				  i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
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		}

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		start = RX_SGE(fp->rx_sge_prod);
		end = RX_SGE(fp->last_max_sge);
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		for (j = start; j != end; j = RX_SGE(j + 1)) {
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			u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
			struct sw_rx_page *sw_page = &fp->rx_page_ring[j];

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			BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
				  i, j, rx_sge[1], rx_sge[0], sw_page->page);
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		}

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		start = RCQ_BD(fp->rx_comp_cons - 10);
		end = RCQ_BD(fp->rx_comp_cons + 503);
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		for (j = start; j != end; j = RCQ_BD(j + 1)) {
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			u32 *cqe = (u32 *)&fp->rx_comp_ring[j];

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			BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
				  i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
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		}
	}

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	/* Tx */
	for_each_tx_queue(bp, i) {
		struct bnx2x_fastpath *fp = &bp->fp[i];

		start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
		end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
		for (j = start; j != end; j = TX_BD(j + 1)) {
			struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];

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			BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
				  i, j, sw_bd->skb, sw_bd->first_bd);
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		}

		start = TX_BD(fp->tx_bd_cons - 10);
		end = TX_BD(fp->tx_bd_cons + 254);
		for (j = start; j != end; j = TX_BD(j + 1)) {
			u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];

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			BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
				  i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
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		}
	}
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	bnx2x_fw_dump(bp);
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	bnx2x_mc_assert(bp);
	BNX2X_ERR("end crash dump -----------------\n");
}

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static void bnx2x_int_enable(struct bnx2x *bp)
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{
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	int port = BP_PORT(bp);
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	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
	u32 val = REG_RD(bp, addr);
	int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
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	int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
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	if (msix) {
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		val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
			 HC_CONFIG_0_REG_INT_LINE_EN_0);
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		val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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	} else if (msi) {
		val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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	} else {
		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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			HC_CONFIG_0_REG_INT_LINE_EN_0 |
			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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		DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
		   val, port, addr);
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		REG_WR(bp, addr, val);

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		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
	}

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	DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
	   val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
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	REG_WR(bp, addr, val);
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	/*
	 * Ensure that HC_CONFIG is written before leading/trailing edge config
	 */
	mmiowb();
	barrier();
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	if (CHIP_IS_E1H(bp)) {
		/* init leading/trailing edge */
		if (IS_E1HMF(bp)) {
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			val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
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			if (bp->port.pmf)
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				/* enable nig and gpio3 attention */
				val |= 0x1100;
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		} else
			val = 0xffff;

		REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
		REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
	}
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	/* Make sure that interrupts are indeed enabled from here on */
	mmiowb();
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}

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static void bnx2x_int_disable(struct bnx2x *bp)
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{
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	int port = BP_PORT(bp);
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	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
	u32 val = REG_RD(bp, addr);

	val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
		 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
		 HC_CONFIG_0_REG_INT_LINE_EN_0 |
		 HC_CONFIG_0_REG_ATTN_BIT_EN_0);

	DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
	   val, port, addr);

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	/* flush all outstanding writes */
	mmiowb();

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	REG_WR(bp, addr, val);
	if (REG_RD(bp, addr) != val)
		BNX2X_ERR("BUG! proper val not read from IGU!\n");
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}

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static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
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{
	int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
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	int i, offset;
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	/* disable interrupt handling */
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	atomic_inc(&bp->intr_sem);
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	smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */

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	if (disable_hw)
		/* prevent the HW from sending interrupts */
		bnx2x_int_disable(bp);
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	/* make sure all ISRs are done */
	if (msix) {
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		synchronize_irq(bp->msix_table[0].vector);
		offset = 1;
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		for_each_queue(bp, i)
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			synchronize_irq(bp->msix_table[i + offset].vector);
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	} else
		synchronize_irq(bp->pdev->irq);

	/* make sure sp_task is not running */
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	cancel_delayed_work(&bp->sp_task);
	flush_workqueue(bnx2x_wq);
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}

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/* fast path */
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/*
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 * General service functions
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 */

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static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
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				u8 storm, u16 index, u8 op, u8 update)
{
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	u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
		       COMMAND_REG_INT_ACK);
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	struct igu_ack_register igu_ack;

	igu_ack.status_block_index = index;
	igu_ack.sb_id_and_flags =
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			((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
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			 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
			 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
			 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));

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	DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
	   (*(u32 *)&igu_ack), hc_addr);
	REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
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	/* Make sure that ACK is written */
	mmiowb();
	barrier();
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}

static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
{
	struct host_status_block *fpsb = fp->status_blk;
	u16 rc = 0;

	barrier(); /* status block is written to by the chip */
	if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
		fp->fp_c_idx = fpsb->c_status_block.status_block_index;
		rc |= 1;
	}
	if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
		fp->fp_u_idx = fpsb->u_status_block.status_block_index;
		rc |= 2;
	}
	return rc;
}

static u16 bnx2x_ack_int(struct bnx2x *bp)
{
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	u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
		       COMMAND_REG_SIMD_MASK);
	u32 result = REG_RD(bp, hc_addr);
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	DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
	   result, hc_addr);
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	return result;
}


/*
 * fast path service functions
 */

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static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
{
	/* Tell compiler that consumer and producer can change */
	barrier();
	return (fp->tx_pkt_prod != fp->tx_pkt_cons);
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}

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/* free skb in the packet ring at pos idx
 * return idx of last bd freed
 */
static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
			     u16 idx)
{
	struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
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	struct eth_tx_start_bd *tx_start_bd;
	struct eth_tx_bd *tx_data_bd;
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	struct sk_buff *skb = tx_buf->skb;
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	u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
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	int nbd;

	DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
	   idx, tx_buf, skb);

	/* unmap first bd */
	DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
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	tx_start_bd = &fp->tx_desc_ring[bd_idx].start_bd;
	pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_start_bd),
			 BD_UNMAP_LEN(tx_start_bd), PCI_DMA_TODEVICE);
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	nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
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#ifdef BNX2X_STOP_ON_ERROR
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	if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
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		BNX2X_ERR("BAD nbd!\n");
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		bnx2x_panic();
	}
#endif
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	new_cons = nbd + tx_buf->first_bd;
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	/* Get the next bd */
	bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
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	/* Skip a parse bd... */
	--nbd;
	bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));

	/* ...and the TSO split header bd since they have no mapping */
	if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
		--nbd;
		bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
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	}

	/* now free frags */
	while (nbd > 0) {

		DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
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		tx_data_bd = &fp->tx_desc_ring[bd_idx].reg_bd;
		pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_data_bd),
			       BD_UNMAP_LEN(tx_data_bd), PCI_DMA_TODEVICE);
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		if (--nbd)
			bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
	}

	/* release skb */
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	WARN_ON(!skb);
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	dev_kfree_skb_any(skb);
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	tx_buf->first_bd = 0;
	tx_buf->skb = NULL;

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	return new_cons;
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}

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static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
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{
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	s16 used;
	u16 prod;
	u16 cons;
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	barrier(); /* Tell compiler that prod and cons can change */
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	prod = fp->tx_bd_prod;
	cons = fp->tx_bd_cons;

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	/* NUM_TX_RINGS = number of "next-page" entries
	   It will be used as a threshold */
	used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
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#ifdef BNX2X_STOP_ON_ERROR
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	WARN_ON(used < 0);
	WARN_ON(used > fp->bp->tx_ring_size);
	WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
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#endif
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	return (s16)(fp->bp->tx_ring_size) - used;
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}

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static void bnx2x_tx_int(struct bnx2x_fastpath *fp)
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{
	struct bnx2x *bp = fp->bp;
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	struct netdev_queue *txq;
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	u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
	int done = 0;

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return;
#endif

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	txq = netdev_get_tx_queue(bp->dev, fp->index - bp->num_rx_queues);
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	hw_cons = le16_to_cpu(*fp->tx_cons_sb);
	sw_cons = fp->tx_pkt_cons;

	while (sw_cons != hw_cons) {
		u16 pkt_cons;

		pkt_cons = TX_BD(sw_cons);

		/* prefetch(bp->tx_buf_ring[pkt_cons].skb); */

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		DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
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		   hw_cons, sw_cons, pkt_cons);

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/*		if (NEXT_TX_IDX(sw_cons) != hw_cons) {
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			rmb();
			prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
		}
*/
		bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
		sw_cons++;
		done++;
	}

	fp->tx_pkt_cons = sw_cons;
	fp->tx_bd_cons = bd_cons;

	/* TBD need a thresh? */
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	if (unlikely(netif_tx_queue_stopped(txq))) {
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		/* Need to make the tx_bd_cons update visible to start_xmit()
		 * before checking for netif_tx_queue_stopped().  Without the
		 * memory barrier, there is a small possibility that
		 * start_xmit() will miss it and cause the queue to be stopped
		 * forever.
		 */
		smp_mb();

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		if ((netif_tx_queue_stopped(txq)) &&
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		    (bp->state == BNX2X_STATE_OPEN) &&
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		    (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
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			netif_tx_wake_queue(txq);
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	}
}

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static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
			   union eth_rx_cqe *rr_cqe)
{
	struct bnx2x *bp = fp->bp;
	int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
	int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);

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	DP(BNX2X_MSG_SP,
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	   "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
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	   fp->index, cid, command, bp->state,
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	   rr_cqe->ramrod_cqe.ramrod_type);
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	bp->spq_left++;

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	if (fp->index) {
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		switch (command | fp->state) {
		case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
						BNX2X_FP_STATE_OPENING):
			DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
			   cid);
			fp->state = BNX2X_FP_STATE_OPEN;
			break;

		case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
			DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
			   cid);
			fp->state = BNX2X_FP_STATE_HALTED;
			break;

		default:
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			BNX2X_ERR("unexpected MC reply (%d)  "
				  "fp->state is %x\n", command, fp->state);
			break;
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		}
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		mb(); /* force bnx2x_wait_ramrod() to see the change */
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		return;
	}
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	switch (command | bp->state) {
	case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
		DP(NETIF_MSG_IFUP, "got setup ramrod\n");
		bp->state = BNX2X_STATE_OPEN;
		break;

	case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
		DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
		bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
		fp->state = BNX2X_FP_STATE_HALTED;
		break;

	case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
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		DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
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		bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
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		break;

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	case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
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	case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
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		DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
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		bp->set_mac_pending = 0;
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		break;

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	case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
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	case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DISABLED):
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		DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
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		break;

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	default:
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		BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
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			  command, bp->state);
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		break;
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	}
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	mb(); /* force bnx2x_wait_ramrod() to see the change */
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}

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static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
				     struct bnx2x_fastpath *fp, u16 index)
{
	struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
	struct page *page = sw_buf->page;
	struct eth_rx_sge *sge = &fp->rx_sge_ring[index];

	/* Skip "next page" elements */
	if (!page)
		return;

	pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
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		       SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
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	__free_pages(page, PAGES_PER_SGE_SHIFT);

	sw_buf->page = NULL;
	sge->addr_hi = 0;
	sge->addr_lo = 0;
}

static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
					   struct bnx2x_fastpath *fp, int last)
{
	int i;

	for (i = 0; i < last; i++)
		bnx2x_free_rx_sge(bp, fp, i);
}

static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
				     struct bnx2x_fastpath *fp, u16 index)
{
	struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
	struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
	struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
	dma_addr_t mapping;

	if (unlikely(page == NULL))
		return -ENOMEM;

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	mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
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			       PCI_DMA_FROMDEVICE);
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	if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
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		__free_pages(page, PAGES_PER_SGE_SHIFT);
		return -ENOMEM;
	}

	sw_buf->page = page;
	pci_unmap_addr_set(sw_buf, mapping, mapping);

	sge->addr_hi = cpu_to_le32(U64_HI(mapping));
	sge->addr_lo = cpu_to_le32(U64_LO(mapping));

	return 0;
}

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static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
				     struct bnx2x_fastpath *fp, u16 index)
{
	struct sk_buff *skb;
	struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
	struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
	dma_addr_t mapping;

	skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
	if (unlikely(skb == NULL))
		return -ENOMEM;

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	mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
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				 PCI_DMA_FROMDEVICE);
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	if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
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		dev_kfree_skb(skb);
		return -ENOMEM;
	}

	rx_buf->skb = skb;
	pci_unmap_addr_set(rx_buf, mapping, mapping);

	rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
	rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));

	return 0;
}

/* note that we are not allocating a new skb,
 * we are just moving one from cons to prod
 * we are not creating a new mapping,
 * so there is no need to check for dma_mapping_error().
 */
static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
			       struct sk_buff *skb, u16 cons, u16 prod)
{
	struct bnx2x *bp = fp->bp;
	struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
	struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
	struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
	struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];

	pci_dma_sync_single_for_device(bp->pdev,
				       pci_unmap_addr(cons_rx_buf, mapping),
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				       RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
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	prod_rx_buf->skb = cons_rx_buf->skb;
	pci_unmap_addr_set(prod_rx_buf, mapping,
			   pci_unmap_addr(cons_rx_buf, mapping));
	*prod_bd = *cons_bd;
}

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static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
					     u16 idx)
{
	u16 last_max = fp->last_max_sge;

	if (SUB_S16(idx, last_max) > 0)
		fp->last_max_sge = idx;
}

static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
{
	int i, j;

	for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
		int idx = RX_SGE_CNT * i - 1;

		for (j = 0; j < 2; j++) {
			SGE_MASK_CLEAR_BIT(fp, idx);
			idx--;
		}
	}
}

static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
				  struct eth_fast_path_rx_cqe *fp_cqe)
{
	struct bnx2x *bp = fp->bp;
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	u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
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				     le16_to_cpu(fp_cqe->len_on_bd)) >>
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		      SGE_PAGE_SHIFT;
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	u16 last_max, last_elem, first_elem;
	u16 delta = 0;
	u16 i;

	if (!sge_len)
		return;

	/* First mark all used pages */
	for (i = 0; i < sge_len; i++)
		SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));

	DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
	   sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));

	/* Here we assume that the last SGE index is the biggest */
	prefetch((void *)(fp->sge_mask));
	bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));

	last_max = RX_SGE(fp->last_max_sge);
	last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
	first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;

	/* If ring is not full */
	if (last_elem + 1 != first_elem)
		last_elem++;

	/* Now update the prod */
	for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
		if (likely(fp->sge_mask[i]))
			break;

		fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
		delta += RX_SGE_MASK_ELEM_SZ;
	}

	if (delta > 0) {
		fp->rx_sge_prod += delta;
		/* clear page-end entries */
		bnx2x_clear_sge_mask_next_elems(fp);
	}

	DP(NETIF_MSG_RX_STATUS,
	   "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
	   fp->last_max_sge, fp->rx_sge_prod);
}

static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
{
	/* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
	memset(fp->sge_mask, 0xff,
	       (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));

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	/* Clear the two last indices in the page to 1:
	   these are the indices that correspond to the "next" element,
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	   hence will never be indicated and should be removed from
	   the calculations. */
	bnx2x_clear_sge_mask_next_elems(fp);
}

static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
			    struct sk_buff *skb, u16 cons, u16 prod)
{
	struct bnx2x *bp = fp->bp;
	struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
	struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
	struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
	dma_addr_t mapping;

	/* move empty skb from pool to prod and map it */
	prod_rx_buf->skb = fp->tpa_pool[queue].skb;
	mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
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				 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
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	pci_unmap_addr_set(prod_rx_buf, mapping, mapping);

	/* move partial skb from cons to pool (don't unmap yet) */
	fp->tpa_pool[queue] = *cons_rx_buf;

	/* mark bin state as start - print error if current state != stop */
	if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
		BNX2X_ERR("start of bin not in stop [%d]\n", queue);

	fp->tpa_state[queue] = BNX2X_TPA_START;

	/* point prod_bd to new skb */
	prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
	prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));

#ifdef BNX2X_STOP_ON_ERROR
	fp->tpa_queue_used |= (1 << queue);
#ifdef __powerpc64__
	DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
#else
	DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
#endif
	   fp->tpa_queue_used);
#endif
}

static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
			       struct sk_buff *skb,
			       struct eth_fast_path_rx_cqe *fp_cqe,
			       u16 cqe_idx)
{
	struct sw_rx_page *rx_pg, old_rx_pg;
	u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
	u32 i, frag_len, frag_size, pages;
	int err;
	int j;

	frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
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	pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
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	/* This is needed in order to enable forwarding support */
	if (frag_size)
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		skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
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					       max(frag_size, (u32)len_on_bd));

#ifdef BNX2X_STOP_ON_ERROR
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	if (pages >
	    min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
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		BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
			  pages, cqe_idx);
		BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
			  fp_cqe->pkt_len, len_on_bd);
		bnx2x_panic();
		return -EINVAL;
	}
#endif

	/* Run through the SGL and compose the fragmented skb */
	for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
		u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));

		/* FW gives the indices of the SGE as if the ring is an array
		   (meaning that "next" element will consume 2 indices) */
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		frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
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		rx_pg = &fp->rx_page_ring[sge_idx];
		old_rx_pg = *rx_pg;

		/* If we fail to allocate a substitute page, we simply stop
		   where we are and drop the whole packet */
		err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
		if (unlikely(err)) {
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			fp->eth_q_stats.rx_skb_alloc_failed++;
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			return err;
		}

		/* Unmap the page as we r going to pass it to the stack */
		pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
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			      SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
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		/* Add one frag and update the appropriate fields in the skb */
		skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);

		skb->data_len += frag_len;
		skb->truesize += frag_len;
		skb->len += frag_len;

		frag_size -= frag_len;
	}

	return 0;
}

static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
			   u16 queue, int pad, int len, union eth_rx_cqe *cqe,
			   u16 cqe_idx)
{
	struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
	struct sk_buff *skb = rx_buf->skb;
	/* alloc new skb */
	struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);

	/* Unmap skb in the pool anyway, as we are going to change
	   pool entry status to BNX2X_TPA_STOP even if new skb allocation
	   fails. */
	pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
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			 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
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	if (likely(new_skb)) {
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		/* fix ip xsum and give it to the stack */
		/* (no need to map the new skb) */
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#ifdef BCM_VLAN
		int is_vlan_cqe =
			(le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
			 PARSING_FLAGS_VLAN);
		int is_not_hwaccel_vlan_cqe =
			(is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
#endif
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		prefetch(skb);
		prefetch(((char *)(skb)) + 128);

#ifdef BNX2X_STOP_ON_ERROR
		if (pad + len > bp->rx_buf_size) {
			BNX2X_ERR("skb_put is about to fail...  "
				  "pad %d  len %d  rx_buf_size %d\n",
				  pad, len, bp->rx_buf_size);
			bnx2x_panic();
			return;
		}
#endif

		skb_reserve(skb, pad);
		skb_put(skb, len);

		skb->protocol = eth_type_trans(skb, bp->dev);
		skb->ip_summed = CHECKSUM_UNNECESSARY;

		{
			struct iphdr *iph;

			iph = (struct iphdr *)skb->data;
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#ifdef BCM_VLAN
			/* If there is no Rx VLAN offloading -
			   take VLAN tag into an account */
			if (unlikely(is_not_hwaccel_vlan_cqe))
				iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
#endif
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			iph->check = 0;
			iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
		}

		if (!bnx2x_fill_frag_skb(bp, fp, skb,
					 &cqe->fast_path_cqe, cqe_idx)) {
#ifdef BCM_VLAN
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			if ((bp->vlgrp != NULL) && is_vlan_cqe &&
			    (!is_not_hwaccel_vlan_cqe))
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				vlan_hwaccel_receive_skb(skb, bp->vlgrp,
						le16_to_cpu(cqe->fast_path_cqe.
							    vlan_tag));
			else
#endif
				netif_receive_skb(skb);
		} else {
			DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
			   " - dropping packet!\n");
			dev_kfree_skb(skb);
		}


		/* put new skb in bin */
		fp->tpa_pool[queue].skb = new_skb;

	} else {
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		/* else drop the packet and keep the buffer in the bin */
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		DP(NETIF_MSG_RX_STATUS,
		   "Failed to allocate new skb - dropping packet!\n");
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		fp->eth_q_stats.rx_skb_alloc_failed++;
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	}

	fp->tpa_state[queue] = BNX2X_TPA_STOP;
}

static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
					struct bnx2x_fastpath *fp,
					u16 bd_prod, u16 rx_comp_prod,
					u16 rx_sge_prod)
{
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	struct ustorm_eth_rx_producers rx_prods = {0};
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	int i;

	/* Update producers */
	rx_prods.bd_prod = bd_prod;
	rx_prods.cqe_prod = rx_comp_prod;
	rx_prods.sge_prod = rx_sge_prod;

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	/*
	 * Make sure that the BD and SGE data is updated before updating the
	 * producers since FW might read the BD/SGE right after the producer
	 * is updated.
	 * This is only applicable for weak-ordered memory model archs such
	 * as IA-64. The following barrier is also mandatory since FW will
	 * assumes BDs must have buffers.
	 */
	wmb();

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	for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
		REG_WR(bp, BAR_USTRORM_INTMEM +
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		       USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4,
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		       ((u32 *)&rx_prods)[i]);

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	mmiowb(); /* keep prod updates ordered */

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	DP(NETIF_MSG_RX_STATUS,
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	   "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
	   fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
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}

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static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
{
	struct bnx2x *bp = fp->bp;
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	u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
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	u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
	int rx_pkt = 0;

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return 0;
#endif

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	/* CQ "next element" is of the size of the regular element,
	   that's why it's ok here */
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	hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
	if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
		hw_comp_cons++;

	bd_cons = fp->rx_bd_cons;
	bd_prod = fp->rx_bd_prod;
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	bd_prod_fw = bd_prod;
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	sw_comp_cons = fp->rx_comp_cons;
	sw_comp_prod = fp->rx_comp_prod;

	/* Memory barrier necessary as speculative reads of the rx
	 * buffer can be ahead of the index in the status block
	 */
	rmb();

	DP(NETIF_MSG_RX_STATUS,
	   "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
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	   fp->index, hw_comp_cons, sw_comp_cons);
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	while (sw_comp_cons != hw_comp_cons) {
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		struct sw_rx_bd *rx_buf = NULL;
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		struct sk_buff *skb;
		union eth_rx_cqe *cqe;
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		u8 cqe_fp_flags;
		u16 len, pad;
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		comp_ring_cons = RCQ_BD(sw_comp_cons);
		bd_prod = RX_BD(bd_prod);
		bd_cons = RX_BD(bd_cons);

		cqe = &fp->rx_comp_ring[comp_ring_cons];
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		cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
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		DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
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		   "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
		   cqe_fp_flags, cqe->fast_path_cqe.status_flags,
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		   le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
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		   le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
		   le16_to_cpu(cqe->fast_path_cqe.pkt_len));
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		/* is this a slowpath msg? */
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		if (unlikely(CQE_TYPE(cqe_fp_flags))) {
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			bnx2x_sp_event(fp, cqe);
			goto next_cqe;

		/* this is an rx packet */
		} else {
			rx_buf = &fp->rx_buf_ring[bd_cons];
			skb = rx_buf->skb;
			len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
			pad = cqe->fast_path_cqe.placement_offset;

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			/* If CQE is marked both TPA_START and TPA_END
			   it is a non-TPA CQE */
			if ((!fp->disable_tpa) &&
			    (TPA_TYPE(cqe_fp_flags) !=
					(TPA_TYPE_START | TPA_TYPE_END))) {
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				u16 queue = cqe->fast_path_cqe.queue_index;
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				if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
					DP(NETIF_MSG_RX_STATUS,
					   "calling tpa_start on queue %d\n",
					   queue);

					bnx2x_tpa_start(fp, queue, skb,
							bd_cons, bd_prod);
					goto next_rx;
				}

				if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
					DP(NETIF_MSG_RX_STATUS,
					   "calling tpa_stop on queue %d\n",
					   queue);

					if (!BNX2X_RX_SUM_FIX(cqe))
						BNX2X_ERR("STOP on none TCP "
							  "data\n");

					/* This is a size of the linear data
					   on this skb */
					len = le16_to_cpu(cqe->fast_path_cqe.
								len_on_bd);
					bnx2x_tpa_stop(bp, fp, queue, pad,
						    len, cqe, comp_ring_cons);
#ifdef BNX2X_STOP_ON_ERROR
					if (bp->panic)
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						return 0;
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#endif

					bnx2x_update_sge_prod(fp,
							&cqe->fast_path_cqe);
					goto next_cqe;
				}
			}

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			pci_dma_sync_single_for_device(bp->pdev,
					pci_unmap_addr(rx_buf, mapping),
						       pad + RX_COPY_THRESH,
						       PCI_DMA_FROMDEVICE);
			prefetch(skb);
			prefetch(((char *)(skb)) + 128);

			/* is this an error packet? */
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			if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
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				DP(NETIF_MSG_RX_ERR,
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				   "ERROR  flags %x  rx packet %u\n",
				   cqe_fp_flags, sw_comp_cons);
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				fp->eth_q_stats.rx_err_discard_pkt++;
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				goto reuse_rx;
			}

			/* Since we don't have a jumbo ring
			 * copy small packets if mtu > 1500
			 */
			if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
			    (len <= RX_COPY_THRESH)) {
				struct sk_buff *new_skb;

				new_skb = netdev_alloc_skb(bp->dev,
							   len + pad);
				if (new_skb == NULL) {
					DP(NETIF_MSG_RX_ERR,
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					   "ERROR  packet dropped "
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					   "because of alloc failure\n");
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					fp->eth_q_stats.rx_skb_alloc_failed++;
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					goto reuse_rx;
				}

				/* aligned copy */
				skb_copy_from_linear_data_offset(skb, pad,
						    new_skb->data + pad, len);
				skb_reserve(new_skb, pad);
				skb_put(new_skb, len);

				bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);

				skb = new_skb;

			} else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
				pci_unmap_single(bp->pdev,
					pci_unmap_addr(rx_buf, mapping),
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						 bp->rx_buf_size,
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						 PCI_DMA_FROMDEVICE);
				skb_reserve(skb, pad);
				skb_put(skb, len);

			} else {
				DP(NETIF_MSG_RX_ERR,
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				   "ERROR  packet dropped because "
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				   "of alloc failure\n");
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				fp->eth_q_stats.rx_skb_alloc_failed++;
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reuse_rx:
				bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
				goto next_rx;
			}

			skb->protocol = eth_type_trans(skb, bp->dev);

			skb->ip_summed = CHECKSUM_NONE;
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			if (bp->rx_csum) {
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				if (likely(BNX2X_RX_CSUM_OK(cqe)))
					skb->ip_summed = CHECKSUM_UNNECESSARY;
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				else
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					fp->eth_q_stats.hw_csum_err++;
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			}
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		}

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		skb_record_rx_queue(skb, fp->index);
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#ifdef BCM_VLAN
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		if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
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		    (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
		     PARSING_FLAGS_VLAN))
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			vlan_hwaccel_receive_skb(skb, bp->vlgrp,
				le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
		else
#endif
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			netif_receive_skb(skb);
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next_rx:
		rx_buf->skb = NULL;

		bd_cons = NEXT_RX_IDX(bd_cons);
		bd_prod = NEXT_RX_IDX(bd_prod);
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		bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
		rx_pkt++;
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next_cqe:
		sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
		sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);

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		if (rx_pkt == budget)
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			break;
	} /* while */

	fp->rx_bd_cons = bd_cons;
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	fp->rx_bd_prod = bd_prod_fw;
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	fp->rx_comp_cons = sw_comp_cons;
	fp->rx_comp_prod = sw_comp_prod;

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	/* Update producers */
	bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
			     fp->rx_sge_prod);
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	fp->rx_pkt += rx_pkt;
	fp->rx_calls++;

	return rx_pkt;
}

static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
{
	struct bnx2x_fastpath *fp = fp_cookie;
	struct bnx2x *bp = fp->bp;

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	/* Return here if interrupt is disabled */
	if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
		DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
		return IRQ_HANDLED;
	}

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	DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
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	   fp->index, fp->sb_id);
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	bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
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#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return IRQ_HANDLED;
#endif
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	/* Handle Rx or Tx according to MSI-X vector */
	if (fp->is_rx_queue) {
		prefetch(fp->rx_cons_sb);
		prefetch(&fp->status_blk->u_status_block.status_block_index);
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		napi_schedule(&bnx2x_fp(bp, fp->index, napi));
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	} else {
		prefetch(fp->tx_cons_sb);
		prefetch(&fp->status_blk->c_status_block.status_block_index);

		bnx2x_update_fpsb_idx(fp);
		rmb();
		bnx2x_tx_int(fp);

		/* Re-enable interrupts */
		bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
			     le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
		bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
			     le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
	}
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	return IRQ_HANDLED;
}

static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
{
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	struct bnx2x *bp = netdev_priv(dev_instance);
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	u16 status = bnx2x_ack_int(bp);
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	u16 mask;
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	int i;
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	/* Return here if interrupt is shared and it's not for us */
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	if (unlikely(status == 0)) {
		DP(NETIF_MSG_INTR, "not our interrupt!\n");
		return IRQ_NONE;
	}
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	DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
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	/* Return here if interrupt is disabled */
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	if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
		DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
		return IRQ_HANDLED;
	}

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#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return IRQ_HANDLED;
#endif

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	for (i = 0; i < BNX2X_NUM_QUEUES(bp); i++) {
		struct bnx2x_fastpath *fp = &bp->fp[i];
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		mask = 0x2 << fp->sb_id;
		if (status & mask) {
			/* Handle Rx or Tx according to SB id */
			if (fp->is_rx_queue) {
				prefetch(fp->rx_cons_sb);
				prefetch(&fp->status_blk->u_status_block.
							status_block_index);
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				napi_schedule(&bnx2x_fp(bp, fp->index, napi));
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			} else {
				prefetch(fp->tx_cons_sb);
				prefetch(&fp->status_blk->c_status_block.
							status_block_index);

				bnx2x_update_fpsb_idx(fp);
				rmb();
				bnx2x_tx_int(fp);

				/* Re-enable interrupts */
				bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
					     le16_to_cpu(fp->fp_u_idx),
					     IGU_INT_NOP, 1);
				bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
					     le16_to_cpu(fp->fp_c_idx),
					     IGU_INT_ENABLE, 1);
			}
			status &= ~mask;
		}
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	}


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	if (unlikely(status & 0x1)) {
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		queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
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		status &= ~0x1;
		if (!status)
			return IRQ_HANDLED;
	}

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	if (status)
		DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
		   status);
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	return IRQ_HANDLED;
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}

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/* end of fast path */
1800

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static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1802

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/* Link */

/*
 * General service functions
 */
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static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
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{
	u32 lock_status;
	u32 resource_bit = (1 << resource);
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	int func = BP_FUNC(bp);
	u32 hw_lock_control_reg;
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	int cnt;
1816

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	/* Validating that the resource is within range */
	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
		DP(NETIF_MSG_HW,
		   "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
		   resource, HW_LOCK_MAX_RESOURCE_VALUE);
		return -EINVAL;
	}
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	if (func <= 5) {
		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
	} else {
		hw_lock_control_reg =
				(MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
	}

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	/* Validating that the resource is not already taken */
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	lock_status = REG_RD(bp, hw_lock_control_reg);
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	if (lock_status & resource_bit) {
		DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
		   lock_status, resource_bit);
		return -EEXIST;
	}
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	/* Try for 5 second every 5ms */
	for (cnt = 0; cnt < 1000; cnt++) {
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		/* Try to acquire the lock */
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		REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
		lock_status = REG_RD(bp, hw_lock_control_reg);
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		if (lock_status & resource_bit)
			return 0;
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		msleep(5);
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	}
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	DP(NETIF_MSG_HW, "Timeout\n");
	return -EAGAIN;
}
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static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
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{
	u32 lock_status;
	u32 resource_bit = (1 << resource);
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	int func = BP_FUNC(bp);
	u32 hw_lock_control_reg;
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	/* Validating that the resource is within range */
	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
		DP(NETIF_MSG_HW,
		   "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
		   resource, HW_LOCK_MAX_RESOURCE_VALUE);
		return -EINVAL;
	}

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	if (func <= 5) {
		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
	} else {
		hw_lock_control_reg =
				(MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
	}

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	/* Validating that the resource is currently taken */
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	lock_status = REG_RD(bp, hw_lock_control_reg);
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	if (!(lock_status & resource_bit)) {
		DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
		   lock_status, resource_bit);
		return -EFAULT;
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	}

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	REG_WR(bp, hw_lock_control_reg, resource_bit);
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	return 0;
}

/* HW Lock for shared dual port PHYs */
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static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
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{
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	mutex_lock(&bp->port.phy_mutex);
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	if (bp->port.need_hw_lock)
		bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
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}
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static void bnx2x_release_phy_lock(struct bnx2x *bp)
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{
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	if (bp->port.need_hw_lock)
		bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
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	mutex_unlock(&bp->port.phy_mutex);
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}
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int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
{
	/* The GPIO should be swapped if swap register is set and active */
	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
	int gpio_shift = gpio_num +
			(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
	u32 gpio_mask = (1 << gpio_shift);
	u32 gpio_reg;
	int value;

	if (gpio_num > MISC_REGISTERS_GPIO_3) {
		BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
		return -EINVAL;
	}

	/* read GPIO value */
	gpio_reg = REG_RD(bp, MISC_REG_GPIO);

	/* get the requested pin value */
	if ((gpio_reg & gpio_mask) == gpio_mask)
		value = 1;
	else
		value = 0;

	DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);

	return value;
}

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int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
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{
	/* The GPIO should be swapped if swap register is set and active */
	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1939
			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
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	int gpio_shift = gpio_num +
			(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
	u32 gpio_mask = (1 << gpio_shift);
	u32 gpio_reg;
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	if (gpio_num > MISC_REGISTERS_GPIO_3) {
		BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
		return -EINVAL;
	}
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	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
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	/* read GPIO and mask except the float bits */
	gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
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	switch (mode) {
	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
		DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
		   gpio_num, gpio_shift);
		/* clear FLOAT and set CLR */
		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
		break;
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	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
		DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
		   gpio_num, gpio_shift);
		/* clear FLOAT and set SET */
		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
		break;
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	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
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		DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
		   gpio_num, gpio_shift);
		/* set FLOAT */
		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
		break;
1977

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	default:
		break;
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	}

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	REG_WR(bp, MISC_REG_GPIO, gpio_reg);
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	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1984

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	return 0;
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}

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int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
{
	/* The GPIO should be swapped if swap register is set and active */
	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
	int gpio_shift = gpio_num +
			(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
	u32 gpio_mask = (1 << gpio_shift);
	u32 gpio_reg;

	if (gpio_num > MISC_REGISTERS_GPIO_3) {
		BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
		return -EINVAL;
	}

	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
	/* read GPIO int */
	gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);

	switch (mode) {
	case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
		DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
				   "output low\n", gpio_num, gpio_shift);
		/* clear SET and set CLR */
		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
		break;

	case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
		DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
				   "output high\n", gpio_num, gpio_shift);
		/* clear CLR and set SET */
		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
		break;

	default:
		break;
	}

	REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);

	return 0;
}

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2034
static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2035
{
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	u32 spio_mask = (1 << spio_num);
	u32 spio_reg;
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	if ((spio_num < MISC_REGISTERS_SPIO_4) ||
	    (spio_num > MISC_REGISTERS_SPIO_7)) {
		BNX2X_ERR("Invalid SPIO %d\n", spio_num);
		return -EINVAL;
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	}

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	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
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	/* read SPIO and mask except the float bits */
	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2048

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	switch (mode) {
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	case MISC_REGISTERS_SPIO_OUTPUT_LOW:
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		DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
		/* clear FLOAT and set CLR */
		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
		break;
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	case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
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		DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
		/* clear FLOAT and set SET */
		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
		break;
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	case MISC_REGISTERS_SPIO_INPUT_HI_Z:
		DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
		/* set FLOAT */
		spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
		break;
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	default:
		break;
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	}

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	REG_WR(bp, MISC_REG_SPIO, spio_reg);
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	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
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	return 0;
}

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static void bnx2x_calc_fc_adv(struct bnx2x *bp)
2081
{
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	switch (bp->link_vars.ieee_fc &
		MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
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	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
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		bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
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					  ADVERTISED_Pause);
		break;
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	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
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		bp->port.advertising |= (ADVERTISED_Asym_Pause |
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					 ADVERTISED_Pause);
		break;
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	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
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		bp->port.advertising |= ADVERTISED_Asym_Pause;
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		break;
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	default:
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		bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
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					  ADVERTISED_Pause);
		break;
	}
}
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static void bnx2x_link_report(struct bnx2x *bp)
{
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	if (bp->state == BNX2X_STATE_DISABLED) {
		netif_carrier_off(bp->dev);
		printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
		return;
	}

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	if (bp->link_vars.link_up) {
		if (bp->state == BNX2X_STATE_OPEN)
			netif_carrier_on(bp->dev);
		printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
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		printk("%d Mbps ", bp->link_vars.line_speed);
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		if (bp->link_vars.duplex == DUPLEX_FULL)
			printk("full duplex");
		else
			printk("half duplex");
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		if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
			if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
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				printk(", receive ");
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				if (bp->link_vars.flow_ctrl &
				    BNX2X_FLOW_CTRL_TX)
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					printk("& transmit ");
			} else {
				printk(", transmit ");
			}
			printk("flow control ON");
		}
		printk("\n");
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	} else { /* link_down */
		netif_carrier_off(bp->dev);
		printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
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	}
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}

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static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
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{
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	if (!BP_NOMCP(bp)) {
		u8 rc;
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		/* Initialize link parameters structure variables */
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		/* It is recommended to turn off RX FC for jumbo frames
		   for better performance */
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		if (bp->dev->mtu > 5000)
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			bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
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		else
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			bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
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		bnx2x_acquire_phy_lock(bp);
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		if (load_mode == LOAD_DIAG)
			bp->link_params.loopback_mode = LOOPBACK_XGXS_10;

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		rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
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		bnx2x_release_phy_lock(bp);
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		bnx2x_calc_fc_adv(bp);

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		if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
			bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
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			bnx2x_link_report(bp);
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		}
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		return rc;
	}
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	BNX2X_ERR("Bootcode is missing - can not initialize link\n");
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	return -EINVAL;
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}

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static void bnx2x_link_set(struct bnx2x *bp)
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{
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	if (!BP_NOMCP(bp)) {
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		bnx2x_acquire_phy_lock(bp);
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		bnx2x_phy_init(&bp->link_params, &bp->link_vars);
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		bnx2x_release_phy_lock(bp);
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		bnx2x_calc_fc_adv(bp);
	} else
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		BNX2X_ERR("Bootcode is missing - can not set link\n");
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}
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static void bnx2x__link_reset(struct bnx2x *bp)
{
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	if (!BP_NOMCP(bp)) {
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		bnx2x_acquire_phy_lock(bp);
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		bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
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		bnx2x_release_phy_lock(bp);
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	} else
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		BNX2X_ERR("Bootcode is missing - can not reset link\n");
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}
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static u8 bnx2x_link_test(struct bnx2x *bp)
{
	u8 rc;
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	bnx2x_acquire_phy_lock(bp);
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	rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
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	bnx2x_release_phy_lock(bp);
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	return rc;
}
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static void bnx2x_init_port_minmax(struct bnx2x *bp)
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{
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	u32 r_param = bp->link_vars.line_speed / 8;
	u32 fair_periodic_timeout_usec;
	u32 t_fair;
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	memset(&(bp->cmng.rs_vars), 0,
	       sizeof(struct rate_shaping_vars_per_port));
	memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
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	/* 100 usec in SDM ticks = 25 since each tick is 4 usec */
	bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
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	/* this is the threshold below which no timer arming will occur
	   1.25 coefficient is for the threshold to be a little bigger
	   than the real time, to compensate for timer in-accuracy */
	bp->cmng.rs_vars.rs_threshold =
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				(RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;

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	/* resolution of fairness timer */
	fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
	/* for 10G it is 1000usec. for 1G it is 10000usec. */
	t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
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	/* this is the threshold below which we won't arm the timer anymore */
	bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
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	/* we multiply by 1e3/8 to get bytes/msec.
	   We don't want the credits to pass a credit
	   of the t_fair*FAIR_MEM (algorithm resolution) */
	bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
	/* since each tick is 4 usec */
	bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
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}

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/* Calculates the sum of vn_min_rates.
   It's needed for further normalizing of the min_rates.
   Returns:
     sum of vn_min_rates.
       or
     0 - if all the min_rates are 0.
     In the later case fainess algorithm should be deactivated.
     If not all min_rates are zero then those that are zeroes will be set to 1.
 */
static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
{
	int all_zero = 1;
	int port = BP_PORT(bp);
	int vn;

	bp->vn_weight_sum = 0;
	for (vn = VN_0; vn < E1HVN_MAX; vn++) {
		int func = 2*vn + port;
		u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
		u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
				   FUNC_MF_CFG_MIN_BW_SHIFT) * 100;

		/* Skip hidden vns */
		if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
			continue;

		/* If min rate is zero - set it to 1 */
		if (!vn_min_rate)
			vn_min_rate = DEF_MIN_RATE;
		else
			all_zero = 0;

		bp->vn_weight_sum += vn_min_rate;
	}

	/* ... only if all min rates are zeros - disable fairness */
	if (all_zero)
		bp->vn_weight_sum = 0;
}

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static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
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{
	struct rate_shaping_vars_per_vn m_rs_vn;
	struct fairness_vars_per_vn m_fair_vn;
	u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
	u16 vn_min_rate, vn_max_rate;
	int i;

	/* If function is hidden - set min and max to zeroes */
	if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
		vn_min_rate = 0;
		vn_max_rate = 0;

	} else {
		vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
				FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
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		/* If fairness is enabled (not all min rates are zeroes) and
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		   if current min rate is zero - set it to 1.
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		   This is a requirement of the algorithm. */
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		if (bp->vn_weight_sum && (vn_min_rate == 0))
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			vn_min_rate = DEF_MIN_RATE;
		vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
				FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
	}

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	DP(NETIF_MSG_IFUP,
	   "func %d: vn_min_rate=%d  vn_max_rate=%d  vn_weight_sum=%d\n",
	   func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
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	memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
	memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));

	/* global vn counter - maximal Mbps for this vn */
	m_rs_vn.vn_counter.rate = vn_max_rate;

	/* quota - number of bytes transmitted in this period */
	m_rs_vn.vn_counter.quota =
				(vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;

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	if (bp->vn_weight_sum) {
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		/* credit for each period of the fairness algorithm:
		   number of bytes in T_FAIR (the vn share the port rate).
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		   vn_weight_sum should not be larger than 10000, thus
		   T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
		   than zero */
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		m_fair_vn.vn_credit_delta =
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			max((u32)(vn_min_rate * (T_FAIR_COEF /
						 (8 * bp->vn_weight_sum))),
			    (u32)(bp->cmng.fair_vars.fair_threshold * 2));
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		DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
		   m_fair_vn.vn_credit_delta);
	}

	/* Store it to internal memory */
	for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
		REG_WR(bp, BAR_XSTRORM_INTMEM +
		       XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
		       ((u32 *)(&m_rs_vn))[i]);

	for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
		REG_WR(bp, BAR_XSTRORM_INTMEM +
		       XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
		       ((u32 *)(&m_fair_vn))[i]);
}

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/* This function is called upon link interrupt */
static void bnx2x_link_attn(struct bnx2x *bp)
{
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	/* Make sure that we are synced with the current statistics */
	bnx2x_stats_handle(bp, STATS_EVENT_STOP);

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	bnx2x_link_update(&bp->link_params, &bp->link_vars);
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	if (bp->link_vars.link_up) {

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		/* dropless flow control */
		if (CHIP_IS_E1H(bp)) {
			int port = BP_PORT(bp);
			u32 pause_enabled = 0;

			if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
				pause_enabled = 1;

			REG_WR(bp, BAR_USTRORM_INTMEM +
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			       USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
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			       pause_enabled);
		}

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		if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
			struct host_port_stats *pstats;

			pstats = bnx2x_sp(bp, port_stats);
			/* reset old bmac stats */
			memset(&(pstats->mac_stx[0]), 0,
			       sizeof(struct mac_stx));
		}
		if ((bp->state == BNX2X_STATE_OPEN) ||
		    (bp->state == BNX2X_STATE_DISABLED))
			bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
	}

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	/* indicate link status */
	bnx2x_link_report(bp);
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	if (IS_E1HMF(bp)) {
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		int port = BP_PORT(bp);
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		int func;
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		int vn;
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		for (vn = VN_0; vn < E1HVN_MAX; vn++) {
			if (vn == BP_E1HVN(bp))
				continue;

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			func = ((vn << 1) | port);
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			/* Set the attention towards other drivers
			   on the same port */
			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
			       (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
		}

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		if (bp->link_vars.link_up) {
			int i;

			/* Init rate shaping and fairness contexts */
			bnx2x_init_port_minmax(bp);
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			for (vn = VN_0; vn < E1HVN_MAX; vn++)
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				bnx2x_init_vn_minmax(bp, 2*vn + port);

			/* Store it to internal memory */
			for (i = 0;
			     i < sizeof(struct cmng_struct_per_port) / 4; i++)
				REG_WR(bp, BAR_XSTRORM_INTMEM +
				  XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
				       ((u32 *)(&bp->cmng))[i]);
		}
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	}
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}
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static void bnx2x__link_status_update(struct bnx2x *bp)
{
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	int func = BP_FUNC(bp);

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	if (bp->state != BNX2X_STATE_OPEN)
		return;
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	bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
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	if (bp->link_vars.link_up)
		bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
	else
		bnx2x_stats_handle(bp, STATS_EVENT_STOP);

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	bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
	bnx2x_calc_vn_weight_sum(bp);

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	/* indicate link status */
	bnx2x_link_report(bp);
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}

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static void bnx2x_pmf_update(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
	u32 val;

	bp->port.pmf = 1;
	DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);

	/* enable nig attention */
	val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
	REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
	REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
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	bnx2x_stats_handle(bp, STATS_EVENT_PMF);
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}

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/* end of Link */
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/* slow path */

/*
 * General service functions
 */

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/* send the MCP a request, block until there is a reply */
u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
{
	int func = BP_FUNC(bp);
	u32 seq = ++bp->fw_seq;
	u32 rc = 0;
	u32 cnt = 1;
	u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;

	SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
	DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));

	do {
		/* let the FW do it's magic ... */
		msleep(delay);

		rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);

		/* Give the FW up to 2 second (200*10ms) */
	} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));

	DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
	   cnt*delay, rc, seq);

	/* is this a reply to our command? */
	if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
		rc &= FW_MSG_CODE_MASK;
	else {
		/* FW BUG! */
		BNX2X_ERR("FW failed to respond!\n");
		bnx2x_fw_dump(bp);
		rc = 0;
	}

	return rc;
}

static void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set);
static void bnx2x_set_rx_mode(struct net_device *dev);

static void bnx2x_e1h_disable(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
	int i;

	bp->rx_mode = BNX2X_RX_MODE_NONE;
	bnx2x_set_storm_rx_mode(bp);

	netif_tx_disable(bp->dev);
	bp->dev->trans_start = jiffies;	/* prevent tx timeout */

	REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);

	bnx2x_set_mac_addr_e1h(bp, 0);

	for (i = 0; i < MC_HASH_SIZE; i++)
		REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);

	netif_carrier_off(bp->dev);
}

static void bnx2x_e1h_enable(struct bnx2x *bp)
{
	int port = BP_PORT(bp);

	REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);

	bnx2x_set_mac_addr_e1h(bp, 1);

	/* Tx queue should be only reenabled */
	netif_tx_wake_all_queues(bp->dev);

	/* Initialize the receive filter. */
	bnx2x_set_rx_mode(bp->dev);
}

static void bnx2x_update_min_max(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
	int vn, i;

	/* Init rate shaping and fairness contexts */
	bnx2x_init_port_minmax(bp);

	bnx2x_calc_vn_weight_sum(bp);

	for (vn = VN_0; vn < E1HVN_MAX; vn++)
		bnx2x_init_vn_minmax(bp, 2*vn + port);

	if (bp->port.pmf) {
		int func;

		/* Set the attention towards other drivers on the same port */
		for (vn = VN_0; vn < E1HVN_MAX; vn++) {
			if (vn == BP_E1HVN(bp))
				continue;

			func = ((vn << 1) | port);
			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
			       (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
		}

		/* Store it to internal memory */
		for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
			REG_WR(bp, BAR_XSTRORM_INTMEM +
			       XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
			       ((u32 *)(&bp->cmng))[i]);
	}
}

static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
{
	int func = BP_FUNC(bp);

	DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
	bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);

	if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {

		if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
			DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
			bp->state = BNX2X_STATE_DISABLED;

			bnx2x_e1h_disable(bp);
		} else {
			DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
			bp->state = BNX2X_STATE_OPEN;

			bnx2x_e1h_enable(bp);
		}
		dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
	}
	if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {

		bnx2x_update_min_max(bp);
		dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
	}

	/* Report results to MCP */
	if (dcc_event)
		bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE);
	else
		bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK);
}

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/* the slow path queue is odd since completions arrive on the fastpath ring */
static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
			 u32 data_hi, u32 data_lo, int common)
{
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	int func = BP_FUNC(bp);
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	DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
	   "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
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	   (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
	   (void *)bp->spq_prod_bd - (void *)bp->spq), command,
	   HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return -EIO;
#endif

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	spin_lock_bh(&bp->spq_lock);
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	if (!bp->spq_left) {
		BNX2X_ERR("BUG! SPQ ring full!\n");
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		spin_unlock_bh(&bp->spq_lock);
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		bnx2x_panic();
		return -EBUSY;
	}
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	/* CID needs port number to be encoded int it */
	bp->spq_prod_bd->hdr.conn_and_cmd_data =
			cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
				     HW_CID(bp, cid)));
	bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
	if (common)
		bp->spq_prod_bd->hdr.type |=
			cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));

	bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
	bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);

	bp->spq_left--;

	if (bp->spq_prod_bd == bp->spq_last_bd) {
		bp->spq_prod_bd = bp->spq;
		bp->spq_prod_idx = 0;
		DP(NETIF_MSG_TIMER, "end of spq\n");

	} else {
		bp->spq_prod_bd++;
		bp->spq_prod_idx++;
	}

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	/* Make sure that BD data is updated before writing the producer */
	wmb();

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	REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
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	       bp->spq_prod_idx);

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	mmiowb();

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	spin_unlock_bh(&bp->spq_lock);
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	return 0;
}

/* acquire split MCP access lock register */
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static int bnx2x_acquire_alr(struct bnx2x *bp)
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{
	u32 i, j, val;
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	int rc = 0;
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	might_sleep();
	i = 100;
	for (j = 0; j < i*10; j++) {
		val = (1UL << 31);
		REG_WR(bp, GRCBASE_MCP + 0x9c, val);
		val = REG_RD(bp, GRCBASE_MCP + 0x9c);
		if (val & (1L << 31))
			break;

		msleep(5);
	}
	if (!(val & (1L << 31))) {
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		BNX2X_ERR("Cannot acquire MCP access lock register\n");
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		rc = -EBUSY;
	}

	return rc;
}

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/* release split MCP access lock register */
static void bnx2x_release_alr(struct bnx2x *bp)
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{
	u32 val = 0;

	REG_WR(bp, GRCBASE_MCP + 0x9c, val);
}

static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
{
	struct host_def_status_block *def_sb = bp->def_status_blk;
	u16 rc = 0;

	barrier(); /* status block is written to by the chip */
	if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
		bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
		rc |= 1;
	}
	if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
		bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
		rc |= 2;
	}
	if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
		bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
		rc |= 4;
	}
	if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
		bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
		rc |= 8;
	}
	if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
		bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
		rc |= 16;
	}
	return rc;
}

/*
 * slow path service functions
 */

static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
{
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	int port = BP_PORT(bp);
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	u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
		       COMMAND_REG_ATTN_BITS_SET);
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	u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
			      MISC_REG_AEU_MASK_ATTN_FUNC_0;
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	u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
				       NIG_REG_MASK_INTERRUPT_PORT0;
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	u32 aeu_mask;
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	u32 nig_mask = 0;
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	if (bp->attn_state & asserted)
		BNX2X_ERR("IGU ERROR\n");

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	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
	aeu_mask = REG_RD(bp, aeu_addr);

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	DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
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	   aeu_mask, asserted);
	aeu_mask &= ~(asserted & 0xff);
	DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
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	REG_WR(bp, aeu_addr, aeu_mask);
	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
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	DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
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	bp->attn_state |= asserted;
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	DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
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	if (asserted & ATTN_HARD_WIRED_MASK) {
		if (asserted & ATTN_NIG_FOR_FUNC) {

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			bnx2x_acquire_phy_lock(bp);

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			/* save nig interrupt mask */
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			nig_mask = REG_RD(bp, nig_int_mask_addr);
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			REG_WR(bp, nig_int_mask_addr, 0);
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			bnx2x_link_attn(bp);
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			/* handle unicore attn? */
		}
		if (asserted & ATTN_SW_TIMER_4_FUNC)
			DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");

		if (asserted & GPIO_2_FUNC)
			DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");

		if (asserted & GPIO_3_FUNC)
			DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");

		if (asserted & GPIO_4_FUNC)
			DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");

		if (port == 0) {
			if (asserted & ATTN_GENERAL_ATTN_1) {
				DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
				REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
			}
			if (asserted & ATTN_GENERAL_ATTN_2) {
				DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
				REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
			}
			if (asserted & ATTN_GENERAL_ATTN_3) {
				DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
				REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
			}
		} else {
			if (asserted & ATTN_GENERAL_ATTN_4) {
				DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
				REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
			}
			if (asserted & ATTN_GENERAL_ATTN_5) {
				DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
				REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
			}
			if (asserted & ATTN_GENERAL_ATTN_6) {
				DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
				REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
			}
		}

	} /* if hardwired */

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	DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
	   asserted, hc_addr);
	REG_WR(bp, hc_addr, asserted);
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	/* now set back the mask */
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	if (asserted & ATTN_NIG_FOR_FUNC) {
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		REG_WR(bp, nig_int_mask_addr, nig_mask);
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		bnx2x_release_phy_lock(bp);
	}
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}

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static inline void bnx2x_fan_failure(struct bnx2x *bp)
{
	int port = BP_PORT(bp);

	/* mark the failure */
	bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
	bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
	SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
		 bp->link_params.ext_phy_config);

	/* log the failure */
	printk(KERN_ERR PFX "Fan Failure on Network Controller %s has caused"
	       " the driver to shutdown the card to prevent permanent"
	       " damage.  Please contact Dell Support for assistance\n",
	       bp->dev->name);
}
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static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
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{
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	int port = BP_PORT(bp);
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	int reg_offset;
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	u32 val, swap_val, swap_override;
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	reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
			     MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
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	if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
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		val = REG_RD(bp, reg_offset);
		val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
		REG_WR(bp, reg_offset, val);

		BNX2X_ERR("SPIO5 hw attention\n");

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		/* Fan failure attention */
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		switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
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			/* Low power mode is controlled by GPIO 2 */
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			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
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				       MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
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			/* The PHY reset is controlled by GPIO 1 */
			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
				       MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
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			break;

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		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
			/* The PHY reset is controlled by GPIO 1 */
			/* fake the port number to cancel the swap done in
			   set_gpio() */
			swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
			swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
			port = (swap_val && swap_override) ^ 1;
			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
				       MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
			break;

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		default:
			break;
		}
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		bnx2x_fan_failure(bp);
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	}
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	if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
		    AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
		bnx2x_acquire_phy_lock(bp);
		bnx2x_handle_module_detect_int(&bp->link_params);
		bnx2x_release_phy_lock(bp);
	}

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	if (attn & HW_INTERRUT_ASSERT_SET_0) {

		val = REG_RD(bp, reg_offset);
		val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
		REG_WR(bp, reg_offset, val);

		BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
			  (attn & HW_INTERRUT_ASSERT_SET_0));
		bnx2x_panic();
	}
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}

static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
{
	u32 val;

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	if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
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		val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
		BNX2X_ERR("DB hw attention 0x%x\n", val);
		/* DORQ discard attention */
		if (val & 0x2)
			BNX2X_ERR("FATAL error from DORQ\n");
	}
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	if (attn & HW_INTERRUT_ASSERT_SET_1) {

		int port = BP_PORT(bp);
		int reg_offset;

		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
				     MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);

		val = REG_RD(bp, reg_offset);
		val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
		REG_WR(bp, reg_offset, val);

		BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
			  (attn & HW_INTERRUT_ASSERT_SET_1));
		bnx2x_panic();
	}
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}

static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
{
	u32 val;

	if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {

		val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
		BNX2X_ERR("CFC hw attention 0x%x\n", val);
		/* CFC error attention */
		if (val & 0x2)
			BNX2X_ERR("FATAL error from CFC\n");
	}

	if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {

		val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
		BNX2X_ERR("PXP hw attention 0x%x\n", val);
		/* RQ_USDMDP_FIFO_OVERFLOW */
		if (val & 0x18000)
			BNX2X_ERR("FATAL error from PXP\n");
	}
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	if (attn & HW_INTERRUT_ASSERT_SET_2) {

		int port = BP_PORT(bp);
		int reg_offset;

		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
				     MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);

		val = REG_RD(bp, reg_offset);
		val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
		REG_WR(bp, reg_offset, val);

		BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
			  (attn & HW_INTERRUT_ASSERT_SET_2));
		bnx2x_panic();
	}
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}

static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
{
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	u32 val;

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	if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {

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		if (attn & BNX2X_PMF_LINK_ASSERT) {
			int func = BP_FUNC(bp);

			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
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			val = SHMEM_RD(bp, func_mb[func].drv_status);
			if (val & DRV_STATUS_DCC_EVENT_MASK)
				bnx2x_dcc_event(bp,
					    (val & DRV_STATUS_DCC_EVENT_MASK));
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			bnx2x__link_status_update(bp);
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			if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
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				bnx2x_pmf_update(bp);

		} else if (attn & BNX2X_MC_ASSERT_BITS) {
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			BNX2X_ERR("MC assert!\n");
			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
			bnx2x_panic();

		} else if (attn & BNX2X_MCP_ASSERT) {

			BNX2X_ERR("MCP assert!\n");
			REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
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			bnx2x_fw_dump(bp);
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		} else
			BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
	}

	if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
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		BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
		if (attn & BNX2X_GRC_TIMEOUT) {
			val = CHIP_IS_E1H(bp) ?
				REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
			BNX2X_ERR("GRC time-out 0x%08x\n", val);
		}
		if (attn & BNX2X_GRC_RSV) {
			val = CHIP_IS_E1H(bp) ?
				REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
			BNX2X_ERR("GRC reserved 0x%08x\n", val);
		}
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		REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
	}
}

static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
{
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	struct attn_route attn;
	struct attn_route group_mask;
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	int port = BP_PORT(bp);
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	int index;
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	u32 reg_addr;
	u32 val;
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	u32 aeu_mask;
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	/* need to take HW lock because MCP or other port might also
	   try to handle this event */
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	bnx2x_acquire_alr(bp);
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	attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
	attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
	attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
	attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
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	DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
	   attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
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	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
		if (deasserted & (1 << index)) {
			group_mask = bp->attn_group[index];

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			DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
			   index, group_mask.sig[0], group_mask.sig[1],
			   group_mask.sig[2], group_mask.sig[3]);
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			bnx2x_attn_int_deasserted3(bp,
					attn.sig[3] & group_mask.sig[3]);
			bnx2x_attn_int_deasserted1(bp,
					attn.sig[1] & group_mask.sig[1]);
			bnx2x_attn_int_deasserted2(bp,
					attn.sig[2] & group_mask.sig[2]);
			bnx2x_attn_int_deasserted0(bp,
					attn.sig[0] & group_mask.sig[0]);
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			if ((attn.sig[0] & group_mask.sig[0] &
						HW_PRTY_ASSERT_SET_0) ||
			    (attn.sig[1] & group_mask.sig[1] &
						HW_PRTY_ASSERT_SET_1) ||
			    (attn.sig[2] & group_mask.sig[2] &
						HW_PRTY_ASSERT_SET_2))
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				BNX2X_ERR("FATAL HW block parity attention\n");
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		}
	}

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	bnx2x_release_alr(bp);
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	reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
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	val = ~deasserted;
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	DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
	   val, reg_addr);
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	REG_WR(bp, reg_addr, val);
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	if (~bp->attn_state & deasserted)
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		BNX2X_ERR("IGU ERROR\n");
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	reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
			  MISC_REG_AEU_MASK_ATTN_FUNC_0;

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	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
	aeu_mask = REG_RD(bp, reg_addr);

	DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
	   aeu_mask, deasserted);
	aeu_mask |= (deasserted & 0xff);
	DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
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	REG_WR(bp, reg_addr, aeu_mask);
	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
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	DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
	bp->attn_state &= ~deasserted;
	DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
}

static void bnx2x_attn_int(struct bnx2x *bp)
{
	/* read local copy of bits */
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	u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
								attn_bits);
	u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
								attn_bits_ack);
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	u32 attn_state = bp->attn_state;

	/* look for changed bits */
	u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
	u32 deasserted = ~attn_bits &  attn_ack &  attn_state;

	DP(NETIF_MSG_HW,
	   "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
	   attn_bits, attn_ack, asserted, deasserted);

	if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
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		BNX2X_ERR("BAD attention state\n");
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	/* handle bits that were raised */
	if (asserted)
		bnx2x_attn_int_asserted(bp, asserted);

	if (deasserted)
		bnx2x_attn_int_deasserted(bp, deasserted);
}

static void bnx2x_sp_task(struct work_struct *work)
{
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	struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
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	u16 status;

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	/* Return here if interrupt is disabled */
	if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
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		DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
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		return;
	}

	status = bnx2x_update_dsb_idx(bp);
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/*	if (status == 0)				     */
/*		BNX2X_ERR("spurious slowpath interrupt!\n"); */
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	DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
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	/* HW attentions */
	if (status & 0x1)
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		bnx2x_attn_int(bp);

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	bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
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		     IGU_INT_NOP, 1);
	bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
		     IGU_INT_NOP, 1);
	bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
		     IGU_INT_NOP, 1);
	bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
		     IGU_INT_NOP, 1);
	bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
		     IGU_INT_ENABLE, 1);
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}

static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
{
	struct net_device *dev = dev_instance;
	struct bnx2x *bp = netdev_priv(dev);

	/* Return here if interrupt is disabled */
	if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
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		DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
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		return IRQ_HANDLED;
	}

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	bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
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#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return IRQ_HANDLED;
#endif

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	queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
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	return IRQ_HANDLED;
}

/* end of slow path */

/* Statistics */

/****************************************************************************
* Macros
****************************************************************************/

/* sum[hi:lo] += add[hi:lo] */
#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
	do { \
		s_lo += a_lo; \
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		s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
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	} while (0)

/* difference = minuend - subtrahend */
#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
	do { \
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		if (m_lo < s_lo) { \
			/* underflow */ \
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			d_hi = m_hi - s_hi; \
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			if (d_hi > 0) { \
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				/* we can 'loan' 1 */ \
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				d_hi--; \
				d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
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			} else { \
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				/* m_hi <= s_hi */ \
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				d_hi = 0; \
				d_lo = 0; \
			} \
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		} else { \
			/* m_lo >= s_lo */ \
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			if (m_hi < s_hi) { \
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				d_hi = 0; \
				d_lo = 0; \
			} else { \
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				/* m_hi >= s_hi */ \
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				d_hi = m_hi - s_hi; \
				d_lo = m_lo - s_lo; \
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			} \
		} \
	} while (0)

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#define UPDATE_STAT64(s, t) \
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	do { \
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		DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
			diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
		pstats->mac_stx[0].t##_hi = new->s##_hi; \
		pstats->mac_stx[0].t##_lo = new->s##_lo; \
		ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
		       pstats->mac_stx[1].t##_lo, diff.lo); \
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	} while (0)

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#define UPDATE_STAT64_NIG(s, t) \
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	do { \
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		DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
			diff.lo, new->s##_lo, old->s##_lo); \
		ADD_64(estats->t##_hi, diff.hi, \
		       estats->t##_lo, diff.lo); \
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	} while (0)

/* sum[hi:lo] += add */
#define ADD_EXTEND_64(s_hi, s_lo, a) \
	do { \
		s_lo += a; \
		s_hi += (s_lo < a) ? 1 : 0; \
	} while (0)

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#define UPDATE_EXTEND_STAT(s) \
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	do { \
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		ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
			      pstats->mac_stx[1].s##_lo, \
			      new->s); \
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	} while (0)

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#define UPDATE_EXTEND_TSTAT(s, t) \
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	do { \
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		diff = le32_to_cpu(tclient->s) - le32_to_cpu(old_tclient->s); \
		old_tclient->s = tclient->s; \
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		ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
	} while (0)

#define UPDATE_EXTEND_USTAT(s, t) \
	do { \
		diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
		old_uclient->s = uclient->s; \
		ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
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	} while (0)

#define UPDATE_EXTEND_XSTAT(s, t) \
	do { \
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		diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \
		old_xclient->s = xclient->s; \
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		ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
	} while (0)

/* minuend -= subtrahend */
#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
	do { \
		DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
	} while (0)

/* minuend[hi:lo] -= subtrahend */
#define SUB_EXTEND_64(m_hi, m_lo, s) \
	do { \
		SUB_64(m_hi, 0, m_lo, s); \
	} while (0)

#define SUB_EXTEND_USTAT(s, t) \
	do { \
		diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
		SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
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	} while (0)

/*
 * General service functions
 */

static inline long bnx2x_hilo(u32 *hiref)
{
	u32 lo = *(hiref + 1);
#if (BITS_PER_LONG == 64)
	u32 hi = *hiref;

	return HILO_U64(hi, lo);
#else
	return lo;
#endif
}

/*
 * Init service functions
 */

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static void bnx2x_storm_stats_post(struct bnx2x *bp)
{
	if (!bp->stats_pending) {
		struct eth_query_ramrod_data ramrod_data = {0};
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		int i, rc;
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		ramrod_data.drv_counter = bp->stats_counter++;
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		ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
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		for_each_queue(bp, i)
			ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
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		rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
				   ((u32 *)&ramrod_data)[1],
				   ((u32 *)&ramrod_data)[0], 0);
		if (rc == 0) {
			/* stats ramrod has it's own slot on the spq */
			bp->spq_left++;
			bp->stats_pending = 1;
		}
	}
}

static void bnx2x_stats_init(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
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	int i;
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	bp->stats_pending = 0;
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	bp->executer_idx = 0;
	bp->stats_counter = 0;

	/* port stats */
	if (!BP_NOMCP(bp))
		bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
	else
		bp->port.port_stx = 0;
	DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);

	memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
	bp->port.old_nig_stats.brb_discard =
			REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
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	bp->port.old_nig_stats.brb_truncate =
			REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
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	REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
		    &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
	REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
		    &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);

	/* function stats */
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	for_each_queue(bp, i) {
		struct bnx2x_fastpath *fp = &bp->fp[i];

		memset(&fp->old_tclient, 0,
		       sizeof(struct tstorm_per_client_stats));
		memset(&fp->old_uclient, 0,
		       sizeof(struct ustorm_per_client_stats));
		memset(&fp->old_xclient, 0,
		       sizeof(struct xstorm_per_client_stats));
		memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
	}

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	memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
	memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));

	bp->stats_state = STATS_STATE_DISABLED;
	if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
		bnx2x_stats_handle(bp, STATS_EVENT_PMF);
}

static void bnx2x_hw_stats_post(struct bnx2x *bp)
{
	struct dmae_command *dmae = &bp->stats_dmae;
	u32 *stats_comp = bnx2x_sp(bp, stats_comp);

	*stats_comp = DMAE_COMP_VAL;
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	if (CHIP_REV_IS_SLOW(bp))
		return;
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	/* loader */
	if (bp->executer_idx) {
		int loader_idx = PMF_DMAE_C(bp);

		memset(dmae, 0, sizeof(struct dmae_command));

		dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
				DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
				DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
				DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
				DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
				(BP_PORT(bp) ? DMAE_CMD_PORT_1 :
					       DMAE_CMD_PORT_0) |
				(BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
		dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
		dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
		dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
				     sizeof(struct dmae_command) *
				     (loader_idx + 1)) >> 2;
		dmae->dst_addr_hi = 0;
		dmae->len = sizeof(struct dmae_command) >> 2;
		if (CHIP_IS_E1(bp))
			dmae->len--;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;

		*stats_comp = 0;
		bnx2x_post_dmae(bp, dmae, loader_idx);

	} else if (bp->func_stx) {
		*stats_comp = 0;
		bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
	}
}

static int bnx2x_stats_comp(struct bnx2x *bp)
{
	u32 *stats_comp = bnx2x_sp(bp, stats_comp);
	int cnt = 10;

	might_sleep();
	while (*stats_comp != DMAE_COMP_VAL) {
		if (!cnt) {
			BNX2X_ERR("timeout waiting for stats finished\n");
			break;
		}
		cnt--;
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		msleep(1);
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	}
	return 1;
}

/*
 * Statistics service functions
 */

static void bnx2x_stats_pmf_update(struct bnx2x *bp)
{
	struct dmae_command *dmae;
	u32 opcode;
	int loader_idx = PMF_DMAE_C(bp);
	u32 *stats_comp = bnx2x_sp(bp, stats_comp);

	/* sanity */
	if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
		BNX2X_ERR("BUG!\n");
		return;
	}

	bp->executer_idx = 0;

	opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
		  DMAE_CMD_C_ENABLE |
		  DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
		  DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
		  DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
		  (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
		  (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));

	dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
	dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
	dmae->src_addr_lo = bp->port.port_stx >> 2;
	dmae->src_addr_hi = 0;
	dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
	dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
	dmae->len = DMAE_LEN32_RD_MAX;
	dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
	dmae->comp_addr_hi = 0;
	dmae->comp_val = 1;

	dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
	dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
	dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
	dmae->src_addr_hi = 0;
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	dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
				   DMAE_LEN32_RD_MAX * 4);
	dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
				   DMAE_LEN32_RD_MAX * 4);
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	dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
	dmae->comp_val = DMAE_COMP_VAL;

	*stats_comp = 0;
	bnx2x_hw_stats_post(bp);
	bnx2x_stats_comp(bp);
}

static void bnx2x_port_stats_init(struct bnx2x *bp)
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{
	struct dmae_command *dmae;
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	int port = BP_PORT(bp);
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	int vn = BP_E1HVN(bp);
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	u32 opcode;
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	int loader_idx = PMF_DMAE_C(bp);
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	u32 mac_addr;
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	u32 *stats_comp = bnx2x_sp(bp, stats_comp);

	/* sanity */
	if (!bp->link_vars.link_up || !bp->port.pmf) {
		BNX2X_ERR("BUG!\n");
		return;
	}
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	bp->executer_idx = 0;
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	/* MCP */
	opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
		  DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
		  DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
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#ifdef __BIG_ENDIAN
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		  DMAE_CMD_ENDIANITY_B_DW_SWAP |
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#else
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		  DMAE_CMD_ENDIANITY_DW_SWAP |
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#endif
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		  (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
		  (vn << DMAE_CMD_E1HVN_SHIFT));
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	if (bp->port.port_stx) {
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		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = opcode;
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		dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
		dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
		dmae->dst_addr_lo = bp->port.port_stx >> 2;
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		dmae->dst_addr_hi = 0;
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		dmae->len = sizeof(struct host_port_stats) >> 2;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;
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	}

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	if (bp->func_stx) {

		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = opcode;
		dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
		dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
		dmae->dst_addr_lo = bp->func_stx >> 2;
		dmae->dst_addr_hi = 0;
		dmae->len = sizeof(struct host_func_stats) >> 2;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;
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	}

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	/* MAC */
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	opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
		  DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
		  DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
		  DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
		  DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
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		  (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
		  (vn << DMAE_CMD_E1HVN_SHIFT));
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	if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
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		mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
				   NIG_REG_INGRESS_BMAC0_MEM);

		/* BIGMAC_REGISTER_TX_STAT_GTPKT ..
		   BIGMAC_REGISTER_TX_STAT_GTBYT */
		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = opcode;
		dmae->src_addr_lo = (mac_addr +
				     BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
		dmae->src_addr_hi = 0;
		dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
		dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
		dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
			     BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;

		/* BIGMAC_REGISTER_RX_STAT_GR64 ..
		   BIGMAC_REGISTER_RX_STAT_GRIPJ */
		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = opcode;
		dmae->src_addr_lo = (mac_addr +
				     BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
		dmae->src_addr_hi = 0;
		dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
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				offsetof(struct bmac_stats, rx_stat_gr64_lo));
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		dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
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				offsetof(struct bmac_stats, rx_stat_gr64_lo));
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		dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
			     BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;

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	} else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
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		mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);

		/* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = opcode;
		dmae->src_addr_lo = (mac_addr +
				     EMAC_REG_EMAC_RX_STAT_AC) >> 2;
		dmae->src_addr_hi = 0;
		dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
		dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
		dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;

		/* EMAC_REG_EMAC_RX_STAT_AC_28 */
		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = opcode;
		dmae->src_addr_lo = (mac_addr +
				     EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
		dmae->src_addr_hi = 0;
		dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
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		     offsetof(struct emac_stats, rx_stat_falsecarriererrors));
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		dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
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		     offsetof(struct emac_stats, rx_stat_falsecarriererrors));
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		dmae->len = 1;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;

		/* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = opcode;
		dmae->src_addr_lo = (mac_addr +
				     EMAC_REG_EMAC_TX_STAT_AC) >> 2;
		dmae->src_addr_hi = 0;
		dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
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			offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
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		dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
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			offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
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		dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
		dmae->comp_addr_hi = 0;
		dmae->comp_val = 1;
	}

	/* NIG */
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	dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
	dmae->opcode = opcode;
	dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
				    NIG_REG_STAT0_BRB_DISCARD) >> 2;
	dmae->src_addr_hi = 0;
	dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
	dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
	dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
	dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
	dmae->comp_addr_hi = 0;
	dmae->comp_val = 1;

	dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
	dmae->opcode = opcode;
	dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
				    NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
	dmae->src_addr_hi = 0;
	dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
			offsetof(struct nig_stats, egress_mac_pkt0_lo));
	dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
			offsetof(struct nig_stats, egress_mac_pkt0_lo));
	dmae->len = (2*sizeof(u32)) >> 2;
	dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
	dmae->comp_addr_hi = 0;
	dmae->comp_val = 1;

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	dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
	dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
			DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
			DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
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			(port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
			(vn << DMAE_CMD_E1HVN_SHIFT));
	dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
				    NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
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	dmae->src_addr_hi = 0;
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	dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
			offsetof(struct nig_stats, egress_mac_pkt1_lo));
	dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
			offsetof(struct nig_stats, egress_mac_pkt1_lo));
	dmae->len = (2*sizeof(u32)) >> 2;
	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
	dmae->comp_val = DMAE_COMP_VAL;

	*stats_comp = 0;
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}

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static void bnx2x_func_stats_init(struct bnx2x *bp)
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{
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	struct dmae_command *dmae = &bp->stats_dmae;
	u32 *stats_comp = bnx2x_sp(bp, stats_comp);
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	/* sanity */
	if (!bp->func_stx) {
		BNX2X_ERR("BUG!\n");
		return;
	}
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	bp->executer_idx = 0;
	memset(dmae, 0, sizeof(struct dmae_command));
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	dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
			DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
			DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
			(BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
			(BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
	dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
	dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
	dmae->dst_addr_lo = bp->func_stx >> 2;
	dmae->dst_addr_hi = 0;
	dmae->len = sizeof(struct host_func_stats) >> 2;
	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
	dmae->comp_val = DMAE_COMP_VAL;
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	*stats_comp = 0;
}
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static void bnx2x_stats_start(struct bnx2x *bp)
{
	if (bp->port.pmf)
		bnx2x_port_stats_init(bp);

	else if (bp->func_stx)
		bnx2x_func_stats_init(bp);

	bnx2x_hw_stats_post(bp);
	bnx2x_storm_stats_post(bp);
}

static void bnx2x_stats_pmf_start(struct bnx2x *bp)
{
	bnx2x_stats_comp(bp);
	bnx2x_stats_pmf_update(bp);
	bnx2x_stats_start(bp);
}

static void bnx2x_stats_restart(struct bnx2x *bp)
{
	bnx2x_stats_comp(bp);
	bnx2x_stats_start(bp);
}

static void bnx2x_bmac_stats_update(struct bnx2x *bp)
{
	struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
	struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
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	struct bnx2x_eth_stats *estats = &bp->eth_stats;
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	struct {
		u32 lo;
		u32 hi;
	} diff;
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	UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
	UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
	UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
	UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
	UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
	UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
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	UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
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	UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
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	UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
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	UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
	UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
	UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
	UPDATE_STAT64(tx_stat_gt127,
				tx_stat_etherstatspkts65octetsto127octets);
	UPDATE_STAT64(tx_stat_gt255,
				tx_stat_etherstatspkts128octetsto255octets);
	UPDATE_STAT64(tx_stat_gt511,
				tx_stat_etherstatspkts256octetsto511octets);
	UPDATE_STAT64(tx_stat_gt1023,
				tx_stat_etherstatspkts512octetsto1023octets);
	UPDATE_STAT64(tx_stat_gt1518,
				tx_stat_etherstatspkts1024octetsto1522octets);
	UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
	UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
	UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
	UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
	UPDATE_STAT64(tx_stat_gterr,
				tx_stat_dot3statsinternalmactransmiterrors);
	UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
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	estats->pause_frames_received_hi =
				pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
	estats->pause_frames_received_lo =
				pstats->mac_stx[1].rx_stat_bmac_xpf_lo;

	estats->pause_frames_sent_hi =
				pstats->mac_stx[1].tx_stat_outxoffsent_hi;
	estats->pause_frames_sent_lo =
				pstats->mac_stx[1].tx_stat_outxoffsent_lo;
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}

static void bnx2x_emac_stats_update(struct bnx2x *bp)
{
	struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
	struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
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	struct bnx2x_eth_stats *estats = &bp->eth_stats;
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	UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
	UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
	UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
	UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
	UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
	UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
	UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
	UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
	UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
	UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
	UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
	UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
	UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
	UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
	UPDATE_EXTEND_STAT(tx_stat_outxonsent);
	UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
	UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
	UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
	UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
	UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
	UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
	UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
	UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
	UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
	UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
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	estats->pause_frames_received_hi =
			pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
	estats->pause_frames_received_lo =
			pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
	ADD_64(estats->pause_frames_received_hi,
	       pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
	       estats->pause_frames_received_lo,
	       pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);

	estats->pause_frames_sent_hi =
			pstats->mac_stx[1].tx_stat_outxonsent_hi;
	estats->pause_frames_sent_lo =
			pstats->mac_stx[1].tx_stat_outxonsent_lo;
	ADD_64(estats->pause_frames_sent_hi,
	       pstats->mac_stx[1].tx_stat_outxoffsent_hi,
	       estats->pause_frames_sent_lo,
	       pstats->mac_stx[1].tx_stat_outxoffsent_lo);
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}

static int bnx2x_hw_stats_update(struct bnx2x *bp)
{
	struct nig_stats *new = bnx2x_sp(bp, nig_stats);
	struct nig_stats *old = &(bp->port.old_nig_stats);
	struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
	struct bnx2x_eth_stats *estats = &bp->eth_stats;
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	struct {
		u32 lo;
		u32 hi;
	} diff;
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	u32 nig_timer_max;
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	if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
		bnx2x_bmac_stats_update(bp);

	else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
		bnx2x_emac_stats_update(bp);

	else { /* unreached */
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		BNX2X_ERR("stats updated by DMAE but no MAC active\n");
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		return -1;
	}
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	ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
		      new->brb_discard - old->brb_discard);
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	ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
		      new->brb_truncate - old->brb_truncate);
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	UPDATE_STAT64_NIG(egress_mac_pkt0,
					etherstatspkts1024octetsto1522octets);
	UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
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	memcpy(old, new, sizeof(struct nig_stats));
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	memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
	       sizeof(struct mac_stx));
	estats->brb_drop_hi = pstats->brb_drop_hi;
	estats->brb_drop_lo = pstats->brb_drop_lo;
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	pstats->host_port_stats_start = ++pstats->host_port_stats_end;
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	nig_timer_max = SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
	if (nig_timer_max != estats->nig_timer_max) {
		estats->nig_timer_max = nig_timer_max;
		BNX2X_ERR("NIG timer max (%u)\n", estats->nig_timer_max);
	}

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	return 0;
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}

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static int bnx2x_storm_stats_update(struct bnx2x *bp)
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{
	struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
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	struct tstorm_per_port_stats *tport =
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					&stats->tstorm_common.port_statistics;
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	struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
	struct bnx2x_eth_stats *estats = &bp->eth_stats;
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	int i;

	memset(&(fstats->total_bytes_received_hi), 0,
	       sizeof(struct host_func_stats) - 2*sizeof(u32));
	estats->error_bytes_received_hi = 0;
	estats->error_bytes_received_lo = 0;
	estats->etherstatsoverrsizepkts_hi = 0;
	estats->etherstatsoverrsizepkts_lo = 0;
	estats->no_buff_discard_hi = 0;
	estats->no_buff_discard_lo = 0;
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	for_each_rx_queue(bp, i) {
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		struct bnx2x_fastpath *fp = &bp->fp[i];
		int cl_id = fp->cl_id;
		struct tstorm_per_client_stats *tclient =
				&stats->tstorm_common.client_statistics[cl_id];
		struct tstorm_per_client_stats *old_tclient = &fp->old_tclient;
		struct ustorm_per_client_stats *uclient =
				&stats->ustorm_common.client_statistics[cl_id];
		struct ustorm_per_client_stats *old_uclient = &fp->old_uclient;
		struct xstorm_per_client_stats *xclient =
				&stats->xstorm_common.client_statistics[cl_id];
		struct xstorm_per_client_stats *old_xclient = &fp->old_xclient;
		struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
		u32 diff;

		/* are storm stats valid? */
		if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
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							bp->stats_counter) {
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			DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
			   "  xstorm counter (%d) != stats_counter (%d)\n",
			   i, xclient->stats_counter, bp->stats_counter);
			return -1;
		}
		if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
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							bp->stats_counter) {
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			DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
			   "  tstorm counter (%d) != stats_counter (%d)\n",
			   i, tclient->stats_counter, bp->stats_counter);
			return -2;
		}
		if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) !=
							bp->stats_counter) {
			DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
			   "  ustorm counter (%d) != stats_counter (%d)\n",
			   i, uclient->stats_counter, bp->stats_counter);
			return -4;
		}
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		qstats->total_bytes_received_hi =
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			le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
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		qstats->total_bytes_received_lo =
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			le32_to_cpu(tclient->rcv_broadcast_bytes.lo);

		ADD_64(qstats->total_bytes_received_hi,
		       le32_to_cpu(tclient->rcv_multicast_bytes.hi),
		       qstats->total_bytes_received_lo,
		       le32_to_cpu(tclient->rcv_multicast_bytes.lo));

		ADD_64(qstats->total_bytes_received_hi,
		       le32_to_cpu(tclient->rcv_unicast_bytes.hi),
		       qstats->total_bytes_received_lo,
		       le32_to_cpu(tclient->rcv_unicast_bytes.lo));

		qstats->valid_bytes_received_hi =
					qstats->total_bytes_received_hi;
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		qstats->valid_bytes_received_lo =
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					qstats->total_bytes_received_lo;
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		qstats->error_bytes_received_hi =
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				le32_to_cpu(tclient->rcv_error_bytes.hi);
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		qstats->error_bytes_received_lo =
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				le32_to_cpu(tclient->rcv_error_bytes.lo);

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		ADD_64(qstats->total_bytes_received_hi,
		       qstats->error_bytes_received_hi,
		       qstats->total_bytes_received_lo,
		       qstats->error_bytes_received_lo);

		UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
					total_unicast_packets_received);
		UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
					total_multicast_packets_received);
		UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
					total_broadcast_packets_received);
		UPDATE_EXTEND_TSTAT(packets_too_big_discard,
					etherstatsoverrsizepkts);
		UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);

		SUB_EXTEND_USTAT(ucast_no_buff_pkts,
					total_unicast_packets_received);
		SUB_EXTEND_USTAT(mcast_no_buff_pkts,
					total_multicast_packets_received);
		SUB_EXTEND_USTAT(bcast_no_buff_pkts,
					total_broadcast_packets_received);
		UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
		UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
		UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);

		qstats->total_bytes_transmitted_hi =
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				le32_to_cpu(xclient->unicast_bytes_sent.hi);
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		qstats->total_bytes_transmitted_lo =
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				le32_to_cpu(xclient->unicast_bytes_sent.lo);

		ADD_64(qstats->total_bytes_transmitted_hi,
		       le32_to_cpu(xclient->multicast_bytes_sent.hi),
		       qstats->total_bytes_transmitted_lo,
		       le32_to_cpu(xclient->multicast_bytes_sent.lo));

		ADD_64(qstats->total_bytes_transmitted_hi,
		       le32_to_cpu(xclient->broadcast_bytes_sent.hi),
		       qstats->total_bytes_transmitted_lo,
		       le32_to_cpu(xclient->broadcast_bytes_sent.lo));
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		UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
					total_unicast_packets_transmitted);
		UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
					total_multicast_packets_transmitted);
		UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
					total_broadcast_packets_transmitted);

		old_tclient->checksum_discard = tclient->checksum_discard;
		old_tclient->ttl0_discard = tclient->ttl0_discard;

		ADD_64(fstats->total_bytes_received_hi,
		       qstats->total_bytes_received_hi,
		       fstats->total_bytes_received_lo,
		       qstats->total_bytes_received_lo);
		ADD_64(fstats->total_bytes_transmitted_hi,
		       qstats->total_bytes_transmitted_hi,
		       fstats->total_bytes_transmitted_lo,
		       qstats->total_bytes_transmitted_lo);
		ADD_64(fstats->total_unicast_packets_received_hi,
		       qstats->total_unicast_packets_received_hi,
		       fstats->total_unicast_packets_received_lo,
		       qstats->total_unicast_packets_received_lo);
		ADD_64(fstats->total_multicast_packets_received_hi,
		       qstats->total_multicast_packets_received_hi,
		       fstats->total_multicast_packets_received_lo,
		       qstats->total_multicast_packets_received_lo);
		ADD_64(fstats->total_broadcast_packets_received_hi,
		       qstats->total_broadcast_packets_received_hi,
		       fstats->total_broadcast_packets_received_lo,
		       qstats->total_broadcast_packets_received_lo);
		ADD_64(fstats->total_unicast_packets_transmitted_hi,
		       qstats->total_unicast_packets_transmitted_hi,
		       fstats->total_unicast_packets_transmitted_lo,
		       qstats->total_unicast_packets_transmitted_lo);
		ADD_64(fstats->total_multicast_packets_transmitted_hi,
		       qstats->total_multicast_packets_transmitted_hi,
		       fstats->total_multicast_packets_transmitted_lo,
		       qstats->total_multicast_packets_transmitted_lo);
		ADD_64(fstats->total_broadcast_packets_transmitted_hi,
		       qstats->total_broadcast_packets_transmitted_hi,
		       fstats->total_broadcast_packets_transmitted_lo,
		       qstats->total_broadcast_packets_transmitted_lo);
		ADD_64(fstats->valid_bytes_received_hi,
		       qstats->valid_bytes_received_hi,
		       fstats->valid_bytes_received_lo,
		       qstats->valid_bytes_received_lo);

		ADD_64(estats->error_bytes_received_hi,
		       qstats->error_bytes_received_hi,
		       estats->error_bytes_received_lo,
		       qstats->error_bytes_received_lo);
		ADD_64(estats->etherstatsoverrsizepkts_hi,
		       qstats->etherstatsoverrsizepkts_hi,
		       estats->etherstatsoverrsizepkts_lo,
		       qstats->etherstatsoverrsizepkts_lo);
		ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
		       estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
	}

	ADD_64(fstats->total_bytes_received_hi,
	       estats->rx_stat_ifhcinbadoctets_hi,
	       fstats->total_bytes_received_lo,
	       estats->rx_stat_ifhcinbadoctets_lo);
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	memcpy(estats, &(fstats->total_bytes_received_hi),
	       sizeof(struct host_func_stats) - 2*sizeof(u32));

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	ADD_64(estats->etherstatsoverrsizepkts_hi,
	       estats->rx_stat_dot3statsframestoolong_hi,
	       estats->etherstatsoverrsizepkts_lo,
	       estats->rx_stat_dot3statsframestoolong_lo);
	ADD_64(estats->error_bytes_received_hi,
	       estats->rx_stat_ifhcinbadoctets_hi,
	       estats->error_bytes_received_lo,
	       estats->rx_stat_ifhcinbadoctets_lo);

	if (bp->port.pmf) {
		estats->mac_filter_discard =
				le32_to_cpu(tport->mac_filter_discard);
		estats->xxoverflow_discard =
				le32_to_cpu(tport->xxoverflow_discard);
		estats->brb_truncate_discard =
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				le32_to_cpu(tport->brb_truncate_discard);
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		estats->mac_discard = le32_to_cpu(tport->mac_discard);
	}
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	fstats->host_func_stats_start = ++fstats->host_func_stats_end;
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	bp->stats_pending = 0;

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	return 0;
}

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static void bnx2x_net_stats_update(struct bnx2x *bp)
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{
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	struct bnx2x_eth_stats *estats = &bp->eth_stats;
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	struct net_device_stats *nstats = &bp->dev->stats;
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	int i;
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	nstats->rx_packets =
		bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
		bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
		bnx2x_hilo(&estats->total_broadcast_packets_received_hi);

	nstats->tx_packets =
		bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
		bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
		bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);

4196
	nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
4197

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	nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
4199

4200
	nstats->rx_dropped = estats->mac_discard;
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	for_each_rx_queue(bp, i)
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		nstats->rx_dropped +=
			le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);

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	nstats->tx_dropped = 0;

	nstats->multicast =
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		bnx2x_hilo(&estats->total_multicast_packets_received_hi);
4209

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4210
	nstats->collisions =
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		bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
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	nstats->rx_length_errors =
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		bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
		bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
	nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
				 bnx2x_hilo(&estats->brb_truncate_hi);
	nstats->rx_crc_errors =
		bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
	nstats->rx_frame_errors =
		bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
	nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
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	nstats->rx_missed_errors = estats->xxoverflow_discard;

	nstats->rx_errors = nstats->rx_length_errors +
			    nstats->rx_over_errors +
			    nstats->rx_crc_errors +
			    nstats->rx_frame_errors +
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			    nstats->rx_fifo_errors +
			    nstats->rx_missed_errors;
4231

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	nstats->tx_aborted_errors =
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		bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
		bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
	nstats->tx_carrier_errors =
		bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
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	nstats->tx_fifo_errors = 0;
	nstats->tx_heartbeat_errors = 0;
	nstats->tx_window_errors = 0;

	nstats->tx_errors = nstats->tx_aborted_errors +
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			    nstats->tx_carrier_errors +
	    bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
}

static void bnx2x_drv_stats_update(struct bnx2x *bp)
{
	struct bnx2x_eth_stats *estats = &bp->eth_stats;
	int i;

	estats->driver_xoff = 0;
	estats->rx_err_discard_pkt = 0;
	estats->rx_skb_alloc_failed = 0;
	estats->hw_csum_err = 0;
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	for_each_rx_queue(bp, i) {
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		struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;

		estats->driver_xoff += qstats->driver_xoff;
		estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
		estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
		estats->hw_csum_err += qstats->hw_csum_err;
	}
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}

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static void bnx2x_stats_update(struct bnx2x *bp)
4266
{
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	u32 *stats_comp = bnx2x_sp(bp, stats_comp);
4268

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	if (*stats_comp != DMAE_COMP_VAL)
		return;

	if (bp->port.pmf)
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		bnx2x_hw_stats_update(bp);
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	if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
		BNX2X_ERR("storm stats were not updated for 3 times\n");
		bnx2x_panic();
		return;
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	}

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	bnx2x_net_stats_update(bp);
	bnx2x_drv_stats_update(bp);

4284
	if (bp->msglevel & NETIF_MSG_TIMER) {
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		struct bnx2x_fastpath *fp0_rx = bp->fp;
		struct bnx2x_fastpath *fp0_tx = &(bp->fp[bp->num_rx_queues]);
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		struct tstorm_per_client_stats *old_tclient =
							&bp->fp->old_tclient;
		struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats;
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		struct bnx2x_eth_stats *estats = &bp->eth_stats;
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		struct net_device_stats *nstats = &bp->dev->stats;
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		int i;
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		printk(KERN_DEBUG "%s:\n", bp->dev->name);
		printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
				  "  tx pkt (%lx)\n",
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		       bnx2x_tx_avail(fp0_tx),
		       le16_to_cpu(*fp0_tx->tx_cons_sb), nstats->tx_packets);
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		printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
				  "  rx pkt (%lx)\n",
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		       (u16)(le16_to_cpu(*fp0_rx->rx_cons_sb) -
			     fp0_rx->rx_comp_cons),
		       le16_to_cpu(*fp0_rx->rx_cons_sb), nstats->rx_packets);
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		printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u  "
				  "brb truncate %u\n",
		       (netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"),
		       qstats->driver_xoff,
		       estats->brb_drop_lo, estats->brb_truncate_lo);
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		printk(KERN_DEBUG "tstats: checksum_discard %u  "
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			"packets_too_big_discard %lu  no_buff_discard %lu  "
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			"mac_discard %u  mac_filter_discard %u  "
			"xxovrflow_discard %u  brb_truncate_discard %u  "
			"ttl0_discard %u\n",
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		       le32_to_cpu(old_tclient->checksum_discard),
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		       bnx2x_hilo(&qstats->etherstatsoverrsizepkts_hi),
		       bnx2x_hilo(&qstats->no_buff_discard_hi),
		       estats->mac_discard, estats->mac_filter_discard,
		       estats->xxoverflow_discard, estats->brb_truncate_discard,
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		       le32_to_cpu(old_tclient->ttl0_discard));
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		for_each_queue(bp, i) {
			printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
			       bnx2x_fp(bp, i, tx_pkt),
			       bnx2x_fp(bp, i, rx_pkt),
			       bnx2x_fp(bp, i, rx_calls));
		}
	}

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	bnx2x_hw_stats_post(bp);
	bnx2x_storm_stats_post(bp);
}
4332

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static void bnx2x_port_stats_stop(struct bnx2x *bp)
{
	struct dmae_command *dmae;
	u32 opcode;
	int loader_idx = PMF_DMAE_C(bp);
	u32 *stats_comp = bnx2x_sp(bp, stats_comp);
4339

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4340
	bp->executer_idx = 0;
4341

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	opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
		  DMAE_CMD_C_ENABLE |
		  DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4345
#ifdef __BIG_ENDIAN
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		  DMAE_CMD_ENDIANITY_B_DW_SWAP |
4347
#else
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		  DMAE_CMD_ENDIANITY_DW_SWAP |
4349
#endif
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		  (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
		  (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));

	if (bp->port.port_stx) {

		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		if (bp->func_stx)
			dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
		else
			dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
		dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
		dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
		dmae->dst_addr_lo = bp->port.port_stx >> 2;
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		dmae->dst_addr_hi = 0;
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		dmae->len = sizeof(struct host_port_stats) >> 2;
		if (bp->func_stx) {
			dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
			dmae->comp_addr_hi = 0;
			dmae->comp_val = 1;
		} else {
			dmae->comp_addr_lo =
				U64_LO(bnx2x_sp_mapping(bp, stats_comp));
			dmae->comp_addr_hi =
				U64_HI(bnx2x_sp_mapping(bp, stats_comp));
			dmae->comp_val = DMAE_COMP_VAL;
4375

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			*stats_comp = 0;
		}
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	}

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	if (bp->func_stx) {

		dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
		dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
		dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
		dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
		dmae->dst_addr_lo = bp->func_stx >> 2;
		dmae->dst_addr_hi = 0;
		dmae->len = sizeof(struct host_func_stats) >> 2;
		dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
		dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
		dmae->comp_val = DMAE_COMP_VAL;

		*stats_comp = 0;
4394
	}
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}

static void bnx2x_stats_stop(struct bnx2x *bp)
{
	int update = 0;

	bnx2x_stats_comp(bp);

	if (bp->port.pmf)
		update = (bnx2x_hw_stats_update(bp) == 0);

	update |= (bnx2x_storm_stats_update(bp) == 0);

	if (update) {
		bnx2x_net_stats_update(bp);
4410

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		if (bp->port.pmf)
			bnx2x_port_stats_stop(bp);

		bnx2x_hw_stats_post(bp);
		bnx2x_stats_comp(bp);
4416 4417 4418
	}
}

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static void bnx2x_stats_do_nothing(struct bnx2x *bp)
{
}

static const struct {
	void (*action)(struct bnx2x *bp);
	enum bnx2x_stats_state next_state;
} bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
/* state	event	*/
{
/* DISABLED	PMF	*/ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
/*		LINK_UP	*/ {bnx2x_stats_start,      STATS_STATE_ENABLED},
/*		UPDATE	*/ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
/*		STOP	*/ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
},
{
/* ENABLED	PMF	*/ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
/*		LINK_UP	*/ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
/*		UPDATE	*/ {bnx2x_stats_update,     STATS_STATE_ENABLED},
/*		STOP	*/ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
}
};

static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
{
	enum bnx2x_stats_state state = bp->stats_state;

	bnx2x_stats_stm[state][event].action(bp);
	bp->stats_state = bnx2x_stats_stm[state][event].next_state;

	if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
		DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
		   state, event, bp->stats_state);
}

4454 4455 4456 4457 4458 4459 4460 4461
static void bnx2x_timer(unsigned long data)
{
	struct bnx2x *bp = (struct bnx2x *) data;

	if (!netif_running(bp->dev))
		return;

	if (atomic_read(&bp->intr_sem) != 0)
4462
		goto timer_restart;
4463 4464 4465 4466 4467

	if (poll) {
		struct bnx2x_fastpath *fp = &bp->fp[0];
		int rc;

4468
		bnx2x_tx_int(fp);
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		rc = bnx2x_rx_int(fp, 1000);
	}

4472 4473
	if (!BP_NOMCP(bp)) {
		int func = BP_FUNC(bp);
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		u32 drv_pulse;
		u32 mcp_pulse;

		++bp->fw_drv_pulse_wr_seq;
		bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
		/* TBD - add SYSTEM_TIME */
		drv_pulse = bp->fw_drv_pulse_wr_seq;
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		SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
4482

4483
		mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
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			     MCP_PULSE_SEQ_MASK);
		/* The delta between driver pulse and mcp response
		 * should be 1 (before mcp response) or 0 (after mcp response)
		 */
		if ((drv_pulse != mcp_pulse) &&
		    (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
			/* someone lost a heartbeat... */
			BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
				  drv_pulse, mcp_pulse);
		}
	}

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	if ((bp->state == BNX2X_STATE_OPEN) ||
	    (bp->state == BNX2X_STATE_DISABLED))
		bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
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4500
timer_restart:
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	mod_timer(&bp->timer, jiffies + bp->current_interval);
}

/* end of Statistics */

/* nic init */

/*
 * nic init service functions
 */

4512
static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4513
{
4514 4515
	int port = BP_PORT(bp);

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	/* "CSTORM" */
	bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
			CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
			CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
	bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
			CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
			CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
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}

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static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
			  dma_addr_t mapping, int sb_id)
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{
	int port = BP_PORT(bp);
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	int func = BP_FUNC(bp);
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	int index;
4531
	u64 section;
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	/* USTORM */
	section = ((u64)mapping) + offsetof(struct host_status_block,
					    u_status_block);
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	sb->u_status_block.status_block_id = sb_id;
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	REG_WR(bp, BAR_CSTRORM_INTMEM +
	       CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section));
	REG_WR(bp, BAR_CSTRORM_INTMEM +
	       ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
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	       U64_HI(section));
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	REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_USB_FUNC_OFF +
		CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
4545 4546

	for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
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		REG_WR16(bp, BAR_CSTRORM_INTMEM +
			 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 1);
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	/* CSTORM */
	section = ((u64)mapping) + offsetof(struct host_status_block,
					    c_status_block);
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	sb->c_status_block.status_block_id = sb_id;
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	REG_WR(bp, BAR_CSTRORM_INTMEM +
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	       CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
4557
	REG_WR(bp, BAR_CSTRORM_INTMEM +
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	       ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
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	       U64_HI(section));
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	REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
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		CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
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	for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
		REG_WR16(bp, BAR_CSTRORM_INTMEM +
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			 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 1);
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	bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
}

static void bnx2x_zero_def_sb(struct bnx2x *bp)
{
	int func = BP_FUNC(bp);
4573

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	bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY +
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			TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
			sizeof(struct tstorm_def_status_block)/4);
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	bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
			CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
			sizeof(struct cstorm_def_status_block_u)/4);
	bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
			CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
			sizeof(struct cstorm_def_status_block_c)/4);
	bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY +
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			XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
			sizeof(struct xstorm_def_status_block)/4);
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}

static void bnx2x_init_def_sb(struct bnx2x *bp,
			      struct host_def_status_block *def_sb,
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			      dma_addr_t mapping, int sb_id)
4591
{
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	int port = BP_PORT(bp);
	int func = BP_FUNC(bp);
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	int index, val, reg_offset;
	u64 section;

	/* ATTN */
	section = ((u64)mapping) + offsetof(struct host_def_status_block,
					    atten_status_block);
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	def_sb->atten_status_block.status_block_id = sb_id;
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	bp->attn_state = 0;

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	reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
			     MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);

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	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
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		bp->attn_group[index].sig[0] = REG_RD(bp,
						     reg_offset + 0x10*index);
		bp->attn_group[index].sig[1] = REG_RD(bp,
					       reg_offset + 0x4 + 0x10*index);
		bp->attn_group[index].sig[2] = REG_RD(bp,
					       reg_offset + 0x8 + 0x10*index);
		bp->attn_group[index].sig[3] = REG_RD(bp,
					       reg_offset + 0xc + 0x10*index);
	}

	reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
			     HC_REG_ATTN_MSG0_ADDR_L);

	REG_WR(bp, reg_offset, U64_LO(section));
	REG_WR(bp, reg_offset + 4, U64_HI(section));

	reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);

	val = REG_RD(bp, reg_offset);
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	val |= sb_id;
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	REG_WR(bp, reg_offset, val);

	/* USTORM */
	section = ((u64)mapping) + offsetof(struct host_def_status_block,
					    u_def_status_block);
4633
	def_sb->u_def_status_block.status_block_id = sb_id;
4634

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	REG_WR(bp, BAR_CSTRORM_INTMEM +
	       CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section));
	REG_WR(bp, BAR_CSTRORM_INTMEM +
	       ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4),
4639
	       U64_HI(section));
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	REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_USB_FUNC_OFF +
		CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
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	for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
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		REG_WR16(bp, BAR_CSTRORM_INTMEM +
			 CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
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	/* CSTORM */
	section = ((u64)mapping) + offsetof(struct host_def_status_block,
					    c_def_status_block);
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	def_sb->c_def_status_block.status_block_id = sb_id;
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	REG_WR(bp, BAR_CSTRORM_INTMEM +
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	       CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
4654
	REG_WR(bp, BAR_CSTRORM_INTMEM +
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	       ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4),
4656
	       U64_HI(section));
4657
	REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
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		CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
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	for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
		REG_WR16(bp, BAR_CSTRORM_INTMEM +
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			 CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
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	/* TSTORM */
	section = ((u64)mapping) + offsetof(struct host_def_status_block,
					    t_def_status_block);
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	def_sb->t_def_status_block.status_block_id = sb_id;
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	REG_WR(bp, BAR_TSTRORM_INTMEM +
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	       TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
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	REG_WR(bp, BAR_TSTRORM_INTMEM +
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	       ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
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	       U64_HI(section));
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	REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
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		TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
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	for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
		REG_WR16(bp, BAR_TSTRORM_INTMEM +
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			 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
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	/* XSTORM */
	section = ((u64)mapping) + offsetof(struct host_def_status_block,
					    x_def_status_block);
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	def_sb->x_def_status_block.status_block_id = sb_id;
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	REG_WR(bp, BAR_XSTRORM_INTMEM +
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	       XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
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	REG_WR(bp, BAR_XSTRORM_INTMEM +
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	       ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
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	       U64_HI(section));
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	REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
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		XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
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	for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
		REG_WR16(bp, BAR_XSTRORM_INTMEM +
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			 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4697

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	bp->stats_pending = 0;
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	bp->set_mac_pending = 0;
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	bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
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}

static void bnx2x_update_coalesce(struct bnx2x *bp)
{
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	int port = BP_PORT(bp);
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	int i;

	for_each_queue(bp, i) {
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		int sb_id = bp->fp[i].sb_id;
4711 4712

		/* HC_INDEX_U_ETH_RX_CQ_CONS */
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		REG_WR8(bp, BAR_CSTRORM_INTMEM +
			CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
						      U_SB_ETH_RX_CQ_INDEX),
4716
			bp->rx_ticks/12);
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		REG_WR16(bp, BAR_CSTRORM_INTMEM +
			 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
						       U_SB_ETH_RX_CQ_INDEX),
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			 (bp->rx_ticks/12) ? 0 : 1);
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		/* HC_INDEX_C_ETH_TX_CQ_CONS */
		REG_WR8(bp, BAR_CSTRORM_INTMEM +
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			CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
						      C_SB_ETH_TX_CQ_INDEX),
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			bp->tx_ticks/12);
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		REG_WR16(bp, BAR_CSTRORM_INTMEM +
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			 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
						       C_SB_ETH_TX_CQ_INDEX),
4730
			 (bp->tx_ticks/12) ? 0 : 1);
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	}
}

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static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
				       struct bnx2x_fastpath *fp, int last)
{
	int i;

	for (i = 0; i < last; i++) {
		struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
		struct sk_buff *skb = rx_buf->skb;

		if (skb == NULL) {
			DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
			continue;
		}

		if (fp->tpa_state[i] == BNX2X_TPA_START)
			pci_unmap_single(bp->pdev,
					 pci_unmap_addr(rx_buf, mapping),
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					 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
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		dev_kfree_skb(skb);
		rx_buf->skb = NULL;
	}
}

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static void bnx2x_init_rx_rings(struct bnx2x *bp)
{
4760
	int func = BP_FUNC(bp);
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	int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
					      ETH_MAX_AGGREGATION_QUEUES_E1H;
	u16 ring_prod, cqe_ring_prod;
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	int i, j;

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	bp->rx_buf_size = bp->dev->mtu + ETH_OVREHEAD + BNX2X_RX_ALIGN;
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	DP(NETIF_MSG_IFUP,
	   "mtu %d  rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
4769

4770 4771
	if (bp->flags & TPA_ENABLE_FLAG) {

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		for_each_rx_queue(bp, j) {
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			struct bnx2x_fastpath *fp = &bp->fp[j];
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			for (i = 0; i < max_agg_queues; i++) {
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				fp->tpa_pool[i].skb =
				   netdev_alloc_skb(bp->dev, bp->rx_buf_size);
				if (!fp->tpa_pool[i].skb) {
					BNX2X_ERR("Failed to allocate TPA "
						  "skb pool for queue[%d] - "
						  "disabling TPA on this "
						  "queue!\n", j);
					bnx2x_free_tpa_pool(bp, fp, i);
					fp->disable_tpa = 1;
					break;
				}
				pci_unmap_addr_set((struct sw_rx_bd *)
							&bp->fp->tpa_pool[i],
						   mapping, 0);
				fp->tpa_state[i] = BNX2X_TPA_STOP;
			}
		}
	}

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	for_each_rx_queue(bp, j) {
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		struct bnx2x_fastpath *fp = &bp->fp[j];

		fp->rx_bd_cons = 0;
		fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
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		fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;

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		/* Mark queue as Rx */
		fp->is_rx_queue = 1;

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		/* "next page" elements initialization */
		/* SGE ring */
		for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
			struct eth_rx_sge *sge;

			sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
			sge->addr_hi =
				cpu_to_le32(U64_HI(fp->rx_sge_mapping +
					BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
			sge->addr_lo =
				cpu_to_le32(U64_LO(fp->rx_sge_mapping +
					BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
		}

		bnx2x_init_sge_ring_bit_mask(fp);
4820

4821
		/* RX BD ring */
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		for (i = 1; i <= NUM_RX_RINGS; i++) {
			struct eth_rx_bd *rx_bd;

			rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
			rx_bd->addr_hi =
				cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4828
					    BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
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			rx_bd->addr_lo =
				cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4831
					    BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
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		}

4834
		/* CQ ring */
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		for (i = 1; i <= NUM_RCQ_RINGS; i++) {
			struct eth_rx_cqe_next_page *nextpg;

			nextpg = (struct eth_rx_cqe_next_page *)
				&fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
			nextpg->addr_hi =
				cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4842
					   BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4843 4844
			nextpg->addr_lo =
				cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4845
					   BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4846 4847
		}

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		/* Allocate SGEs and initialize the ring elements */
		for (i = 0, ring_prod = 0;
		     i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4851

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			if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
				BNX2X_ERR("was only able to allocate "
					  "%d rx sges\n", i);
				BNX2X_ERR("disabling TPA for queue[%d]\n", j);
				/* Cleanup already allocated elements */
				bnx2x_free_rx_sge_range(bp, fp, ring_prod);
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				bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
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				fp->disable_tpa = 1;
				ring_prod = 0;
				break;
			}
			ring_prod = NEXT_SGE_IDX(ring_prod);
		}
		fp->rx_sge_prod = ring_prod;

		/* Allocate BDs and initialize BD ring */
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		fp->rx_comp_cons = 0;
4869
		cqe_ring_prod = ring_prod = 0;
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		for (i = 0; i < bp->rx_ring_size; i++) {
			if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
				BNX2X_ERR("was only able to allocate "
4873 4874
					  "%d rx skbs on queue[%d]\n", i, j);
				fp->eth_q_stats.rx_skb_alloc_failed++;
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				break;
			}
			ring_prod = NEXT_RX_IDX(ring_prod);
4878
			cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4879
			WARN_ON(ring_prod <= i);
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		}

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		fp->rx_bd_prod = ring_prod;
		/* must not have more available CQEs than BDs */
		fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
				       cqe_ring_prod);
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		fp->rx_pkt = fp->rx_calls = 0;

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		/* Warning!
		 * this will generate an interrupt (to the TSTORM)
		 * must only be done after chip is initialized
		 */
		bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
				     fp->rx_sge_prod);
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		if (j != 0)
			continue;

		REG_WR(bp, BAR_USTRORM_INTMEM +
4898
		       USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
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		       U64_LO(fp->rx_comp_mapping));
		REG_WR(bp, BAR_USTRORM_INTMEM +
4901
		       USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
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		       U64_HI(fp->rx_comp_mapping));
	}
}

static void bnx2x_init_tx_ring(struct bnx2x *bp)
{
	int i, j;

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	for_each_tx_queue(bp, j) {
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		struct bnx2x_fastpath *fp = &bp->fp[j];

		for (i = 1; i <= NUM_TX_RINGS; i++) {
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			struct eth_tx_next_bd *tx_next_bd =
				&fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
4916

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			tx_next_bd->addr_hi =
4918
				cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4919
					    BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
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			tx_next_bd->addr_lo =
4921
				cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4922
					    BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4923 4924
		}

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		fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE;
		fp->tx_db.data.zero_fill1 = 0;
		fp->tx_db.data.prod = 0;

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		fp->tx_pkt_prod = 0;
		fp->tx_pkt_cons = 0;
		fp->tx_bd_prod = 0;
		fp->tx_bd_cons = 0;
		fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
		fp->tx_pkt = 0;
	}
}

static void bnx2x_init_sp_ring(struct bnx2x *bp)
{
4940
	int func = BP_FUNC(bp);
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	spin_lock_init(&bp->spq_lock);

	bp->spq_left = MAX_SPQ_PENDING;
	bp->spq_prod_idx = 0;
	bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
	bp->spq_prod_bd = bp->spq;
	bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;

4950
	REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4951
	       U64_LO(bp->spq_mapping));
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	REG_WR(bp,
	       XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
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	       U64_HI(bp->spq_mapping));

4956
	REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
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	       bp->spq_prod_idx);
}

static void bnx2x_init_context(struct bnx2x *bp)
{
	int i;

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	for_each_rx_queue(bp, i) {
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		struct eth_context *context = bnx2x_sp(bp, context[i].eth);
		struct bnx2x_fastpath *fp = &bp->fp[i];
4967
		u8 cl_id = fp->cl_id;
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		context->ustorm_st_context.common.sb_index_numbers =
						BNX2X_RX_SB_INDEX_NUM;
4971
		context->ustorm_st_context.common.clientId = cl_id;
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		context->ustorm_st_context.common.status_block_id = fp->sb_id;
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		context->ustorm_st_context.common.flags =
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			(USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
			 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
		context->ustorm_st_context.common.statistics_counter_id =
						cl_id;
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		context->ustorm_st_context.common.mc_alignment_log_size =
4979
						BNX2X_RX_ALIGN_SHIFT;
4980
		context->ustorm_st_context.common.bd_buff_size =
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						bp->rx_buf_size;
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		context->ustorm_st_context.common.bd_page_base_hi =
4983
						U64_HI(fp->rx_desc_mapping);
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		context->ustorm_st_context.common.bd_page_base_lo =
4985
						U64_LO(fp->rx_desc_mapping);
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		if (!fp->disable_tpa) {
			context->ustorm_st_context.common.flags |=
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				USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
4989
			context->ustorm_st_context.common.sge_buff_size =
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				(u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
					 (u32)0xffff);
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			context->ustorm_st_context.common.sge_page_base_hi =
						U64_HI(fp->rx_sge_mapping);
			context->ustorm_st_context.common.sge_page_base_lo =
						U64_LO(fp->rx_sge_mapping);
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			context->ustorm_st_context.common.max_sges_for_packet =
				SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
			context->ustorm_st_context.common.max_sges_for_packet =
				((context->ustorm_st_context.common.
				  max_sges_for_packet + PAGES_PER_SGE - 1) &
				 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
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		}

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		context->ustorm_ag_context.cdu_usage =
			CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
					       CDU_REGION_NUMBER_UCM_AG,
					       ETH_CONNECTION_TYPE);

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		context->xstorm_ag_context.cdu_reserved =
			CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
					       CDU_REGION_NUMBER_XCM_AG,
					       ETH_CONNECTION_TYPE);
	}

	for_each_tx_queue(bp, i) {
		struct bnx2x_fastpath *fp = &bp->fp[i];
		struct eth_context *context =
			bnx2x_sp(bp, context[i - bp->num_rx_queues].eth);

		context->cstorm_st_context.sb_index_number =
						C_SB_ETH_TX_CQ_INDEX;
		context->cstorm_st_context.status_block_id = fp->sb_id;

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		context->xstorm_st_context.tx_bd_page_base_hi =
						U64_HI(fp->tx_desc_mapping);
		context->xstorm_st_context.tx_bd_page_base_lo =
						U64_LO(fp->tx_desc_mapping);
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		context->xstorm_st_context.statistics_data = (fp->cl_id |
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				XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
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	}
}

static void bnx2x_init_ind_table(struct bnx2x *bp)
{
5036
	int func = BP_FUNC(bp);
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	int i;

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	if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
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		return;

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	DP(NETIF_MSG_IFUP,
	   "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
5044
	for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
5045
		REG_WR8(bp, BAR_TSTRORM_INTMEM +
5046
			TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
5047
			bp->fp->cl_id + (i % bp->num_rx_queues));
5048 5049
}

5050 5051 5052
static void bnx2x_set_client_config(struct bnx2x *bp)
{
	struct tstorm_eth_client_config tstorm_client = {0};
5053 5054
	int port = BP_PORT(bp);
	int i;
5055

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5056
	tstorm_client.mtu = bp->dev->mtu;
5057
	tstorm_client.config_flags =
5058 5059
				(TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
				 TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
5060
#ifdef BCM_VLAN
5061
	if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
5062
		tstorm_client.config_flags |=
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5063
				TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
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		DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
	}
#endif

	for_each_queue(bp, i) {
5069 5070
		tstorm_client.statistics_counter_id = bp->fp[i].cl_id;

5071
		REG_WR(bp, BAR_TSTRORM_INTMEM +
5072
		       TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
5073 5074
		       ((u32 *)&tstorm_client)[0]);
		REG_WR(bp, BAR_TSTRORM_INTMEM +
5075
		       TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
5076 5077 5078
		       ((u32 *)&tstorm_client)[1]);
	}

5079 5080
	DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
	   ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
5081 5082
}

5083 5084 5085
static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
{
	struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
5086 5087 5088
	int mode = bp->rx_mode;
	int mask = (1 << BP_L_ID(bp));
	int func = BP_FUNC(bp);
5089
	int port = BP_PORT(bp);
5090
	int i;
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	/* All but management unicast packets should pass to the host as well */
	u32 llh_mask =
		NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
		NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
		NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
		NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
5097

5098
	DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
5099 5100 5101

	switch (mode) {
	case BNX2X_RX_MODE_NONE: /* no Rx */
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		tstorm_mac_filter.ucast_drop_all = mask;
		tstorm_mac_filter.mcast_drop_all = mask;
		tstorm_mac_filter.bcast_drop_all = mask;
5105
		break;
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5106

5107
	case BNX2X_RX_MODE_NORMAL:
5108
		tstorm_mac_filter.bcast_accept_all = mask;
5109
		break;
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5110

5111
	case BNX2X_RX_MODE_ALLMULTI:
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		tstorm_mac_filter.mcast_accept_all = mask;
		tstorm_mac_filter.bcast_accept_all = mask;
5114
		break;
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5115

5116
	case BNX2X_RX_MODE_PROMISC:
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		tstorm_mac_filter.ucast_accept_all = mask;
		tstorm_mac_filter.mcast_accept_all = mask;
		tstorm_mac_filter.bcast_accept_all = mask;
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		/* pass management unicast packets as well */
		llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
5122
		break;
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5123

5124
	default:
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		BNX2X_ERR("BAD rx mode (%d)\n", mode);
		break;
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	}

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	REG_WR(bp,
	       (port ? NIG_REG_LLH1_BRB1_DRV_MASK : NIG_REG_LLH0_BRB1_DRV_MASK),
	       llh_mask);

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	for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
		REG_WR(bp, BAR_TSTRORM_INTMEM +
5135
		       TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
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		       ((u32 *)&tstorm_mac_filter)[i]);

5138
/*		DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
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		   ((u32 *)&tstorm_mac_filter)[i]); */
	}

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	if (mode != BNX2X_RX_MODE_NONE)
		bnx2x_set_client_config(bp);
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}

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static void bnx2x_init_internal_common(struct bnx2x *bp)
{
	int i;

	/* Zero this manually as its initialization is
	   currently missing in the initTool */
	for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
		REG_WR(bp, BAR_USTRORM_INTMEM +
		       USTORM_AGG_DATA_OFFSET + i * 4, 0);
}

static void bnx2x_init_internal_port(struct bnx2x *bp)
{
	int port = BP_PORT(bp);

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5161 5162 5163 5164
	REG_WR(bp,
	       BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BNX2X_BTR);
	REG_WR(bp,
	       BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BNX2X_BTR);
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	REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
	REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
}

static void bnx2x_init_internal_func(struct bnx2x *bp)
5170 5171 5172
{
	struct tstorm_eth_function_common_config tstorm_config = {0};
	struct stats_indication_flags stats_flags = {0};
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	int port = BP_PORT(bp);
	int func = BP_FUNC(bp);
5175 5176
	int i, j;
	u32 offset;
5177
	u16 max_agg_size;
5178 5179

	if (is_multi(bp)) {
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5180
		tstorm_config.config_flags = MULTI_FLAGS(bp);
5181 5182
		tstorm_config.rss_result_mask = MULTI_MASK;
	}
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	/* Enable TPA if needed */
	if (bp->flags & TPA_ENABLE_FLAG)
		tstorm_config.config_flags |=
			TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;

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5189 5190 5191
	if (IS_E1HMF(bp))
		tstorm_config.config_flags |=
				TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
5192

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	tstorm_config.leading_client_id = BP_L_ID(bp);

5195
	REG_WR(bp, BAR_TSTRORM_INTMEM +
5196
	       TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
5197 5198
	       (*(u32 *)&tstorm_config));

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5199
	bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
5200 5201
	bnx2x_set_storm_rx_mode(bp);

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	for_each_queue(bp, i) {
		u8 cl_id = bp->fp[i].cl_id;

		/* reset xstorm per client statistics */
		offset = BAR_XSTRORM_INTMEM +
			 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
		for (j = 0;
		     j < sizeof(struct xstorm_per_client_stats) / 4; j++)
			REG_WR(bp, offset + j*4, 0);

		/* reset tstorm per client statistics */
		offset = BAR_TSTRORM_INTMEM +
			 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
		for (j = 0;
		     j < sizeof(struct tstorm_per_client_stats) / 4; j++)
			REG_WR(bp, offset + j*4, 0);

		/* reset ustorm per client statistics */
		offset = BAR_USTRORM_INTMEM +
			 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
		for (j = 0;
		     j < sizeof(struct ustorm_per_client_stats) / 4; j++)
			REG_WR(bp, offset + j*4, 0);
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5225 5226 5227
	}

	/* Init statistics related context */
5228
	stats_flags.collect_eth = 1;
5229

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5230
	REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
5231
	       ((u32 *)&stats_flags)[0]);
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5232
	REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
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	       ((u32 *)&stats_flags)[1]);

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5235
	REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
5236
	       ((u32 *)&stats_flags)[0]);
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5237
	REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
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	       ((u32 *)&stats_flags)[1]);

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	REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
	       ((u32 *)&stats_flags)[0]);
	REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
	       ((u32 *)&stats_flags)[1]);

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5245
	REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
5246
	       ((u32 *)&stats_flags)[0]);
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5247
	REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
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	       ((u32 *)&stats_flags)[1]);

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5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262
	REG_WR(bp, BAR_XSTRORM_INTMEM +
	       XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
	       U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
	REG_WR(bp, BAR_XSTRORM_INTMEM +
	       XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
	       U64_HI(bnx2x_sp_mapping(bp, fw_stats)));

	REG_WR(bp, BAR_TSTRORM_INTMEM +
	       TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
	       U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
	REG_WR(bp, BAR_TSTRORM_INTMEM +
	       TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
	       U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
5263

5264 5265 5266 5267 5268 5269 5270
	REG_WR(bp, BAR_USTRORM_INTMEM +
	       USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
	       U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
	REG_WR(bp, BAR_USTRORM_INTMEM +
	       USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
	       U64_HI(bnx2x_sp_mapping(bp, fw_stats)));

5271 5272 5273 5274 5275 5276 5277 5278 5279 5280
	if (CHIP_IS_E1H(bp)) {
		REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
			IS_E1HMF(bp));
		REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
			IS_E1HMF(bp));
		REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
			IS_E1HMF(bp));
		REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
			IS_E1HMF(bp));

5281 5282
		REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
			 bp->e1hov);
5283 5284
	}

5285 5286 5287 5288 5289
	/* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
	max_agg_size =
		min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
			  SGE_PAGE_SIZE * PAGES_PER_SGE),
		    (u32)0xffff);
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5290
	for_each_rx_queue(bp, i) {
5291 5292 5293
		struct bnx2x_fastpath *fp = &bp->fp[i];

		REG_WR(bp, BAR_USTRORM_INTMEM +
5294
		       USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
5295 5296
		       U64_LO(fp->rx_comp_mapping));
		REG_WR(bp, BAR_USTRORM_INTMEM +
5297
		       USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
5298 5299
		       U64_HI(fp->rx_comp_mapping));

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5300 5301 5302 5303 5304 5305 5306 5307
		/* Next page */
		REG_WR(bp, BAR_USTRORM_INTMEM +
		       USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id),
		       U64_LO(fp->rx_comp_mapping + BCM_PAGE_SIZE));
		REG_WR(bp, BAR_USTRORM_INTMEM +
		       USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4,
		       U64_HI(fp->rx_comp_mapping + BCM_PAGE_SIZE));

5308
		REG_WR16(bp, BAR_USTRORM_INTMEM +
5309
			 USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
5310 5311
			 max_agg_size);
	}
5312

5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344
	/* dropless flow control */
	if (CHIP_IS_E1H(bp)) {
		struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};

		rx_pause.bd_thr_low = 250;
		rx_pause.cqe_thr_low = 250;
		rx_pause.cos = 1;
		rx_pause.sge_thr_low = 0;
		rx_pause.bd_thr_high = 350;
		rx_pause.cqe_thr_high = 350;
		rx_pause.sge_thr_high = 0;

		for_each_rx_queue(bp, i) {
			struct bnx2x_fastpath *fp = &bp->fp[i];

			if (!fp->disable_tpa) {
				rx_pause.sge_thr_low = 150;
				rx_pause.sge_thr_high = 250;
			}


			offset = BAR_USTRORM_INTMEM +
				 USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
								   fp->cl_id);
			for (j = 0;
			     j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
			     j++)
				REG_WR(bp, offset + j*4,
				       ((u32 *)&rx_pause)[j]);
		}
	}

5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382
	memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));

	/* Init rate shaping and fairness contexts */
	if (IS_E1HMF(bp)) {
		int vn;

		/* During init there is no active link
		   Until link is up, set link rate to 10Gbps */
		bp->link_vars.line_speed = SPEED_10000;
		bnx2x_init_port_minmax(bp);

		bnx2x_calc_vn_weight_sum(bp);

		for (vn = VN_0; vn < E1HVN_MAX; vn++)
			bnx2x_init_vn_minmax(bp, 2*vn + port);

		/* Enable rate shaping and fairness */
		bp->cmng.flags.cmng_enables =
					CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
		if (bp->vn_weight_sum)
			bp->cmng.flags.cmng_enables |=
					CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
		else
			DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
			   "  fairness will be disabled\n");
	} else {
		/* rate shaping and fairness are disabled */
		DP(NETIF_MSG_IFUP,
		   "single function mode  minmax will be disabled\n");
	}


	/* Store it to internal memory */
	if (bp->port.pmf)
		for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
			REG_WR(bp, BAR_XSTRORM_INTMEM +
			       XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
			       ((u32 *)(&bp->cmng))[i]);
5383 5384
}

5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406
static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
{
	switch (load_code) {
	case FW_MSG_CODE_DRV_LOAD_COMMON:
		bnx2x_init_internal_common(bp);
		/* no break */

	case FW_MSG_CODE_DRV_LOAD_PORT:
		bnx2x_init_internal_port(bp);
		/* no break */

	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
		bnx2x_init_internal_func(bp);
		break;

	default:
		BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
		break;
	}
}

static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5407 5408 5409 5410 5411 5412
{
	int i;

	for_each_queue(bp, i) {
		struct bnx2x_fastpath *fp = &bp->fp[i];

5413
		fp->bp = bp;
5414 5415
		fp->state = BNX2X_FP_STATE_CLOSED;
		fp->index = i;
5416 5417
		fp->cl_id = BP_L_ID(bp) + i;
		fp->sb_id = fp->cl_id;
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5418 5419 5420
		/* Suitable Rx and Tx SBs are served by the same client */
		if (i >= bp->num_rx_queues)
			fp->cl_id -= bp->num_rx_queues;
5421
		DP(NETIF_MSG_IFUP,
5422 5423
		   "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  sb %d\n",
		   i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
5424
		bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
5425
			      fp->sb_id);
5426
		bnx2x_update_fpsb_idx(fp);
5427 5428
	}

5429 5430 5431 5432
	/* ensure status block indices were read */
	rmb();


5433 5434 5435
	bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
			  DEF_SB_ID);
	bnx2x_update_dsb_idx(bp);
5436 5437 5438 5439 5440
	bnx2x_update_coalesce(bp);
	bnx2x_init_rx_rings(bp);
	bnx2x_init_tx_ring(bp);
	bnx2x_init_sp_ring(bp);
	bnx2x_init_context(bp);
5441
	bnx2x_init_internal(bp, load_code);
5442
	bnx2x_init_ind_table(bp);
5443 5444 5445 5446 5447 5448 5449 5450 5451
	bnx2x_stats_init(bp);

	/* At this point, we are ready for interrupts */
	atomic_set(&bp->intr_sem, 0);

	/* flush all before enabling interrupts */
	mb();
	mmiowb();

5452
	bnx2x_int_enable(bp);
5453 5454 5455 5456 5457

	/* Check for SPIO5 */
	bnx2x_attn_int_deasserted0(bp,
		REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
				   AEU_INPUTS_ATTN_BITS_SPIO5);
5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494
}

/* end of nic init */

/*
 * gzip service functions
 */

static int bnx2x_gunzip_init(struct bnx2x *bp)
{
	bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
					      &bp->gunzip_mapping);
	if (bp->gunzip_buf  == NULL)
		goto gunzip_nomem1;

	bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
	if (bp->strm  == NULL)
		goto gunzip_nomem2;

	bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
				      GFP_KERNEL);
	if (bp->strm->workspace == NULL)
		goto gunzip_nomem3;

	return 0;

gunzip_nomem3:
	kfree(bp->strm);
	bp->strm = NULL;

gunzip_nomem2:
	pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
			    bp->gunzip_mapping);
	bp->gunzip_buf = NULL;

gunzip_nomem1:
	printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
5495
	       " un-compression\n", bp->dev->name);
5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512
	return -ENOMEM;
}

static void bnx2x_gunzip_end(struct bnx2x *bp)
{
	kfree(bp->strm->workspace);

	kfree(bp->strm);
	bp->strm = NULL;

	if (bp->gunzip_buf) {
		pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
				    bp->gunzip_mapping);
		bp->gunzip_buf = NULL;
	}
}

5513
static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5514 5515 5516 5517
{
	int n, rc;

	/* check gzip header */
5518 5519
	if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
		BNX2X_ERR("Bad gzip header\n");
5520
		return -EINVAL;
5521
	}
5522 5523 5524

	n = 10;

5525
#define FNAME				0x8
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	if (zbuf[3] & FNAME)
		while ((zbuf[n++] != 0) && (n < len));

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	bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
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	bp->strm->avail_in = len - n;
	bp->strm->next_out = bp->gunzip_buf;
	bp->strm->avail_out = FW_BUF_SIZE;

	rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
	if (rc != Z_OK)
		return rc;

	rc = zlib_inflate(bp->strm, Z_FINISH);
	if ((rc != Z_OK) && (rc != Z_STREAM_END))
		printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
		       bp->dev->name, bp->strm->msg);

	bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
	if (bp->gunzip_outlen & 0x3)
		printk(KERN_ERR PFX "%s: Firmware decompression error:"
				    " gunzip_outlen (%d) not aligned\n",
		       bp->dev->name, bp->gunzip_outlen);
	bp->gunzip_outlen >>= 2;

	zlib_inflateEnd(bp->strm);

	if (rc == Z_STREAM_END)
		return 0;

	return rc;
}

/* nic load/unload */

/*
5562
 * General service functions
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 */

/* send a NIG loopback debug packet */
static void bnx2x_lb_pckt(struct bnx2x *bp)
{
	u32 wb_write[3];

	/* Ethernet source and destination addresses */
	wb_write[0] = 0x55555555;
	wb_write[1] = 0x55555555;
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	wb_write[2] = 0x20;		/* SOP */
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	REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);

	/* NON-IP protocol */
	wb_write[0] = 0x09000000;
	wb_write[1] = 0x55555555;
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	wb_write[2] = 0x10;		/* EOP, eop_bvalid = 0 */
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	REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
}

/* some of the internal memories
 * are not directly readable from the driver
 * to test them we send debug packets
 */
static int bnx2x_int_mem_test(struct bnx2x *bp)
{
	int factor;
	int count, i;
	u32 val = 0;

5593
	if (CHIP_REV_IS_FPGA(bp))
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		factor = 120;
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	else if (CHIP_REV_IS_EMUL(bp))
		factor = 200;
	else
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		factor = 1;

	DP(NETIF_MSG_HW, "start part1\n");

	/* Disable inputs of parser neighbor blocks */
	REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
	REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
	REG_WR(bp, CFC_REG_DEBUG0, 0x1);
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	REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
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	/*  Write 0 to parser credits for CFC search request */
	REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);

	/* send Ethernet packet */
	bnx2x_lb_pckt(bp);

	/* TODO do i reset NIG statistic? */
	/* Wait until NIG register shows 1 packet of size 0x10 */
	count = 1000 * factor;
	while (count) {
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		bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
		val = *bnx2x_sp(bp, wb_data[0]);
		if (val == 0x10)
			break;

		msleep(10);
		count--;
	}
	if (val != 0x10) {
		BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
		return -1;
	}

	/* Wait until PRS register shows 1 packet */
	count = 1000 * factor;
	while (count) {
		val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
		if (val == 1)
			break;

		msleep(10);
		count--;
	}
	if (val != 0x1) {
		BNX2X_ERR("PRS timeout val = 0x%x\n", val);
		return -2;
	}

	/* Reset and init BRB, PRS */
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	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
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	msleep(50);
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	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
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	msleep(50);
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	bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
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	DP(NETIF_MSG_HW, "part2\n");

	/* Disable inputs of parser neighbor blocks */
	REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
	REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
	REG_WR(bp, CFC_REG_DEBUG0, 0x1);
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	REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
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	/* Write 0 to parser credits for CFC search request */
	REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);

	/* send 10 Ethernet packets */
	for (i = 0; i < 10; i++)
		bnx2x_lb_pckt(bp);

	/* Wait until NIG register shows 10 + 1
	   packets of size 11*0x10 = 0xb0 */
	count = 1000 * factor;
	while (count) {
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		bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
		val = *bnx2x_sp(bp, wb_data[0]);
		if (val == 0xb0)
			break;

		msleep(10);
		count--;
	}
	if (val != 0xb0) {
		BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
		return -3;
	}

	/* Wait until PRS register shows 2 packets */
	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
	if (val != 2)
		BNX2X_ERR("PRS timeout  val = 0x%x\n", val);

	/* Write 1 to parser credits for CFC search request */
	REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);

	/* Wait until PRS register shows 3 packets */
	msleep(10 * factor);
	/* Wait until NIG register shows 1 packet of size 0x10 */
	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
	if (val != 3)
		BNX2X_ERR("PRS timeout  val = 0x%x\n", val);

	/* clear NIG EOP FIFO */
	for (i = 0; i < 11; i++)
		REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
	val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
	if (val != 1) {
		BNX2X_ERR("clear of NIG failed\n");
		return -4;
	}

	/* Reset and init BRB, PRS, NIG */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
	msleep(50);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
	msleep(50);
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	bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
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#ifndef BCM_ISCSI
	/* set NIC mode */
	REG_WR(bp, PRS_REG_NIC_MODE, 1);
#endif

	/* Enable inputs of parser neighbor blocks */
	REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
	REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
	REG_WR(bp, CFC_REG_DEBUG0, 0x0);
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	REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
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	DP(NETIF_MSG_HW, "done\n");

	return 0; /* OK */
}

static void enable_blocks_attention(struct bnx2x *bp)
{
	REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
	REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
	REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
	REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
	REG_WR(bp, QM_REG_QM_INT_MASK, 0);
	REG_WR(bp, TM_REG_TM_INT_MASK, 0);
	REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
	REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
	REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5746 5747
/*	REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
/*	REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
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	REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
	REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
	REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
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/*	REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
/*	REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
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	REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
	REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
	REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
	REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
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/*	REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
/*	REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
	if (CHIP_REV_IS_FPGA(bp))
		REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
	else
		REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
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	REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
	REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
	REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
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/*	REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
/*	REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
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	REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
	REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
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/*	REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
	REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);		/* bit 3,4 masked */
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}

5774

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static void bnx2x_reset_common(struct bnx2x *bp)
{
	/* reset_common */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
	       0xd3ffff7f);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
}

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static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
{
	u32 val;
	u8 port;
	u8 is_required = 0;

	val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
	      SHARED_HW_CFG_FAN_FAILURE_MASK;

	if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
		is_required = 1;

	/*
	 * The fan failure mechanism is usually related to the PHY type since
	 * the power consumption of the board is affected by the PHY. Currently,
	 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
	 */
	else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
		for (port = PORT_0; port < PORT_MAX; port++) {
			u32 phy_type =
				SHMEM_RD(bp, dev_info.port_hw_config[port].
					 external_phy_config) &
				PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
			is_required |=
				((phy_type ==
				  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
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				 (phy_type ==
				  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
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				 (phy_type ==
				  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
		}

	DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);

	if (is_required == 0)
		return;

	/* Fan failure is indicated by SPIO 5 */
	bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
		       MISC_REGISTERS_SPIO_INPUT_HI_Z);

	/* set to active low mode */
	val = REG_RD(bp, MISC_REG_SPIO_INT);
	val |= ((1 << MISC_REGISTERS_SPIO_5) <<
				MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
	REG_WR(bp, MISC_REG_SPIO_INT, val);

	/* enable interrupt to signal the IGU */
	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
	val |= (1 << MISC_REGISTERS_SPIO_5);
	REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
}

5837
static int bnx2x_init_common(struct bnx2x *bp)
5838 5839 5840
{
	u32 val, i;

5841
	DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
5842

5843
	bnx2x_reset_common(bp);
5844 5845
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5846

5847
	bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
5848 5849
	if (CHIP_IS_E1H(bp))
		REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5850

5851 5852 5853
	REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
	msleep(30);
	REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5854

5855
	bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
5856 5857 5858 5859 5860
	if (CHIP_IS_E1(bp)) {
		/* enable HW interrupt from PXP on USDM overflow
		   bit 16 on INT_MASK_0 */
		REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
	}
5861

5862
	bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
5863
	bnx2x_init_pxp(bp);
5864 5865

#ifdef __BIG_ENDIAN
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	REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
	REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
	REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
	REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
	REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
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	/* make sure this value is 0 */
	REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
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/*	REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
	REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
	REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
	REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
	REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
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#endif

5881
	REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5882
#ifdef BCM_ISCSI
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	REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
	REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
	REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
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#endif

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	if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
		REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
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	/* let the HW do it's magic ... */
	msleep(100);
	/* finish PXP init */
	val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
	if (val != 1) {
		BNX2X_ERR("PXP2 CFG failed\n");
		return -EBUSY;
	}
	val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
	if (val != 1) {
		BNX2X_ERR("PXP2 RD_INIT failed\n");
		return -EBUSY;
	}
5904

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	REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
	REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5907

5908
	bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5909

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	/* clean the DMAE memory */
	bp->dmae_ready = 1;
	bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
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5914 5915 5916 5917
	bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
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	bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
	bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
	bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
	bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);

5924
	bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
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	/* soft reset pulse */
	REG_WR(bp, QM_REG_SOFT_RESET, 1);
	REG_WR(bp, QM_REG_SOFT_RESET, 0);
5928 5929

#ifdef BCM_ISCSI
5930
	bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5931 5932
#endif

5933
	bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
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	REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
	if (!CHIP_REV_IS_SLOW(bp)) {
		/* enable hw interrupt from doorbell Q */
		REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
	}
5939

5940 5941
	bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5942
	REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5943 5944
	/* set NIC mode */
	REG_WR(bp, PRS_REG_NIC_MODE, 1);
5945 5946
	if (CHIP_IS_E1H(bp))
		REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
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5948 5949 5950 5951
	bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5952

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	bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
	bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
	bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
	bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
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	bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
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	/* sync semi rtc */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
	       0x80000000);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
	       0x80000000);
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	bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
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5973 5974 5975 5976 5977
	REG_WR(bp, SRC_REG_SOFT_RST, 1);
	for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
		REG_WR(bp, i, 0xc0cac01a);
		/* TODO: replace with something meaningful */
	}
5978
	bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5979
	REG_WR(bp, SRC_REG_SOFT_RST, 0);
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5981 5982 5983 5984
	if (sizeof(union cdu_context) != 1024)
		/* we currently assume that a context is 1024 bytes */
		printk(KERN_ALERT PFX "please adjust the size of"
		       " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5985

5986
	bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5987 5988
	val = (4 << 24) + (0 << 12) + 1024;
	REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5989

5990
	bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5991
	REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
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	/* enable context validation interrupt from CFC */
	REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);

	/* set the thresholds to prevent CFC/CDU race */
	REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
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	bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
6000

6001
	bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
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	/* Reset PCIE errors for debug */
	REG_WR(bp, 0x2814, 0xffffffff);
	REG_WR(bp, 0x3820, 0xffffffff);
6005

6006 6007 6008 6009
	bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
	bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
6010

6011
	bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
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	if (CHIP_IS_E1H(bp)) {
		REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
		REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
	}

	if (CHIP_REV_IS_SLOW(bp))
		msleep(200);

	/* finish CFC init */
	val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
	if (val != 1) {
		BNX2X_ERR("CFC LL_INIT failed\n");
		return -EBUSY;
	}
	val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
	if (val != 1) {
		BNX2X_ERR("CFC AC_INIT failed\n");
		return -EBUSY;
	}
	val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
	if (val != 1) {
		BNX2X_ERR("CFC CAM_INIT failed\n");
		return -EBUSY;
	}
	REG_WR(bp, CFC_REG_DEBUG0, 0);
6037

6038 6039 6040 6041 6042 6043 6044 6045 6046 6047 6048
	/* read NIG statistic
	   to see if this is our first up since powerup */
	bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
	val = *bnx2x_sp(bp, wb_data[0]);

	/* do internal memory self test */
	if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
		BNX2X_ERR("internal mem self test failed\n");
		return -EBUSY;
	}

6049
	switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
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	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6053
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
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		bp->port.need_hw_lock = 1;
		break;

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	default:
		break;
	}
6060

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6061 6062
	bnx2x_setup_fan_failure_detection(bp);

6063 6064
	/* clear PXP2 attentions */
	REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6065

6066
	enable_blocks_attention(bp);
6067

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	if (!BP_NOMCP(bp)) {
		bnx2x_acquire_phy_lock(bp);
		bnx2x_common_init_phy(bp, bp->common.shmem_base);
		bnx2x_release_phy_lock(bp);
	} else
		BNX2X_ERR("Bootcode is missing - can not initialize link\n");

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	return 0;
}
6077

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static int bnx2x_init_port(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
6081
	int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
6082
	u32 low, high;
6083
	u32 val;
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	DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);

	REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6088

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	bnx2x_init_block(bp, PXP_BLOCK, init_stage);
	bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
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	bnx2x_init_block(bp, TCM_BLOCK, init_stage);
	bnx2x_init_block(bp, UCM_BLOCK, init_stage);
	bnx2x_init_block(bp, CCM_BLOCK, init_stage);
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#ifdef BCM_ISCSI
	/* Port0  1
	 * Port1  385 */
	i++;
	wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
	wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
	REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
	REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));

	/* Port0  2
	 * Port1  386 */
	i++;
	wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
	wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
	REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
	REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));

	/* Port0  3
	 * Port1  387 */
	i++;
	wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
	wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
	REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
	REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
#endif
6120
	bnx2x_init_block(bp, XCM_BLOCK, init_stage);
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#ifdef BCM_ISCSI
	REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
	REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);

6126
	bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
6127
#endif
6128
	bnx2x_init_block(bp, DQ_BLOCK, init_stage);
6129

6130
	bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
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	if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
		/* no pause for emulation and FPGA */
		low = 0;
		high = 513;
	} else {
		if (IS_E1HMF(bp))
			low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
		else if (bp->dev->mtu > 4096) {
			if (bp->flags & ONE_PORT_FLAG)
				low = 160;
			else {
				val = bp->dev->mtu;
				/* (24*1024 + val*4)/256 */
				low = 96 + (val/64) + ((val % 64) ? 1 : 0);
			}
		} else
			low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
		high = low + 56;	/* 14*1024/256 */
	}
	REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
	REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);


6154
	bnx2x_init_block(bp, PRS_BLOCK, init_stage);
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6156 6157 6158 6159
	bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
	bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
	bnx2x_init_block(bp, USDM_BLOCK, init_stage);
	bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
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6161 6162 6163 6164
	bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
	bnx2x_init_block(bp, USEM_BLOCK, init_stage);
	bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
	bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
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6166 6167
	bnx2x_init_block(bp, UPB_BLOCK, init_stage);
	bnx2x_init_block(bp, XPB_BLOCK, init_stage);
6168

6169
	bnx2x_init_block(bp, PBF_BLOCK, init_stage);
6170 6171

	/* configure PBF to work without PAUSE mtu 9000 */
6172
	REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6173 6174

	/* update threshold */
6175
	REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6176
	/* update init credit */
6177
	REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
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	/* probe changes */
6180
	REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6181
	msleep(5);
6182
	REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
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#ifdef BCM_ISCSI
	/* tell the searcher where the T2 table is */
	REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);

	wb_write[0] = U64_LO(bp->t2_mapping);
	wb_write[1] = U64_HI(bp->t2_mapping);
	REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
	wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
	wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
	REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);

	REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
#endif
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	bnx2x_init_block(bp, CDU_BLOCK, init_stage);
	bnx2x_init_block(bp, CFC_BLOCK, init_stage);
6199 6200 6201 6202 6203

	if (CHIP_IS_E1(bp)) {
		REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
		REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
	}
6204
	bnx2x_init_block(bp, HC_BLOCK, init_stage);
6205

6206
	bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
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	/* init aeu_mask_attn_func_0/1:
	 *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
	 *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
	 *             bits 4-7 are used for "per vn group attention" */
	REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
	       (IS_E1HMF(bp) ? 0xF7 : 0x7));

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	bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
	bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
	bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
	bnx2x_init_block(bp, DBU_BLOCK, init_stage);
	bnx2x_init_block(bp, DBG_BLOCK, init_stage);
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6220
	bnx2x_init_block(bp, NIG_BLOCK, init_stage);
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	REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);

	if (CHIP_IS_E1H(bp)) {
		/* 0x2 disable e1hov, 0x1 enable */
		REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
		       (IS_E1HMF(bp) ? 0x1 : 0x2));

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		/* support pause requests from USDM, TSDM and BRB */
		REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 + port*4, 0x7);

		{
			REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
			REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
			REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
		}
6237 6238
	}

6239 6240
	bnx2x_init_block(bp, MCP_BLOCK, init_stage);
	bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
6241

6242
	switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
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	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		{
		u32 swap_val, swap_override, aeu_gpio_mask, offset;

		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
			       MISC_REGISTERS_GPIO_INPUT_HI_Z, port);

		/* The GPIO should be swapped if the swap register is
		   set and active */
		swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
		swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);

		/* Select function upon port-swap configuration */
		if (port == 0) {
			offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
			aeu_gpio_mask = (swap_val && swap_override) ?
				AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
				AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
		} else {
			offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
			aeu_gpio_mask = (swap_val && swap_override) ?
				AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
				AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
		}
		val = REG_RD(bp, offset);
		/* add GPIO3 to group */
		val |= aeu_gpio_mask;
		REG_WR(bp, offset, val);
		}
		break;

6274
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6275
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6276
		/* add SPIO 5 to group 0 */
6277 6278 6279 6280
		{
		u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
				       MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
		val = REG_RD(bp, reg_addr);
6281
		val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6282 6283
		REG_WR(bp, reg_addr, val);
		}
6284 6285 6286 6287 6288 6289
		break;

	default:
		break;
	}

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	bnx2x__link_reset(bp);
6291

6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324
	return 0;
}

#define ILT_PER_FUNC		(768/2)
#define FUNC_ILT_BASE(func)	(func * ILT_PER_FUNC)
/* the phys address is shifted right 12 bits and has an added
   1=valid bit added to the 53rd bit
   then since this is a wide register(TM)
   we split it into two 32 bit writes
 */
#define ONCHIP_ADDR1(x)		((u32)(((u64)x >> 12) & 0xFFFFFFFF))
#define ONCHIP_ADDR2(x)		((u32)((1 << 20) | ((u64)x >> 44)))
#define PXP_ONE_ILT(x)		(((x) << 10) | x)
#define PXP_ILT_RANGE(f, l)	(((l) << 10) | f)

#define CNIC_ILT_LINES		0

static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
{
	int reg;

	if (CHIP_IS_E1H(bp))
		reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
	else /* E1 */
		reg = PXP2_REG_RQ_ONCHIP_AT + index*8;

	bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
}

static int bnx2x_init_func(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
	int func = BP_FUNC(bp);
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	u32 addr, val;
6326 6327 6328 6329
	int i;

	DP(BNX2X_MSG_MCP, "starting func init  func %x\n", func);

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	/* set MSI reconfigure capability */
	addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
	val = REG_RD(bp, addr);
	val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
	REG_WR(bp, addr, val);

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	i = FUNC_ILT_BASE(func);

	bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
	if (CHIP_IS_E1H(bp)) {
		REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
		REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
	} else /* E1 */
		REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
		       PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));


	if (CHIP_IS_E1H(bp)) {
		for (i = 0; i < 9; i++)
			bnx2x_init_block(bp,
6350
					 cm_blocks[i], FUNC0_STAGE + func);
6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362

		REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
		REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
	}

	/* HC init per function */
	if (CHIP_IS_E1H(bp)) {
		REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);

		REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
		REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
	}
6363
	bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
6364

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6365
	/* Reset PCIE errors for debug */
6366 6367 6368
	REG_WR(bp, 0x2114, 0xffffffff);
	REG_WR(bp, 0x2120, 0xffffffff);

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	return 0;
}

static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
{
	int i, rc = 0;
6375

6376 6377
	DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
	   BP_FUNC(bp), load_code);
6378

6379 6380 6381
	bp->dmae_ready = 0;
	mutex_init(&bp->dmae_mutex);
	bnx2x_gunzip_init(bp);
6382

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	switch (load_code) {
	case FW_MSG_CODE_DRV_LOAD_COMMON:
		rc = bnx2x_init_common(bp);
		if (rc)
			goto init_hw_err;
		/* no break */

	case FW_MSG_CODE_DRV_LOAD_PORT:
		bp->dmae_ready = 1;
		rc = bnx2x_init_port(bp);
		if (rc)
			goto init_hw_err;
		/* no break */

	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
		bp->dmae_ready = 1;
		rc = bnx2x_init_func(bp);
		if (rc)
			goto init_hw_err;
		break;

	default:
		BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
		break;
	}

	if (!BP_NOMCP(bp)) {
		int func = BP_FUNC(bp);
6411 6412

		bp->fw_drv_pulse_wr_seq =
6413
				(SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
6414
				 DRV_PULSE_SEQ_MASK);
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		bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
		DP(BNX2X_MSG_MCP, "drv_pulse 0x%x  func_stx 0x%x\n",
		   bp->fw_drv_pulse_wr_seq, bp->func_stx);
	} else
		bp->func_stx = 0;
6420

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	/* this needs to be done before gunzip end */
	bnx2x_zero_def_sb(bp);
	for_each_queue(bp, i)
		bnx2x_zero_sb(bp, BP_L_ID(bp) + i);

init_hw_err:
	bnx2x_gunzip_end(bp);

	return rc;
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}

static void bnx2x_free_mem(struct bnx2x *bp)
{

#define BNX2X_PCI_FREE(x, y, size) \
	do { \
		if (x) { \
			pci_free_consistent(bp->pdev, size, x, y); \
			x = NULL; \
			y = 0; \
		} \
	} while (0)

#define BNX2X_FREE(x) \
	do { \
		if (x) { \
			vfree(x); \
			x = NULL; \
		} \
	} while (0)

	int i;

	/* fastpath */
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	/* Common */
6456 6457
	for_each_queue(bp, i) {

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		/* status blocks */
6459 6460
		BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
			       bnx2x_fp(bp, i, status_blk_mapping),
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			       sizeof(struct host_status_block));
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	}
	/* Rx */
	for_each_rx_queue(bp, i) {
6465

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		/* fastpath rx rings: rx_buf rx_desc rx_comp */
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		BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
		BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
			       bnx2x_fp(bp, i, rx_desc_mapping),
			       sizeof(struct eth_rx_bd) * NUM_RX_BD);

		BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
			       bnx2x_fp(bp, i, rx_comp_mapping),
			       sizeof(struct eth_fast_path_rx_cqe) *
			       NUM_RCQ_BD);

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		/* SGE ring */
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		BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
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		BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
			       bnx2x_fp(bp, i, rx_sge_mapping),
			       BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
	}
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	/* Tx */
	for_each_tx_queue(bp, i) {

		/* fastpath tx rings: tx_buf tx_desc */
		BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
		BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
			       bnx2x_fp(bp, i, tx_desc_mapping),
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			       sizeof(union eth_tx_bd_types) * NUM_TX_BD);
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	}
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	/* end of fastpath */

	BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
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		       sizeof(struct host_def_status_block));
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	BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
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		       sizeof(struct bnx2x_slowpath));
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#ifdef BCM_ISCSI
	BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
	BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
	BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
	BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
#endif
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	BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
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#undef BNX2X_PCI_FREE
#undef BNX2X_KFREE
}

static int bnx2x_alloc_mem(struct bnx2x *bp)
{

#define BNX2X_PCI_ALLOC(x, y, size) \
	do { \
		x = pci_alloc_consistent(bp->pdev, size, y); \
		if (x == NULL) \
			goto alloc_mem_err; \
		memset(x, 0, size); \
	} while (0)

#define BNX2X_ALLOC(x, size) \
	do { \
		x = vmalloc(size); \
		if (x == NULL) \
			goto alloc_mem_err; \
		memset(x, 0, size); \
	} while (0)

	int i;

	/* fastpath */
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	/* Common */
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	for_each_queue(bp, i) {
		bnx2x_fp(bp, i, bp) = bp;

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		/* status blocks */
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		BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
				&bnx2x_fp(bp, i, status_blk_mapping),
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				sizeof(struct host_status_block));
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	}
	/* Rx */
	for_each_rx_queue(bp, i) {
6545

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		/* fastpath rx rings: rx_buf rx_desc rx_comp */
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		BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
				sizeof(struct sw_rx_bd) * NUM_RX_BD);
		BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
				&bnx2x_fp(bp, i, rx_desc_mapping),
				sizeof(struct eth_rx_bd) * NUM_RX_BD);

		BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
				&bnx2x_fp(bp, i, rx_comp_mapping),
				sizeof(struct eth_fast_path_rx_cqe) *
				NUM_RCQ_BD);

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		/* SGE ring */
		BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
				sizeof(struct sw_rx_page) * NUM_RX_SGE);
		BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
				&bnx2x_fp(bp, i, rx_sge_mapping),
				BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
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	}
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	/* Tx */
	for_each_tx_queue(bp, i) {

		/* fastpath tx rings: tx_buf tx_desc */
		BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
				sizeof(struct sw_tx_bd) * NUM_TX_BD);
		BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
				&bnx2x_fp(bp, i, tx_desc_mapping),
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				sizeof(union eth_tx_bd_types) * NUM_TX_BD);
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	}
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	/* end of fastpath */

	BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
			sizeof(struct host_def_status_block));

	BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
			sizeof(struct bnx2x_slowpath));

#ifdef BCM_ISCSI
	BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);

	/* Initialize T1 */
	for (i = 0; i < 64*1024; i += 64) {
		*(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
		*(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
	}

	/* allocate searcher T2 table
	   we allocate 1/4 of alloc num for T2
	  (which is not entered into the ILT) */
	BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);

	/* Initialize T2 */
	for (i = 0; i < 16*1024; i += 64)
		* (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;

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	/* now fixup the last line in the block to point to the next block */
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	*(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;

	/* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
	BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);

	/* QM queues (128*MAX_CONN) */
	BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
#endif

	/* Slow path ring */
	BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);

	return 0;

alloc_mem_err:
	bnx2x_free_mem(bp);
	return -ENOMEM;

#undef BNX2X_PCI_ALLOC
#undef BNX2X_ALLOC
}

static void bnx2x_free_tx_skbs(struct bnx2x *bp)
{
	int i;

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	for_each_tx_queue(bp, i) {
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		struct bnx2x_fastpath *fp = &bp->fp[i];

		u16 bd_cons = fp->tx_bd_cons;
		u16 sw_prod = fp->tx_pkt_prod;
		u16 sw_cons = fp->tx_pkt_cons;

		while (sw_cons != sw_prod) {
			bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
			sw_cons++;
		}
	}
}

static void bnx2x_free_rx_skbs(struct bnx2x *bp)
{
	int i, j;

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	for_each_rx_queue(bp, j) {
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		struct bnx2x_fastpath *fp = &bp->fp[j];

		for (i = 0; i < NUM_RX_BD; i++) {
			struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
			struct sk_buff *skb = rx_buf->skb;

			if (skb == NULL)
				continue;

			pci_unmap_single(bp->pdev,
					 pci_unmap_addr(rx_buf, mapping),
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					 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
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			rx_buf->skb = NULL;
			dev_kfree_skb(skb);
		}
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		if (!fp->disable_tpa)
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			bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
					    ETH_MAX_AGGREGATION_QUEUES_E1 :
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					    ETH_MAX_AGGREGATION_QUEUES_E1H);
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	}
}

static void bnx2x_free_skbs(struct bnx2x *bp)
{
	bnx2x_free_tx_skbs(bp);
	bnx2x_free_rx_skbs(bp);
}

static void bnx2x_free_msix_irqs(struct bnx2x *bp)
{
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	int i, offset = 1;
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	free_irq(bp->msix_table[0].vector, bp->dev);
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	DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
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	   bp->msix_table[0].vector);

	for_each_queue(bp, i) {
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		DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq  "
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		   "state %x\n", i, bp->msix_table[i + offset].vector,
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		   bnx2x_fp(bp, i, state));

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		free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
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	}
}

static void bnx2x_free_irq(struct bnx2x *bp)
{
	if (bp->flags & USING_MSIX_FLAG) {
		bnx2x_free_msix_irqs(bp);
		pci_disable_msix(bp->pdev);
		bp->flags &= ~USING_MSIX_FLAG;

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	} else if (bp->flags & USING_MSI_FLAG) {
		free_irq(bp->pdev->irq, bp->dev);
		pci_disable_msi(bp->pdev);
		bp->flags &= ~USING_MSI_FLAG;

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	} else
		free_irq(bp->pdev->irq, bp->dev);
}

static int bnx2x_enable_msix(struct bnx2x *bp)
{
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	int i, rc, offset = 1;
	int igu_vec = 0;
6713

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	bp->msix_table[0].entry = igu_vec;
	DP(NETIF_MSG_IFUP, "msix_table[0].entry = %d (slowpath)\n", igu_vec);
6716

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	for_each_queue(bp, i) {
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		igu_vec = BP_L_ID(bp) + offset + i;
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		bp->msix_table[i + offset].entry = igu_vec;
		DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
		   "(fastpath #%u)\n", i + offset, igu_vec, i);
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	}

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	rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
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			     BNX2X_NUM_QUEUES(bp) + offset);
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	if (rc) {
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		DP(NETIF_MSG_IFUP, "MSI-X is not attainable  rc %d\n", rc);
		return rc;
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	}
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	bp->flags |= USING_MSIX_FLAG;

	return 0;
}

static int bnx2x_req_msix_irqs(struct bnx2x *bp)
{
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	int i, rc, offset = 1;
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	rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
			 bp->dev->name, bp->dev);
	if (rc) {
		BNX2X_ERR("request sp irq failed\n");
		return -EBUSY;
	}

	for_each_queue(bp, i) {
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		struct bnx2x_fastpath *fp = &bp->fp[i];

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		if (i < bp->num_rx_queues)
			sprintf(fp->name, "%s-rx-%d", bp->dev->name, i);
		else
			sprintf(fp->name, "%s-tx-%d",
				bp->dev->name, i - bp->num_rx_queues);

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		rc = request_irq(bp->msix_table[i + offset].vector,
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				 bnx2x_msix_fp_int, 0, fp->name, fp);
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		if (rc) {
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			BNX2X_ERR("request fp #%d irq failed  rc %d\n", i, rc);
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			bnx2x_free_msix_irqs(bp);
			return -EBUSY;
		}

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		fp->state = BNX2X_FP_STATE_IRQ;
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	}

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	i = BNX2X_NUM_QUEUES(bp);
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	printk(KERN_INFO PFX "%s: using MSI-X  IRQs: sp %d  fp[%d] %d"
	       " ... fp[%d] %d\n",
	       bp->dev->name, bp->msix_table[0].vector,
	       0, bp->msix_table[offset].vector,
	       i - 1, bp->msix_table[offset + i - 1].vector);
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	return 0;
}

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static int bnx2x_enable_msi(struct bnx2x *bp)
{
	int rc;

	rc = pci_enable_msi(bp->pdev);
	if (rc) {
		DP(NETIF_MSG_IFUP, "MSI is not attainable\n");
		return -1;
	}
	bp->flags |= USING_MSI_FLAG;

	return 0;
}

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static int bnx2x_req_irq(struct bnx2x *bp)
{
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	unsigned long flags;
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	int rc;
6795

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	if (bp->flags & USING_MSI_FLAG)
		flags = 0;
	else
		flags = IRQF_SHARED;

	rc = request_irq(bp->pdev->irq, bnx2x_interrupt, flags,
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			 bp->dev->name, bp->dev);
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	if (!rc)
		bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;

	return rc;
}

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static void bnx2x_napi_enable(struct bnx2x *bp)
{
	int i;

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	for_each_rx_queue(bp, i)
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		napi_enable(&bnx2x_fp(bp, i, napi));
}

static void bnx2x_napi_disable(struct bnx2x *bp)
{
	int i;

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	for_each_rx_queue(bp, i)
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		napi_disable(&bnx2x_fp(bp, i, napi));
}

static void bnx2x_netif_start(struct bnx2x *bp)
{
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	int intr_sem;

	intr_sem = atomic_dec_and_test(&bp->intr_sem);
	smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */

	if (intr_sem) {
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		if (netif_running(bp->dev)) {
			bnx2x_napi_enable(bp);
			bnx2x_int_enable(bp);
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			if (bp->state == BNX2X_STATE_OPEN)
				netif_tx_wake_all_queues(bp->dev);
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		}
	}
}

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static void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
6843
{
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	bnx2x_int_disable_sync(bp, disable_hw);
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	bnx2x_napi_disable(bp);
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	netif_tx_disable(bp->dev);
	bp->dev->trans_start = jiffies;	/* prevent tx timeout */
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}

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/*
 * Init service functions
 */

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static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
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{
	struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
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	int port = BP_PORT(bp);
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	/* CAM allocation
	 * unicasts 0-31:port0 32-63:port1
	 * multicast 64-127:port0 128-191:port1
	 */
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	config->hdr.length = 2;
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	config->hdr.offset = port ? 32 : 0;
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	config->hdr.client_id = bp->fp->cl_id;
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	config->hdr.reserved1 = 0;

	/* primary MAC */
	config->config_table[0].cam_entry.msb_mac_addr =
					swab16(*(u16 *)&bp->dev->dev_addr[0]);
	config->config_table[0].cam_entry.middle_mac_addr =
					swab16(*(u16 *)&bp->dev->dev_addr[2]);
	config->config_table[0].cam_entry.lsb_mac_addr =
					swab16(*(u16 *)&bp->dev->dev_addr[4]);
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	config->config_table[0].cam_entry.flags = cpu_to_le16(port);
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	if (set)
		config->config_table[0].target_table_entry.flags = 0;
	else
		CAM_INVALIDATE(config->config_table[0]);
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	config->config_table[0].target_table_entry.clients_bit_vector =
						cpu_to_le32(1 << BP_L_ID(bp));
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	config->config_table[0].target_table_entry.vlan_id = 0;

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	DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
	   (set ? "setting" : "clearing"),
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	   config->config_table[0].cam_entry.msb_mac_addr,
	   config->config_table[0].cam_entry.middle_mac_addr,
	   config->config_table[0].cam_entry.lsb_mac_addr);

	/* broadcast */
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	config->config_table[1].cam_entry.msb_mac_addr = cpu_to_le16(0xffff);
	config->config_table[1].cam_entry.middle_mac_addr = cpu_to_le16(0xffff);
	config->config_table[1].cam_entry.lsb_mac_addr = cpu_to_le16(0xffff);
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	config->config_table[1].cam_entry.flags = cpu_to_le16(port);
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	if (set)
		config->config_table[1].target_table_entry.flags =
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				TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
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	else
		CAM_INVALIDATE(config->config_table[1]);
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	config->config_table[1].target_table_entry.clients_bit_vector =
						cpu_to_le32(1 << BP_L_ID(bp));
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	config->config_table[1].target_table_entry.vlan_id = 0;

	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
		      U64_HI(bnx2x_sp_mapping(bp, mac_config)),
		      U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
}

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static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
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{
	struct mac_configuration_cmd_e1h *config =
		(struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);

	/* CAM allocation for E1H
	 * unicasts: by func number
	 * multicast: 20+FUNC*20, 20 each
	 */
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	config->hdr.length = 1;
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	config->hdr.offset = BP_FUNC(bp);
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	config->hdr.client_id = bp->fp->cl_id;
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	config->hdr.reserved1 = 0;

	/* primary MAC */
	config->config_table[0].msb_mac_addr =
					swab16(*(u16 *)&bp->dev->dev_addr[0]);
	config->config_table[0].middle_mac_addr =
					swab16(*(u16 *)&bp->dev->dev_addr[2]);
	config->config_table[0].lsb_mac_addr =
					swab16(*(u16 *)&bp->dev->dev_addr[4]);
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	config->config_table[0].clients_bit_vector =
					cpu_to_le32(1 << BP_L_ID(bp));
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	config->config_table[0].vlan_id = 0;
	config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
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	if (set)
		config->config_table[0].flags = BP_PORT(bp);
	else
		config->config_table[0].flags =
				MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
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	DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)  E1HOV %d  CLID %d\n",
	   (set ? "setting" : "clearing"),
6942 6943 6944 6945 6946 6947 6948 6949 6950
	   config->config_table[0].msb_mac_addr,
	   config->config_table[0].middle_mac_addr,
	   config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));

	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
		      U64_HI(bnx2x_sp_mapping(bp, mac_config)),
		      U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
}

6951 6952 6953 6954
static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
			     int *state_p, int poll)
{
	/* can take a while if any port is running */
6955
	int cnt = 5000;
6956

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6957 6958
	DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
	   poll ? "polling" : "waiting", state, idx);
6959 6960

	might_sleep();
6961
	while (cnt--) {
6962 6963
		if (poll) {
			bnx2x_rx_int(bp->fp, 10);
6964 6965
			/* if index is different from 0
			 * the reply for some commands will
6966
			 * be on the non default queue
6967 6968 6969 6970 6971
			 */
			if (idx)
				bnx2x_rx_int(&bp->fp[idx], 10);
		}

6972
		mb(); /* state is changed by bnx2x_sp_event() */
6973 6974 6975 6976
		if (*state_p == state) {
#ifdef BNX2X_STOP_ON_ERROR
			DP(NETIF_MSG_IFUP, "exit  (cnt %d)\n", 5000 - cnt);
#endif
6977
			return 0;
6978
		}
6979 6980 6981 6982 6983

		msleep(1);
	}

	/* timeout! */
6984 6985
	BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
		  poll ? "polling" : "waiting", state, idx);
6986 6987 6988
#ifdef BNX2X_STOP_ON_ERROR
	bnx2x_panic();
#endif
6989

6990
	return -EBUSY;
6991 6992 6993 6994
}

static int bnx2x_setup_leading(struct bnx2x *bp)
{
6995
	int rc;
6996

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6997
	/* reset IGU state */
6998
	bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6999 7000 7001 7002

	/* SETUP ramrod */
	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);

7003 7004
	/* Wait for completion */
	rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
7005

7006
	return rc;
7007 7008 7009 7010
}

static int bnx2x_setup_multi(struct bnx2x *bp, int index)
{
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	struct bnx2x_fastpath *fp = &bp->fp[index];

7013
	/* reset IGU state */
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7014
	bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
7015

7016
	/* SETUP ramrod */
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7017 7018 7019
	fp->state = BNX2X_FP_STATE_OPENING;
	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0,
		      fp->cl_id, 0);
7020 7021 7022

	/* Wait for completion */
	return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
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7023
				 &(fp->state), 0);
7024 7025 7026 7027
}

static int bnx2x_poll(struct napi_struct *napi, int budget);

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static void bnx2x_set_int_mode_msix(struct bnx2x *bp, int *num_rx_queues_out,
				    int *num_tx_queues_out)
{
	int _num_rx_queues = 0, _num_tx_queues = 0;

	switch (bp->multi_mode) {
	case ETH_RSS_MODE_DISABLED:
		_num_rx_queues = 1;
		_num_tx_queues = 1;
		break;

	case ETH_RSS_MODE_REGULAR:
		if (num_rx_queues)
			_num_rx_queues = min_t(u32, num_rx_queues,
					       BNX2X_MAX_QUEUES(bp));
		else
			_num_rx_queues = min_t(u32, num_online_cpus(),
					       BNX2X_MAX_QUEUES(bp));

		if (num_tx_queues)
			_num_tx_queues = min_t(u32, num_tx_queues,
					       BNX2X_MAX_QUEUES(bp));
		else
			_num_tx_queues = min_t(u32, num_online_cpus(),
					       BNX2X_MAX_QUEUES(bp));

		/* There must be not more Tx queues than Rx queues */
		if (_num_tx_queues > _num_rx_queues) {
			BNX2X_ERR("number of tx queues (%d) > "
				  "number of rx queues (%d)"
				  "  defaulting to %d\n",
				  _num_tx_queues, _num_rx_queues,
				  _num_rx_queues);
			_num_tx_queues = _num_rx_queues;
		}
		break;


	default:
		_num_rx_queues = 1;
		_num_tx_queues = 1;
		break;
	}

	*num_rx_queues_out = _num_rx_queues;
	*num_tx_queues_out = _num_tx_queues;
}

static int bnx2x_set_int_mode(struct bnx2x *bp)
7077
{
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7078
	int rc = 0;
7079

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7080 7081 7082
	switch (int_mode) {
	case INT_MODE_INTx:
	case INT_MODE_MSI:
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7083 7084 7085
		bp->num_rx_queues = 1;
		bp->num_tx_queues = 1;
		DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
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7086 7087 7088 7089
		break;

	case INT_MODE_MSIX:
	default:
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7090 7091 7092 7093 7094
		/* Set interrupt mode according to bp->multi_mode value */
		bnx2x_set_int_mode_msix(bp, &bp->num_rx_queues,
					&bp->num_tx_queues);

		DP(NETIF_MSG_IFUP, "set number of queues to: rx %d tx %d\n",
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7095
		   bp->num_rx_queues, bp->num_tx_queues);
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7096

7097 7098 7099 7100
		/* if we can't use MSI-X we only need one fp,
		 * so try to enable MSI-X with the requested number of fp's
		 * and fallback to MSI or legacy INTx with one fp
		 */
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7101 7102
		rc = bnx2x_enable_msix(bp);
		if (rc) {
7103
			/* failed to enable MSI-X */
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7104 7105
			if (bp->multi_mode)
				BNX2X_ERR("Multi requested but failed to "
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7106 7107 7108 7109 7110
					  "enable MSI-X (rx %d tx %d), "
					  "set number of queues to 1\n",
					  bp->num_rx_queues, bp->num_tx_queues);
			bp->num_rx_queues = 1;
			bp->num_tx_queues = 1;
7111
		}
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7112
		break;
7113
	}
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7114
	bp->dev->real_num_tx_queues = bp->num_tx_queues;
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7115
	return rc;
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7116 7117 7118 7119 7120 7121 7122
}


/* must be called with rtnl_lock */
static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
{
	u32 load_code;
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7123 7124
	int i, rc;

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7125 7126 7127 7128 7129 7130 7131
#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return -EPERM;
#endif

	bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;

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7132
	rc = bnx2x_set_int_mode(bp);
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7133

7134 7135 7136
	if (bnx2x_alloc_mem(bp))
		return -ENOMEM;

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7137
	for_each_rx_queue(bp, i)
7138 7139 7140
		bnx2x_fp(bp, i, disable_tpa) =
					((bp->flags & TPA_ENABLE_FLAG) == 0);

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7141
	for_each_rx_queue(bp, i)
7142 7143 7144 7145 7146
		netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
			       bnx2x_poll, 128);

	bnx2x_napi_enable(bp);

7147 7148 7149 7150
	if (bp->flags & USING_MSIX_FLAG) {
		rc = bnx2x_req_msix_irqs(bp);
		if (rc) {
			pci_disable_msix(bp->pdev);
7151
			goto load_error1;
7152 7153
		}
	} else {
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7154 7155
		/* Fall to INTx if failed to enable MSI-X due to lack of
		   memory (in bnx2x_set_int_mode()) */
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7156 7157
		if ((rc != -ENOMEM) && (int_mode != INT_MODE_INTx))
			bnx2x_enable_msi(bp);
7158 7159 7160
		bnx2x_ack_int(bp);
		rc = bnx2x_req_irq(bp);
		if (rc) {
7161
			BNX2X_ERR("IRQ request failed  rc %d, aborting\n", rc);
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7162 7163
			if (bp->flags & USING_MSI_FLAG)
				pci_disable_msi(bp->pdev);
7164
			goto load_error1;
7165
		}
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7166 7167 7168 7169 7170
		if (bp->flags & USING_MSI_FLAG) {
			bp->dev->irq = bp->pdev->irq;
			printk(KERN_INFO PFX "%s: using MSI  IRQ %d\n",
			       bp->dev->name, bp->pdev->irq);
		}
7171 7172
	}

7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192
	/* Send LOAD_REQUEST command to MCP
	   Returns the type of LOAD command:
	   if it is the first port to be initialized
	   common blocks should be initialized, otherwise - not
	*/
	if (!BP_NOMCP(bp)) {
		load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
		if (!load_code) {
			BNX2X_ERR("MCP response failure, aborting\n");
			rc = -EBUSY;
			goto load_error2;
		}
		if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) {
			rc = -EBUSY; /* other port in diagnostic mode */
			goto load_error2;
		}

	} else {
		int port = BP_PORT(bp);

7193
		DP(NETIF_MSG_IFUP, "NO MCP - load counts      %d, %d, %d\n",
7194 7195 7196
		   load_count[0], load_count[1], load_count[2]);
		load_count[0]++;
		load_count[1 + port]++;
7197
		DP(NETIF_MSG_IFUP, "NO MCP - new load counts  %d, %d, %d\n",
7198 7199 7200 7201 7202 7203 7204 7205 7206 7207 7208 7209 7210 7211 7212
		   load_count[0], load_count[1], load_count[2]);
		if (load_count[0] == 1)
			load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
		else if (load_count[1 + port] == 1)
			load_code = FW_MSG_CODE_DRV_LOAD_PORT;
		else
			load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
	}

	if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
	    (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
		bp->port.pmf = 1;
	else
		bp->port.pmf = 0;
	DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
7213 7214

	/* Initialize HW */
7215 7216
	rc = bnx2x_init_hw(bp, load_code);
	if (rc) {
7217
		BNX2X_ERR("HW init failed, aborting\n");
7218
		goto load_error2;
7219 7220 7221
	}

	/* Setup NIC internals and enable interrupts */
7222
	bnx2x_nic_init(bp, load_code);
7223

7224 7225 7226 7227 7228 7229
	if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) &&
	    (bp->common.shmem2_base))
		SHMEM2_WR(bp, dcc_support,
			  (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
			   SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));

7230
	/* Send LOAD_DONE command to MCP */
7231
	if (!BP_NOMCP(bp)) {
7232 7233
		load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
		if (!load_code) {
7234
			BNX2X_ERR("MCP response failure, aborting\n");
7235
			rc = -EBUSY;
7236
			goto load_error3;
7237 7238 7239 7240 7241
		}
	}

	bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;

7242 7243
	rc = bnx2x_setup_leading(bp);
	if (rc) {
7244
		BNX2X_ERR("Setup leading failed!\n");
7245
		goto load_error3;
7246
	}
7247

7248 7249
	if (CHIP_IS_E1H(bp))
		if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
7250
			DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
7251 7252
			bp->state = BNX2X_STATE_DISABLED;
		}
7253

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7254
	if (bp->state == BNX2X_STATE_OPEN) {
7255 7256 7257
		for_each_nondefault_queue(bp, i) {
			rc = bnx2x_setup_multi(bp, i);
			if (rc)
7258
				goto load_error3;
7259
		}
7260

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7261 7262 7263 7264 7265
		if (CHIP_IS_E1(bp))
			bnx2x_set_mac_addr_e1(bp, 1);
		else
			bnx2x_set_mac_addr_e1h(bp, 1);
	}
7266 7267

	if (bp->port.pmf)
7268
		bnx2x_initial_phy_init(bp, load_mode);
7269 7270

	/* Start fast path */
7271 7272
	switch (load_mode) {
	case LOAD_NORMAL:
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7273 7274 7275 7276
		if (bp->state == BNX2X_STATE_OPEN) {
			/* Tx queue should be only reenabled */
			netif_tx_wake_all_queues(bp->dev);
		}
7277
		/* Initialize the receive filter. */
7278 7279 7280 7281
		bnx2x_set_rx_mode(bp->dev);
		break;

	case LOAD_OPEN:
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7282
		netif_tx_start_all_queues(bp->dev);
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7283 7284
		if (bp->state != BNX2X_STATE_OPEN)
			netif_tx_disable(bp->dev);
7285
		/* Initialize the receive filter. */
7286 7287
		bnx2x_set_rx_mode(bp->dev);
		break;
7288

7289
	case LOAD_DIAG:
7290
		/* Initialize the receive filter. */
7291
		bnx2x_set_rx_mode(bp->dev);
7292 7293 7294 7295 7296
		bp->state = BNX2X_STATE_DIAG;
		break;

	default:
		break;
7297 7298
	}

7299 7300 7301
	if (!bp->port.pmf)
		bnx2x__link_status_update(bp);

7302 7303 7304
	/* start the timer */
	mod_timer(&bp->timer, jiffies + bp->current_interval);

7305

7306 7307
	return 0;

7308 7309 7310 7311 7312 7313 7314
load_error3:
	bnx2x_int_disable_sync(bp, 1);
	if (!BP_NOMCP(bp)) {
		bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
		bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
	}
	bp->port.pmf = 0;
7315 7316
	/* Free SKBs, SGEs, TPA pool and driver internals */
	bnx2x_free_skbs(bp);
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7317
	for_each_rx_queue(bp, i)
7318
		bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
7319
load_error2:
7320 7321
	/* Release IRQs */
	bnx2x_free_irq(bp);
7322 7323
load_error1:
	bnx2x_napi_disable(bp);
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7324
	for_each_rx_queue(bp, i)
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7325
		netif_napi_del(&bnx2x_fp(bp, i, napi));
7326 7327
	bnx2x_free_mem(bp);

7328
	return rc;
7329 7330 7331 7332
}

static int bnx2x_stop_multi(struct bnx2x *bp, int index)
{
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7333
	struct bnx2x_fastpath *fp = &bp->fp[index];
7334 7335
	int rc;

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7336
	/* halt the connection */
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7337 7338
	fp->state = BNX2X_FP_STATE_HALTING;
	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0);
7339

7340
	/* Wait for completion */
7341
	rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
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7342
			       &(fp->state), 1);
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7343
	if (rc) /* timeout */
7344 7345 7346 7347 7348
		return rc;

	/* delete cfc entry */
	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);

7349 7350
	/* Wait for completion */
	rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
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7351
			       &(fp->state), 1);
7352
	return rc;
7353 7354
}

7355
static int bnx2x_stop_leading(struct bnx2x *bp)
7356
{
7357
	__le16 dsb_sp_prod_idx;
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7358
	/* if the other port is handling traffic,
7359
	   this can take a lot of time */
7360 7361
	int cnt = 500;
	int rc;
7362 7363 7364 7365 7366

	might_sleep();

	/* Send HALT ramrod */
	bp->fp[0].state = BNX2X_FP_STATE_HALTING;
7367
	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, bp->fp->cl_id, 0);
7368

7369 7370 7371 7372
	/* Wait for completion */
	rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
			       &(bp->fp[0].state), 1);
	if (rc) /* timeout */
7373
		return rc;
7374

7375
	dsb_sp_prod_idx = *bp->dsb_sp_prod;
7376

7377
	/* Send PORT_DELETE ramrod */
7378 7379
	bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);

7380
	/* Wait for completion to arrive on default status block
7381 7382 7383
	   we are going to reset the chip anyway
	   so there is not much to do if this times out
	 */
7384 7385 7386 7387 7388 7389 7390 7391
	while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
		if (!cnt) {
			DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
			   "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
			   *bp->dsb_sp_prod, dsb_sp_prod_idx);
#ifdef BNX2X_STOP_ON_ERROR
			bnx2x_panic();
#endif
7392
			rc = -EBUSY;
7393 7394 7395
			break;
		}
		cnt--;
7396
		msleep(1);
7397
		rmb(); /* Refresh the dsb_sp_prod */
7398 7399 7400
	}
	bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
	bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
7401 7402

	return rc;
7403 7404
}

7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434 7435 7436 7437 7438 7439 7440 7441
static void bnx2x_reset_func(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
	int func = BP_FUNC(bp);
	int base, i;

	/* Configure IGU */
	REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
	REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);

	/* Clear ILT */
	base = FUNC_ILT_BASE(func);
	for (i = base; i < base + ILT_PER_FUNC; i++)
		bnx2x_ilt_wr(bp, i, 0);
}

static void bnx2x_reset_port(struct bnx2x *bp)
{
	int port = BP_PORT(bp);
	u32 val;

	REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);

	/* Do not rcv packets to BRB */
	REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
	/* Do not direct rcv packets that are not for MCP to the BRB */
	REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
			   NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);

	/* Configure AEU */
	REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);

	msleep(100);
	/* Check for BRB port occupancy */
	val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
	if (val)
		DP(NETIF_MSG_IFDOWN,
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		   "BRB1 is not empty  %d blocks are occupied\n", val);
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	/* TODO: Close Doorbell port? */
}

static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
{
	DP(BNX2X_MSG_MCP, "function %d  reset_code %x\n",
	   BP_FUNC(bp), reset_code);

	switch (reset_code) {
	case FW_MSG_CODE_DRV_UNLOAD_COMMON:
		bnx2x_reset_port(bp);
		bnx2x_reset_func(bp);
		bnx2x_reset_common(bp);
		break;

	case FW_MSG_CODE_DRV_UNLOAD_PORT:
		bnx2x_reset_port(bp);
		bnx2x_reset_func(bp);
		break;

	case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
		bnx2x_reset_func(bp);
		break;
7467

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	default:
		BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
		break;
	}
}

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/* must be called with rtnl_lock */
7475
static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
7476
{
7477
	int port = BP_PORT(bp);
7478
	u32 reset_code = 0;
7479
	int i, cnt, rc;
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	bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;

7483 7484
	bp->rx_mode = BNX2X_RX_MODE_NONE;
	bnx2x_set_storm_rx_mode(bp);
7485

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	bnx2x_netif_stop(bp, 1);
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	del_timer_sync(&bp->timer);
	SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb,
		 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
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	bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7492

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	/* Release IRQs */
	bnx2x_free_irq(bp);

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	/* Wait until tx fastpath tasks complete */
	for_each_tx_queue(bp, i) {
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		struct bnx2x_fastpath *fp = &bp->fp[i];

7500
		cnt = 1000;
7501
		while (bnx2x_has_tx_work_unload(fp)) {
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7503
			bnx2x_tx_int(fp);
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			if (!cnt) {
				BNX2X_ERR("timeout waiting for queue[%d]\n",
					  i);
#ifdef BNX2X_STOP_ON_ERROR
				bnx2x_panic();
				return -EBUSY;
#else
				break;
#endif
			}
			cnt--;
7515
			msleep(1);
7516
		}
7517
	}
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	/* Give HW time to discard old tx messages */
	msleep(1);
7520

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	if (CHIP_IS_E1(bp)) {
		struct mac_configuration_cmd *config =
						bnx2x_sp(bp, mcast_config);

		bnx2x_set_mac_addr_e1(bp, 0);

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		for (i = 0; i < config->hdr.length; i++)
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			CAM_INVALIDATE(config->config_table[i]);

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		config->hdr.length = i;
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		if (CHIP_REV_IS_SLOW(bp))
			config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
		else
			config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
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		config->hdr.client_id = bp->fp->cl_id;
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		config->hdr.reserved1 = 0;

		bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
			      U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
			      U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);

	} else { /* E1H */
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		REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);

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		bnx2x_set_mac_addr_e1h(bp, 0);

		for (i = 0; i < MC_HASH_SIZE; i++)
			REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
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		REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
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	}

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	if (unload_mode == UNLOAD_NORMAL)
		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;

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	else if (bp->flags & NO_WOL_FLAG)
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		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;

7559
	else if (bp->wol) {
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		u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
		u8 *mac_addr = bp->dev->dev_addr;
		u32 val;
		/* The mac address is written to entries 1-4 to
		   preserve entry 0 which is used by the PMF */
		u8 entry = (BP_E1HVN(bp) + 1)*8;

		val = (mac_addr[0] << 8) | mac_addr[1];
		EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);

		val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
		      (mac_addr[4] << 8) | mac_addr[5];
		EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);

		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;

	} else
		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
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	/* Close multi and leading connections
	   Completions for ramrods are collected in a synchronous way */
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	for_each_nondefault_queue(bp, i)
		if (bnx2x_stop_multi(bp, i))
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			goto unload_error;
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	rc = bnx2x_stop_leading(bp);
	if (rc) {
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		BNX2X_ERR("Stop leading failed!\n");
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#ifdef BNX2X_STOP_ON_ERROR
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		return -EBUSY;
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#else
		goto unload_error;
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#endif
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	}

unload_error:
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	if (!BP_NOMCP(bp))
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		reset_code = bnx2x_fw_command(bp, reset_code);
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	else {
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		DP(NETIF_MSG_IFDOWN, "NO MCP - load counts      %d, %d, %d\n",
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		   load_count[0], load_count[1], load_count[2]);
		load_count[0]--;
7602
		load_count[1 + port]--;
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		DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts  %d, %d, %d\n",
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		   load_count[0], load_count[1], load_count[2]);
		if (load_count[0] == 0)
			reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
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		else if (load_count[1 + port] == 0)
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			reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
		else
			reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
	}
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	if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
	    (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
		bnx2x__link_reset(bp);
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	/* Reset the chip */
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	bnx2x_reset_chip(bp, reset_code);
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	/* Report UNLOAD_DONE to MCP */
7621
	if (!BP_NOMCP(bp))
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		bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
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7624
	bp->port.pmf = 0;
7625

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	/* Free SKBs, SGEs, TPA pool and driver internals */
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	bnx2x_free_skbs(bp);
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	for_each_rx_queue(bp, i)
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		bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
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	for_each_rx_queue(bp, i)
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		netif_napi_del(&bnx2x_fp(bp, i, napi));
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	bnx2x_free_mem(bp);

	bp->state = BNX2X_STATE_CLOSED;
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	netif_carrier_off(bp->dev);

	return 0;
}

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static void bnx2x_reset_task(struct work_struct *work)
{
	struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);

#ifdef BNX2X_STOP_ON_ERROR
	BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
		  " so reset not done to allow debug dump,\n"
7648
		  " you will need to reboot when done\n");
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	return;
#endif

	rtnl_lock();

	if (!netif_running(bp->dev))
		goto reset_task_exit;

	bnx2x_nic_unload(bp, UNLOAD_NORMAL);
	bnx2x_nic_load(bp, LOAD_NORMAL);

reset_task_exit:
	rtnl_unlock();
}

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/* end of nic load/unload */

/* ethtool_ops */

/*
 * Init service functions
 */

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static inline u32 bnx2x_get_pretend_reg(struct bnx2x *bp, int func)
{
	switch (func) {
	case 0: return PXP2_REG_PGL_PRETEND_FUNC_F0;
	case 1:	return PXP2_REG_PGL_PRETEND_FUNC_F1;
	case 2:	return PXP2_REG_PGL_PRETEND_FUNC_F2;
	case 3:	return PXP2_REG_PGL_PRETEND_FUNC_F3;
	case 4:	return PXP2_REG_PGL_PRETEND_FUNC_F4;
	case 5:	return PXP2_REG_PGL_PRETEND_FUNC_F5;
	case 6:	return PXP2_REG_PGL_PRETEND_FUNC_F6;
	case 7:	return PXP2_REG_PGL_PRETEND_FUNC_F7;
	default:
		BNX2X_ERR("Unsupported function index: %d\n", func);
		return (u32)(-1);
	}
}

static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func)
{
	u32 reg = bnx2x_get_pretend_reg(bp, orig_func), new_val;

	/* Flush all outstanding writes */
	mmiowb();

	/* Pretend to be function 0 */
	REG_WR(bp, reg, 0);
	/* Flush the GRC transaction (in the chip) */
	new_val = REG_RD(bp, reg);
	if (new_val != 0) {
		BNX2X_ERR("Hmmm... Pretend register wasn't updated: (0,%d)!\n",
			  new_val);
		BUG();
	}

	/* From now we are in the "like-E1" mode */
	bnx2x_int_disable(bp);

	/* Flush all outstanding writes */
	mmiowb();

	/* Restore the original funtion settings */
	REG_WR(bp, reg, orig_func);
	new_val = REG_RD(bp, reg);
	if (new_val != orig_func) {
		BNX2X_ERR("Hmmm... Pretend register wasn't updated: (%d,%d)!\n",
			  orig_func, new_val);
		BUG();
	}
}

static inline void bnx2x_undi_int_disable(struct bnx2x *bp, int func)
{
	if (CHIP_IS_E1H(bp))
		bnx2x_undi_int_disable_e1h(bp, func);
	else
		bnx2x_int_disable(bp);
}

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static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
{
	u32 val;

	/* Check if there is any driver already loaded */
	val = REG_RD(bp, MISC_REG_UNPREPARED);
	if (val == 0x1) {
		/* Check if it is the UNDI driver
		 * UNDI driver initializes CID offset for normal bell to 0x7
		 */
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		bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
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		val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
		if (val == 0x7) {
			u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
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			/* save our func */
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			int func = BP_FUNC(bp);
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			u32 swap_en;
			u32 swap_val;
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			/* clear the UNDI indication */
			REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);

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			BNX2X_DEV_INFO("UNDI is active! reset device\n");

			/* try unload UNDI on port 0 */
			bp->func = 0;
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			bp->fw_seq =
			       (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
				DRV_MSG_SEQ_NUMBER_MASK);
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			reset_code = bnx2x_fw_command(bp, reset_code);

			/* if UNDI is loaded on the other port */
			if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {

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				/* send "DONE" for previous unload */
				bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);

				/* unload UNDI on port 1 */
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				bp->func = 1;
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				bp->fw_seq =
			       (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
					DRV_MSG_SEQ_NUMBER_MASK);
				reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;

				bnx2x_fw_command(bp, reset_code);
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			}

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			/* now it's safe to release the lock */
			bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);

7780
			bnx2x_undi_int_disable(bp, func);
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			/* close input traffic and wait for it */
			/* Do not rcv packets to BRB */
			REG_WR(bp,
			      (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
					     NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
			/* Do not direct rcv packets that are not for MCP to
			 * the BRB */
			REG_WR(bp,
			       (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
					      NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
			/* clear AEU */
			REG_WR(bp,
			     (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
					    MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
			msleep(10);

			/* save NIG port swap info */
			swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
			swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
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			/* reset device */
			REG_WR(bp,
			       GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7804
			       0xd3ffffff);
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			REG_WR(bp,
			       GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
			       0x1403);
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			/* take the NIG out of reset and restore swap values */
			REG_WR(bp,
			       GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
			       MISC_REGISTERS_RESET_REG_1_RST_NIG);
			REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
			REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);

			/* send unload done to the MCP */
			bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);

			/* restore our func and fw_seq */
			bp->func = func;
			bp->fw_seq =
			       (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
				DRV_MSG_SEQ_NUMBER_MASK);
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		} else
			bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
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	}
}

static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
{
	u32 val, val2, val3, val4, id;
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	u16 pmc;
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	/* Get the chip revision id and number. */
	/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
	val = REG_RD(bp, MISC_REG_CHIP_NUM);
	id = ((val & 0xffff) << 16);
	val = REG_RD(bp, MISC_REG_CHIP_REV);
	id |= ((val & 0xf) << 12);
	val = REG_RD(bp, MISC_REG_CHIP_METAL);
	id |= ((val & 0xff) << 4);
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	val = REG_RD(bp, MISC_REG_BOND_ID);
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	id |= (val & 0xf);
	bp->common.chip_id = id;
	bp->link_params.chip_id = bp->common.chip_id;
	BNX2X_DEV_INFO("chip ID is 0x%x\n", id);

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	val = (REG_RD(bp, 0x2874) & 0x55);
	if ((bp->common.chip_id & 0x1) ||
	    (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
		bp->flags |= ONE_PORT_FLAG;
		BNX2X_DEV_INFO("single port device\n");
	}

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	val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
	bp->common.flash_size = (NVRAM_1MB_SIZE <<
				 (val & MCPR_NVM_CFG4_FLASH_SIZE));
	BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
		       bp->common.flash_size, bp->common.flash_size);

	bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
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	bp->common.shmem2_base = REG_RD(bp, MISC_REG_GENERIC_CR_0);
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	bp->link_params.shmem_base = bp->common.shmem_base;
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	BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
		       bp->common.shmem_base, bp->common.shmem2_base);
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	if (!bp->common.shmem_base ||
	    (bp->common.shmem_base < 0xA0000) ||
	    (bp->common.shmem_base >= 0xC0000)) {
		BNX2X_DEV_INFO("MCP not active\n");
		bp->flags |= NO_MCP_FLAG;
		return;
	}

	val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
	if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
		!= (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
		BNX2X_ERR("BAD MCP validity signature\n");

	bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
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	BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
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	bp->link_params.hw_led_mode = ((bp->common.hw_config &
					SHARED_HW_CFG_LED_MODE_MASK) >>
				       SHARED_HW_CFG_LED_MODE_SHIFT);

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	bp->link_params.feature_config_flags = 0;
	val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
	if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
		bp->link_params.feature_config_flags |=
				FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
	else
		bp->link_params.feature_config_flags &=
				~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;

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	val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
	bp->common.bc_ver = val;
	BNX2X_DEV_INFO("bc_ver %X\n", val);
	if (val < BNX2X_BC_VER) {
		/* for now only warn
		 * later we might need to enforce this */
		BNX2X_ERR("This driver needs bc_ver %X but found %X,"
			  " please upgrade BC\n", BNX2X_BC_VER, val);
	}
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	bp->link_params.feature_config_flags |=
		(val >= REQ_BC_VER_4_VRFY_OPT_MDL) ?
		FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
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	if (BP_E1HVN(bp) == 0) {
		pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
		bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
	} else {
		/* no WOL capability for E1HVN != 0 */
		bp->flags |= NO_WOL_FLAG;
	}
	BNX2X_DEV_INFO("%sWoL capable\n",
7917
		       (bp->flags & NO_WOL_FLAG) ? "not " : "");
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	val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
	val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
	val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
	val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);

	printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
	       val, val2, val3, val4);
}

static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
						    u32 switch_cfg)
7930
{
7931
	int port = BP_PORT(bp);
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	u32 ext_phy_type;

	switch (switch_cfg) {
	case SWITCH_CFG_1G:
		BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);

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7938 7939
		ext_phy_type =
			SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7940 7941 7942 7943 7944
		switch (ext_phy_type) {
		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
				       ext_phy_type);

7945 7946 7947 7948 7949 7950 7951 7952 7953 7954 7955
			bp->port.supported |= (SUPPORTED_10baseT_Half |
					       SUPPORTED_10baseT_Full |
					       SUPPORTED_100baseT_Half |
					       SUPPORTED_100baseT_Full |
					       SUPPORTED_1000baseT_Full |
					       SUPPORTED_2500baseX_Full |
					       SUPPORTED_TP |
					       SUPPORTED_FIBRE |
					       SUPPORTED_Autoneg |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
7956 7957 7958 7959 7960 7961
			break;

		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
				       ext_phy_type);

7962 7963 7964 7965 7966 7967 7968 7969 7970 7971
			bp->port.supported |= (SUPPORTED_10baseT_Half |
					       SUPPORTED_10baseT_Full |
					       SUPPORTED_100baseT_Half |
					       SUPPORTED_100baseT_Full |
					       SUPPORTED_1000baseT_Full |
					       SUPPORTED_TP |
					       SUPPORTED_FIBRE |
					       SUPPORTED_Autoneg |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
7972 7973 7974 7975 7976
			break;

		default:
			BNX2X_ERR("NVRAM config error. "
				  "BAD SerDes ext_phy_config 0x%x\n",
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7977
				  bp->link_params.ext_phy_config);
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			return;
		}

7981 7982 7983
		bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
					   port*0x10);
		BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7984 7985 7986 7987 7988
		break;

	case SWITCH_CFG_10G:
		BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);

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7989 7990
		ext_phy_type =
			XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
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		switch (ext_phy_type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
				       ext_phy_type);

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			bp->port.supported |= (SUPPORTED_10baseT_Half |
					       SUPPORTED_10baseT_Full |
					       SUPPORTED_100baseT_Half |
					       SUPPORTED_100baseT_Full |
					       SUPPORTED_1000baseT_Full |
					       SUPPORTED_2500baseX_Full |
					       SUPPORTED_10000baseT_Full |
					       SUPPORTED_TP |
					       SUPPORTED_FIBRE |
					       SUPPORTED_Autoneg |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
8008 8009
			break;

8010 8011
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
8012
				       ext_phy_type);
8013

8014
			bp->port.supported |= (SUPPORTED_10000baseT_Full |
8015
					       SUPPORTED_1000baseT_Full |
8016
					       SUPPORTED_FIBRE |
8017
					       SUPPORTED_Autoneg |
8018 8019
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
8020 8021
			break;

8022 8023
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
8024 8025
				       ext_phy_type);

8026
			bp->port.supported |= (SUPPORTED_10000baseT_Full |
8027
					       SUPPORTED_2500baseX_Full |
8028
					       SUPPORTED_1000baseT_Full |
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					       SUPPORTED_FIBRE |
					       SUPPORTED_Autoneg |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
			break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
				       ext_phy_type);

			bp->port.supported |= (SUPPORTED_10000baseT_Full |
8040 8041 8042
					       SUPPORTED_FIBRE |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
8043 8044
			break;

8045 8046
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
8047 8048
				       ext_phy_type);

8049 8050 8051 8052 8053
			bp->port.supported |= (SUPPORTED_10000baseT_Full |
					       SUPPORTED_1000baseT_Full |
					       SUPPORTED_FIBRE |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
8054 8055
			break;

8056 8057
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
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8058 8059
				       ext_phy_type);

8060 8061 8062
			bp->port.supported |= (SUPPORTED_10000baseT_Full |
					       SUPPORTED_1000baseT_Full |
					       SUPPORTED_Autoneg |
8063
					       SUPPORTED_FIBRE |
8064 8065
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
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			break;

8068 8069 8070 8071 8072 8073 8074 8075 8076 8077 8078 8079
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n",
				       ext_phy_type);

			bp->port.supported |= (SUPPORTED_10000baseT_Full |
					       SUPPORTED_1000baseT_Full |
					       SUPPORTED_Autoneg |
					       SUPPORTED_FIBRE |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
			break;

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		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
				       ext_phy_type);

8084 8085 8086 8087 8088
			bp->port.supported |= (SUPPORTED_10000baseT_Full |
					       SUPPORTED_TP |
					       SUPPORTED_Autoneg |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
8089 8090
			break;

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		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
			BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n",
				       ext_phy_type);

			bp->port.supported |= (SUPPORTED_10baseT_Half |
					       SUPPORTED_10baseT_Full |
					       SUPPORTED_100baseT_Half |
					       SUPPORTED_100baseT_Full |
					       SUPPORTED_1000baseT_Full |
					       SUPPORTED_10000baseT_Full |
					       SUPPORTED_TP |
					       SUPPORTED_Autoneg |
					       SUPPORTED_Pause |
					       SUPPORTED_Asym_Pause);
			break;

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		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
			BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
				  bp->link_params.ext_phy_config);
			break;

8112 8113 8114
		default:
			BNX2X_ERR("NVRAM config error. "
				  "BAD XGXS ext_phy_config 0x%x\n",
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8115
				  bp->link_params.ext_phy_config);
8116 8117 8118
			return;
		}

8119 8120 8121
		bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
					   port*0x18);
		BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8122 8123 8124 8125 8126

		break;

	default:
		BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8127
			  bp->port.link_config);
8128 8129
		return;
	}
8130
	bp->link_params.phy_addr = bp->port.phy_addr;
8131 8132

	/* mask what we support according to speed_cap_mask */
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8133 8134
	if (!(bp->link_params.speed_cap_mask &
				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8135
		bp->port.supported &= ~SUPPORTED_10baseT_Half;
8136

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8137 8138
	if (!(bp->link_params.speed_cap_mask &
				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8139
		bp->port.supported &= ~SUPPORTED_10baseT_Full;
8140

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8141 8142
	if (!(bp->link_params.speed_cap_mask &
				PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8143
		bp->port.supported &= ~SUPPORTED_100baseT_Half;
8144

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8145 8146
	if (!(bp->link_params.speed_cap_mask &
				PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8147
		bp->port.supported &= ~SUPPORTED_100baseT_Full;
8148

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8149 8150
	if (!(bp->link_params.speed_cap_mask &
					PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8151 8152
		bp->port.supported &= ~(SUPPORTED_1000baseT_Half |
					SUPPORTED_1000baseT_Full);
8153

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8154 8155
	if (!(bp->link_params.speed_cap_mask &
					PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8156
		bp->port.supported &= ~SUPPORTED_2500baseX_Full;
8157

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8158 8159
	if (!(bp->link_params.speed_cap_mask &
					PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8160
		bp->port.supported &= ~SUPPORTED_10000baseT_Full;
8161

8162
	BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported);
8163 8164
}

8165
static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8166
{
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8167
	bp->link_params.req_duplex = DUPLEX_FULL;
8168

8169
	switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8170
	case PORT_FEATURE_LINK_SPEED_AUTO:
8171
		if (bp->port.supported & SUPPORTED_Autoneg) {
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			bp->link_params.req_line_speed = SPEED_AUTO_NEG;
8173
			bp->port.advertising = bp->port.supported;
8174
		} else {
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			u32 ext_phy_type =
			    XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);

			if ((ext_phy_type ==
			     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
			    (ext_phy_type ==
			     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
8182
				/* force 10G, no AN */
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8183
				bp->link_params.req_line_speed = SPEED_10000;
8184
				bp->port.advertising =
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						(ADVERTISED_10000baseT_Full |
						 ADVERTISED_FIBRE);
				break;
			}
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  Autoneg not supported\n",
8192
				  bp->port.link_config);
8193 8194 8195 8196 8197
			return;
		}
		break;

	case PORT_FEATURE_LINK_SPEED_10M_FULL:
8198
		if (bp->port.supported & SUPPORTED_10baseT_Full) {
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8199
			bp->link_params.req_line_speed = SPEED_10;
8200 8201
			bp->port.advertising = (ADVERTISED_10baseT_Full |
						ADVERTISED_TP);
8202 8203 8204 8205
		} else {
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  speed_cap_mask 0x%x\n",
8206
				  bp->port.link_config,
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8207
				  bp->link_params.speed_cap_mask);
8208 8209 8210 8211 8212
			return;
		}
		break;

	case PORT_FEATURE_LINK_SPEED_10M_HALF:
8213
		if (bp->port.supported & SUPPORTED_10baseT_Half) {
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8214 8215
			bp->link_params.req_line_speed = SPEED_10;
			bp->link_params.req_duplex = DUPLEX_HALF;
8216 8217
			bp->port.advertising = (ADVERTISED_10baseT_Half |
						ADVERTISED_TP);
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		} else {
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  speed_cap_mask 0x%x\n",
8222
				  bp->port.link_config,
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8223
				  bp->link_params.speed_cap_mask);
8224 8225 8226 8227 8228
			return;
		}
		break;

	case PORT_FEATURE_LINK_SPEED_100M_FULL:
8229
		if (bp->port.supported & SUPPORTED_100baseT_Full) {
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8230
			bp->link_params.req_line_speed = SPEED_100;
8231 8232
			bp->port.advertising = (ADVERTISED_100baseT_Full |
						ADVERTISED_TP);
8233 8234 8235 8236
		} else {
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  speed_cap_mask 0x%x\n",
8237
				  bp->port.link_config,
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8238
				  bp->link_params.speed_cap_mask);
8239 8240 8241 8242 8243
			return;
		}
		break;

	case PORT_FEATURE_LINK_SPEED_100M_HALF:
8244
		if (bp->port.supported & SUPPORTED_100baseT_Half) {
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8245 8246
			bp->link_params.req_line_speed = SPEED_100;
			bp->link_params.req_duplex = DUPLEX_HALF;
8247 8248
			bp->port.advertising = (ADVERTISED_100baseT_Half |
						ADVERTISED_TP);
8249 8250 8251 8252
		} else {
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  speed_cap_mask 0x%x\n",
8253
				  bp->port.link_config,
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8254
				  bp->link_params.speed_cap_mask);
8255 8256 8257 8258 8259
			return;
		}
		break;

	case PORT_FEATURE_LINK_SPEED_1G:
8260
		if (bp->port.supported & SUPPORTED_1000baseT_Full) {
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8261
			bp->link_params.req_line_speed = SPEED_1000;
8262 8263
			bp->port.advertising = (ADVERTISED_1000baseT_Full |
						ADVERTISED_TP);
8264 8265 8266 8267
		} else {
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  speed_cap_mask 0x%x\n",
8268
				  bp->port.link_config,
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8269
				  bp->link_params.speed_cap_mask);
8270 8271 8272 8273 8274
			return;
		}
		break;

	case PORT_FEATURE_LINK_SPEED_2_5G:
8275
		if (bp->port.supported & SUPPORTED_2500baseX_Full) {
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8276
			bp->link_params.req_line_speed = SPEED_2500;
8277 8278
			bp->port.advertising = (ADVERTISED_2500baseX_Full |
						ADVERTISED_TP);
8279 8280 8281 8282
		} else {
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  speed_cap_mask 0x%x\n",
8283
				  bp->port.link_config,
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8284
				  bp->link_params.speed_cap_mask);
8285 8286 8287 8288 8289 8290 8291
			return;
		}
		break;

	case PORT_FEATURE_LINK_SPEED_10G_CX4:
	case PORT_FEATURE_LINK_SPEED_10G_KX4:
	case PORT_FEATURE_LINK_SPEED_10G_KR:
8292
		if (bp->port.supported & SUPPORTED_10000baseT_Full) {
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8293
			bp->link_params.req_line_speed = SPEED_10000;
8294 8295
			bp->port.advertising = (ADVERTISED_10000baseT_Full |
						ADVERTISED_FIBRE);
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		} else {
			BNX2X_ERR("NVRAM config error. "
				  "Invalid link_config 0x%x"
				  "  speed_cap_mask 0x%x\n",
8300
				  bp->port.link_config,
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8301
				  bp->link_params.speed_cap_mask);
8302 8303 8304 8305 8306 8307 8308
			return;
		}
		break;

	default:
		BNX2X_ERR("NVRAM config error. "
			  "BAD link speed link_config 0x%x\n",
8309
			  bp->port.link_config);
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8310
		bp->link_params.req_line_speed = SPEED_AUTO_NEG;
8311
		bp->port.advertising = bp->port.supported;
8312 8313 8314
		break;
	}

8315 8316
	bp->link_params.req_flow_ctrl = (bp->port.link_config &
					 PORT_FEATURE_FLOW_CONTROL_MASK);
8317
	if ((bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
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8318
	    !(bp->port.supported & SUPPORTED_Autoneg))
8319
		bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8320

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8321
	BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d  req_flow_ctrl 0x%x"
8322
		       "  advertising 0x%x\n",
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		       bp->link_params.req_line_speed,
		       bp->link_params.req_duplex,
8325
		       bp->link_params.req_flow_ctrl, bp->port.advertising);
8326 8327
}

8328
static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8329
{
8330 8331
	int port = BP_PORT(bp);
	u32 val, val2;
8332
	u32 config;
8333
	u16 i;
8334

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	bp->link_params.bp = bp;
8336
	bp->link_params.port = port;
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	bp->link_params.lane_config =
8339
		SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
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	bp->link_params.ext_phy_config =
8341 8342
		SHMEM_RD(bp,
			 dev_info.port_hw_config[port].external_phy_config);
8343 8344 8345 8346 8347 8348 8349 8350 8351 8352 8353
	/* BCM8727_NOC => BCM8727 no over current */
	if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
	    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
		bp->link_params.ext_phy_config &=
			~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
		bp->link_params.ext_phy_config |=
			PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
		bp->link_params.feature_config_flags |=
			FEATURE_CONFIG_BCM8727_NOC;
	}

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	bp->link_params.speed_cap_mask =
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		SHMEM_RD(bp,
			 dev_info.port_hw_config[port].speed_capability_mask);

8358
	bp->port.link_config =
8359 8360
		SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);

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	/* Get the 4 lanes xgxs config rx and tx */
	for (i = 0; i < 2; i++) {
		val = SHMEM_RD(bp,
			   dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
		bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
		bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);

		val = SHMEM_RD(bp,
			   dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
		bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
		bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
	}

8374 8375 8376
	/* If the device is capable of WoL, set the default state according
	 * to the HW
	 */
8377
	config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8378 8379 8380
	bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
		   (config & PORT_FEATURE_WOL_ENABLED));

8381 8382
	BNX2X_DEV_INFO("lane_config 0x%08x  ext_phy_config 0x%08x"
		       "  speed_cap_mask 0x%08x  link_config 0x%08x\n",
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8383 8384
		       bp->link_params.lane_config,
		       bp->link_params.ext_phy_config,
8385
		       bp->link_params.speed_cap_mask, bp->port.link_config);
8386

8387 8388
	bp->link_params.switch_cfg |= (bp->port.link_config &
				       PORT_FEATURE_CONNECTED_SWITCH_MASK);
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8389
	bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
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	bnx2x_link_settings_requested(bp);

	val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
	val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
	bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
	bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
	bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
	bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
	bp->dev->dev_addr[4] = (u8)(val >> 8  & 0xff);
	bp->dev->dev_addr[5] = (u8)(val & 0xff);
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	memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
	memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
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}

static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
{
	int func = BP_FUNC(bp);
	u32 val, val2;
	int rc = 0;
8410

8411
	bnx2x_get_common_hwinfo(bp);
8412

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	bp->e1hov = 0;
	bp->e1hmf = 0;
	if (CHIP_IS_E1H(bp)) {
		bp->mf_config =
			SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
8418

8419
		val = (SHMEM_RD(bp, mf_cfg.func_mf_config[FUNC_0].e1hov_tag) &
8420
		       FUNC_MF_CFG_E1HOV_TAG_MASK);
8421
		if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
8422
			bp->e1hmf = 1;
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		BNX2X_DEV_INFO("%s function mode\n",
			       IS_E1HMF(bp) ? "multi" : "single");

		if (IS_E1HMF(bp)) {
			val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].
								e1hov_tag) &
			       FUNC_MF_CFG_E1HOV_TAG_MASK);
			if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
				bp->e1hov = val;
				BNX2X_DEV_INFO("E1HOV for func %d is %d "
					       "(0x%04x)\n",
					       func, bp->e1hov, bp->e1hov);
			} else {
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				BNX2X_ERR("!!!  No valid E1HOV for func %d,"
					  "  aborting\n", func);
				rc = -EPERM;
			}
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		} else {
			if (BP_E1HVN(bp)) {
				BNX2X_ERR("!!!  VN %d in single function mode,"
					  "  aborting\n", BP_E1HVN(bp));
				rc = -EPERM;
			}
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		}
	}
8448

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	if (!BP_NOMCP(bp)) {
		bnx2x_get_port_hwinfo(bp);

		bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) &
			      DRV_MSG_SEQ_NUMBER_MASK);
		BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
	}

	if (IS_E1HMF(bp)) {
		val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper);
		val = SHMEM_RD(bp,  mf_cfg.func_mf_config[func].mac_lower);
		if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
		    (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
			bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
			bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
			bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
			bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
			bp->dev->dev_addr[4] = (u8)(val >> 8  & 0xff);
			bp->dev->dev_addr[5] = (u8)(val & 0xff);
			memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
			       ETH_ALEN);
			memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
			       ETH_ALEN);
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		}
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		return rc;
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	}

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	if (BP_NOMCP(bp)) {
		/* only supposed to happen on emulation/FPGA */
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8479
		BNX2X_ERR("warning random MAC workaround active\n");
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		random_ether_addr(bp->dev->dev_addr);
		memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
	}
8483

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	return rc;
}

static int __devinit bnx2x_init_bp(struct bnx2x *bp)
{
	int func = BP_FUNC(bp);
8490
	int timer_interval;
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	int rc;

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	/* Disable interrupt handling until HW is initialized */
	atomic_set(&bp->intr_sem, 1);
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	smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8496

8497
	mutex_init(&bp->port.phy_mutex);
8498

8499
	INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
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	INIT_WORK(&bp->reset_task, bnx2x_reset_task);

	rc = bnx2x_get_hwinfo(bp);

	/* need to reset chip if undi was active */
	if (!BP_NOMCP(bp))
		bnx2x_undi_unload(bp);

	if (CHIP_REV_IS_FPGA(bp))
		printk(KERN_ERR PFX "FPGA detected\n");

	if (BP_NOMCP(bp) && (func == 0))
		printk(KERN_ERR PFX
		       "MCP disabled, must load devices in order!\n");

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8515
	/* Set multi queue mode */
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	if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
	    ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
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		printk(KERN_ERR PFX
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8519
		      "Multi disabled since int_mode requested is not MSI-X\n");
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		multi_mode = ETH_RSS_MODE_DISABLED;
	}
	bp->multi_mode = multi_mode;


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	/* Set TPA flags */
	if (disable_tpa) {
		bp->flags &= ~TPA_ENABLE_FLAG;
		bp->dev->features &= ~NETIF_F_LRO;
	} else {
		bp->flags |= TPA_ENABLE_FLAG;
		bp->dev->features |= NETIF_F_LRO;
	}

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	bp->mrrs = mrrs;
8535

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	bp->tx_ring_size = MAX_TX_AVAIL;
	bp->rx_ring_size = MAX_RX_AVAIL;

	bp->rx_csum = 1;

	bp->tx_ticks = 50;
	bp->rx_ticks = 25;

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	timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
	bp->current_interval = (poll ? poll : timer_interval);
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	init_timer(&bp->timer);
	bp->timer.expires = jiffies + bp->current_interval;
	bp->timer.data = (unsigned long) bp;
	bp->timer.function = bnx2x_timer;

	return rc;
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}

/*
 * ethtool service functions
 */

/* All ethtool functions called with rtnl_lock */

static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct bnx2x *bp = netdev_priv(dev);

8565 8566
	cmd->supported = bp->port.supported;
	cmd->advertising = bp->port.advertising;
8567 8568

	if (netif_carrier_ok(dev)) {
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		cmd->speed = bp->link_vars.line_speed;
		cmd->duplex = bp->link_vars.duplex;
8571
	} else {
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		cmd->speed = bp->link_params.req_line_speed;
		cmd->duplex = bp->link_params.req_duplex;
8574
	}
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	if (IS_E1HMF(bp)) {
		u16 vn_max_rate;

		vn_max_rate = ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
				FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
		if (vn_max_rate < cmd->speed)
			cmd->speed = vn_max_rate;
	}
8583

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	if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
		u32 ext_phy_type =
			XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
8587 8588 8589 8590

		switch (ext_phy_type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
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8591
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
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		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8595
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
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			cmd->port = PORT_FIBRE;
			break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
8600
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
8601 8602 8603
			cmd->port = PORT_TP;
			break;

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8604 8605 8606 8607 8608
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
			BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
				  bp->link_params.ext_phy_config);
			break;

8609 8610
		default:
			DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
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8611 8612
			   bp->link_params.ext_phy_config);
			break;
8613 8614
		}
	} else
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		cmd->port = PORT_TP;

8617
	cmd->phy_address = bp->port.phy_addr;
8618 8619
	cmd->transceiver = XCVR_INTERNAL;

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8620
	if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
8621
		cmd->autoneg = AUTONEG_ENABLE;
8622
	else
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		cmd->autoneg = AUTONEG_DISABLE;

	cmd->maxtxpkt = 0;
	cmd->maxrxpkt = 0;

	DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
	   DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
	   DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
	   DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
	   cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
	   cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
	   cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);

	return 0;
}

static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct bnx2x *bp = netdev_priv(dev);
	u32 advertising;

8644 8645 8646
	if (IS_E1HMF(bp))
		return 0;

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	DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
	   DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
	   DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
	   DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
	   cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
	   cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
	   cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);

	if (cmd->autoneg == AUTONEG_ENABLE) {
8656 8657
		if (!(bp->port.supported & SUPPORTED_Autoneg)) {
			DP(NETIF_MSG_LINK, "Autoneg not supported\n");
8658
			return -EINVAL;
8659
		}
8660 8661

		/* advertise the requested speed and duplex if supported */
8662
		cmd->advertising &= bp->port.supported;
8663

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		bp->link_params.req_line_speed = SPEED_AUTO_NEG;
		bp->link_params.req_duplex = DUPLEX_FULL;
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		bp->port.advertising |= (ADVERTISED_Autoneg |
					 cmd->advertising);
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	} else { /* forced speed */
		/* advertise the requested speed and duplex if supported */
		switch (cmd->speed) {
		case SPEED_10:
			if (cmd->duplex == DUPLEX_FULL) {
8674
				if (!(bp->port.supported &
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				      SUPPORTED_10baseT_Full)) {
					DP(NETIF_MSG_LINK,
					   "10M full not supported\n");
8678
					return -EINVAL;
8679
				}
8680 8681 8682 8683

				advertising = (ADVERTISED_10baseT_Full |
					       ADVERTISED_TP);
			} else {
8684
				if (!(bp->port.supported &
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				      SUPPORTED_10baseT_Half)) {
					DP(NETIF_MSG_LINK,
					   "10M half not supported\n");
8688
					return -EINVAL;
8689
				}
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				advertising = (ADVERTISED_10baseT_Half |
					       ADVERTISED_TP);
			}
			break;

		case SPEED_100:
			if (cmd->duplex == DUPLEX_FULL) {
8698
				if (!(bp->port.supported &
8699 8700 8701
						SUPPORTED_100baseT_Full)) {
					DP(NETIF_MSG_LINK,
					   "100M full not supported\n");
8702
					return -EINVAL;
8703
				}
8704 8705 8706 8707

				advertising = (ADVERTISED_100baseT_Full |
					       ADVERTISED_TP);
			} else {
8708
				if (!(bp->port.supported &
8709 8710 8711
						SUPPORTED_100baseT_Half)) {
					DP(NETIF_MSG_LINK,
					   "100M half not supported\n");
8712
					return -EINVAL;
8713
				}
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				advertising = (ADVERTISED_100baseT_Half |
					       ADVERTISED_TP);
			}
			break;

		case SPEED_1000:
8721 8722
			if (cmd->duplex != DUPLEX_FULL) {
				DP(NETIF_MSG_LINK, "1G half not supported\n");
8723
				return -EINVAL;
8724
			}
8725

8726
			if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
8727
				DP(NETIF_MSG_LINK, "1G full not supported\n");
8728
				return -EINVAL;
8729
			}
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			advertising = (ADVERTISED_1000baseT_Full |
				       ADVERTISED_TP);
			break;

		case SPEED_2500:
8736 8737 8738
			if (cmd->duplex != DUPLEX_FULL) {
				DP(NETIF_MSG_LINK,
				   "2.5G half not supported\n");
8739
				return -EINVAL;
8740
			}
8741

8742
			if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
8743 8744
				DP(NETIF_MSG_LINK,
				   "2.5G full not supported\n");
8745
				return -EINVAL;
8746
			}
8747

8748
			advertising = (ADVERTISED_2500baseX_Full |
8749 8750 8751 8752
				       ADVERTISED_TP);
			break;

		case SPEED_10000:
8753 8754
			if (cmd->duplex != DUPLEX_FULL) {
				DP(NETIF_MSG_LINK, "10G half not supported\n");
8755
				return -EINVAL;
8756
			}
8757

8758
			if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
8759
				DP(NETIF_MSG_LINK, "10G full not supported\n");
8760
				return -EINVAL;
8761
			}
8762 8763 8764 8765 8766 8767

			advertising = (ADVERTISED_10000baseT_Full |
				       ADVERTISED_FIBRE);
			break;

		default:
8768
			DP(NETIF_MSG_LINK, "Unsupported speed\n");
8769 8770 8771
			return -EINVAL;
		}

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		bp->link_params.req_line_speed = cmd->speed;
		bp->link_params.req_duplex = cmd->duplex;
8774
		bp->port.advertising = advertising;
8775 8776
	}

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8777
	DP(NETIF_MSG_LINK, "req_line_speed %d\n"
8778
	   DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
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8779
	   bp->link_params.req_line_speed, bp->link_params.req_duplex,
8780
	   bp->port.advertising);
8781

8782
	if (netif_running(dev)) {
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8783
		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8784 8785
		bnx2x_link_set(bp);
	}
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	return 0;
}

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8790 8791
#define PHY_FW_VER_LEN			10

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static void bnx2x_get_drvinfo(struct net_device *dev,
			      struct ethtool_drvinfo *info)
{
	struct bnx2x *bp = netdev_priv(dev);
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	u8 phy_fw_ver[PHY_FW_VER_LEN];
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	strcpy(info->driver, DRV_MODULE_NAME);
	strcpy(info->version, DRV_MODULE_VERSION);
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	phy_fw_ver[0] = '\0';
8802
	if (bp->port.pmf) {
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		bnx2x_acquire_phy_lock(bp);
8804 8805 8806
		bnx2x_get_ext_phy_fw_version(&bp->link_params,
					     (bp->state != BNX2X_STATE_CLOSED),
					     phy_fw_ver, PHY_FW_VER_LEN);
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8807
		bnx2x_release_phy_lock(bp);
8808
	}
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8809

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	snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s",
		 (bp->common.bc_ver & 0xff0000) >> 16,
		 (bp->common.bc_ver & 0xff00) >> 8,
		 (bp->common.bc_ver & 0xff),
		 ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver);
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	strcpy(info->bus_info, pci_name(bp->pdev));
	info->n_stats = BNX2X_NUM_STATS;
	info->testinfo_len = BNX2X_NUM_TESTS;
8818
	info->eedump_len = bp->common.flash_size;
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	info->regdump_len = 0;
}

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#define IS_E1_ONLINE(info)	(((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
#define IS_E1H_ONLINE(info)	(((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)

static int bnx2x_get_regs_len(struct net_device *dev)
{
	static u32 regdump_len;
	struct bnx2x *bp = netdev_priv(dev);
	int i;

	if (regdump_len)
		return regdump_len;

	if (CHIP_IS_E1(bp)) {
		for (i = 0; i < REGS_COUNT; i++)
			if (IS_E1_ONLINE(reg_addrs[i].info))
				regdump_len += reg_addrs[i].size;

		for (i = 0; i < WREGS_COUNT_E1; i++)
			if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
				regdump_len += wreg_addrs_e1[i].size *
					(1 + wreg_addrs_e1[i].read_regs_count);

	} else { /* E1H */
		for (i = 0; i < REGS_COUNT; i++)
			if (IS_E1H_ONLINE(reg_addrs[i].info))
				regdump_len += reg_addrs[i].size;

		for (i = 0; i < WREGS_COUNT_E1H; i++)
			if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
				regdump_len += wreg_addrs_e1h[i].size *
					(1 + wreg_addrs_e1h[i].read_regs_count);
	}
	regdump_len *= 4;
	regdump_len += sizeof(struct dump_hdr);

	return regdump_len;
}

static void bnx2x_get_regs(struct net_device *dev,
			   struct ethtool_regs *regs, void *_p)
{
	u32 *p = _p, i, j;
	struct bnx2x *bp = netdev_priv(dev);
	struct dump_hdr dump_hdr = {0};

	regs->version = 0;
	memset(p, 0, regs->len);

	if (!netif_running(bp->dev))
		return;

	dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
	dump_hdr.dump_sign = dump_sign_all;
	dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
	dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
	dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
	dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
	dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE;

	memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
	p += dump_hdr.hdr_size + 1;

	if (CHIP_IS_E1(bp)) {
		for (i = 0; i < REGS_COUNT; i++)
			if (IS_E1_ONLINE(reg_addrs[i].info))
				for (j = 0; j < reg_addrs[i].size; j++)
					*p++ = REG_RD(bp,
						      reg_addrs[i].addr + j*4);

	} else { /* E1H */
		for (i = 0; i < REGS_COUNT; i++)
			if (IS_E1H_ONLINE(reg_addrs[i].info))
				for (j = 0; j < reg_addrs[i].size; j++)
					*p++ = REG_RD(bp,
						      reg_addrs[i].addr + j*4);
	}
}

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static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct bnx2x *bp = netdev_priv(dev);

	if (bp->flags & NO_WOL_FLAG) {
		wol->supported = 0;
		wol->wolopts = 0;
	} else {
		wol->supported = WAKE_MAGIC;
		if (bp->wol)
			wol->wolopts = WAKE_MAGIC;
		else
			wol->wolopts = 0;
	}
	memset(&wol->sopass, 0, sizeof(wol->sopass));
}

static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct bnx2x *bp = netdev_priv(dev);

	if (wol->wolopts & ~WAKE_MAGIC)
		return -EINVAL;

	if (wol->wolopts & WAKE_MAGIC) {
		if (bp->flags & NO_WOL_FLAG)
			return -EINVAL;

		bp->wol = 1;
8929
	} else
8930
		bp->wol = 0;
8931

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	return 0;
}

static u32 bnx2x_get_msglevel(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

	return bp->msglevel;
}

static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
{
	struct bnx2x *bp = netdev_priv(dev);

	if (capable(CAP_NET_ADMIN))
		bp->msglevel = level;
}

static int bnx2x_nway_reset(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

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	if (!bp->port.pmf)
		return 0;
8956

8957
	if (netif_running(dev)) {
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8958
		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
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		bnx2x_link_set(bp);
	}
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	return 0;
}

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static u32
bnx2x_get_link(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

	return bp->link_vars.link_up;
}

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static int bnx2x_get_eeprom_len(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

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	return bp->common.flash_size;
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}

static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
{
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	int port = BP_PORT(bp);
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	int count, i;
	u32 val = 0;

	/* adjust timeout for emulation/FPGA */
	count = NVRAM_TIMEOUT_COUNT;
	if (CHIP_REV_IS_SLOW(bp))
		count *= 100;

	/* request access to nvram interface */
	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
	       (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));

	for (i = 0; i < count*10; i++) {
		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
		if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
			break;

		udelay(5);
	}

	if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
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		DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
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		return -EBUSY;
	}

	return 0;
}

static int bnx2x_release_nvram_lock(struct bnx2x *bp)
{
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	int port = BP_PORT(bp);
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	int count, i;
	u32 val = 0;

	/* adjust timeout for emulation/FPGA */
	count = NVRAM_TIMEOUT_COUNT;
	if (CHIP_REV_IS_SLOW(bp))
		count *= 100;

	/* relinquish nvram interface */
	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
	       (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));

	for (i = 0; i < count*10; i++) {
		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
		if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
			break;

		udelay(5);
	}

	if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
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		DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
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		return -EBUSY;
	}

	return 0;
}

static void bnx2x_enable_nvram_access(struct bnx2x *bp)
{
	u32 val;

	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);

	/* enable both bits, even on read */
	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
	       (val | MCPR_NVM_ACCESS_ENABLE_EN |
		      MCPR_NVM_ACCESS_ENABLE_WR_EN));
}

static void bnx2x_disable_nvram_access(struct bnx2x *bp)
{
	u32 val;

	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);

	/* disable both bits, even after read */
	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
	       (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
			MCPR_NVM_ACCESS_ENABLE_WR_EN)));
}

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static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
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				  u32 cmd_flags)
{
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	int count, i, rc;
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	u32 val;

	/* build the command word */
	cmd_flags |= MCPR_NVM_COMMAND_DOIT;

	/* need to clear DONE bit separately */
	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);

	/* address of the NVRAM to read from */
	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));

	/* issue a read command */
	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);

	/* adjust timeout for emulation/FPGA */
	count = NVRAM_TIMEOUT_COUNT;
	if (CHIP_REV_IS_SLOW(bp))
		count *= 100;

	/* wait for completion */
	*ret_val = 0;
	rc = -EBUSY;
	for (i = 0; i < count; i++) {
		udelay(5);
		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);

		if (val & MCPR_NVM_COMMAND_DONE) {
			val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
			/* we read nvram data in cpu order
			 * but ethtool sees it as an array of bytes
			 * converting to big-endian will do the work */
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			*ret_val = cpu_to_be32(val);
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			rc = 0;
			break;
		}
	}

	return rc;
}

static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
			    int buf_size)
{
	int rc;
	u32 cmd_flags;
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	__be32 val;
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	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
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		DP(BNX2X_MSG_NVM,
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		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
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		   offset, buf_size);
		return -EINVAL;
	}

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	if (offset + buf_size > bp->common.flash_size) {
		DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
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				  " buf_size (0x%x) > flash_size (0x%x)\n",
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		   offset, buf_size, bp->common.flash_size);
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		return -EINVAL;
	}

	/* request access to nvram interface */
	rc = bnx2x_acquire_nvram_lock(bp);
	if (rc)
		return rc;

	/* enable access to nvram interface */
	bnx2x_enable_nvram_access(bp);

	/* read the first word(s) */
	cmd_flags = MCPR_NVM_COMMAND_FIRST;
	while ((buf_size > sizeof(u32)) && (rc == 0)) {
		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
		memcpy(ret_buf, &val, 4);

		/* advance to the next dword */
		offset += sizeof(u32);
		ret_buf += sizeof(u32);
		buf_size -= sizeof(u32);
		cmd_flags = 0;
	}

	if (rc == 0) {
		cmd_flags |= MCPR_NVM_COMMAND_LAST;
		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
		memcpy(ret_buf, &val, 4);
	}

	/* disable access to nvram interface */
	bnx2x_disable_nvram_access(bp);
	bnx2x_release_nvram_lock(bp);

	return rc;
}

static int bnx2x_get_eeprom(struct net_device *dev,
			    struct ethtool_eeprom *eeprom, u8 *eebuf)
{
	struct bnx2x *bp = netdev_priv(dev);
	int rc;

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	if (!netif_running(dev))
		return -EAGAIN;

9175
	DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
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	   DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
	   eeprom->len, eeprom->len);

	/* parameters already validated in ethtool_get_eeprom */

	rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);

	return rc;
}

static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
				   u32 cmd_flags)
{
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	int count, i, rc;
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	/* build the command word */
	cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;

	/* need to clear DONE bit separately */
	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);

	/* write the data */
	REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);

	/* address of the NVRAM to write to */
	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));

	/* issue the write command */
	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);

	/* adjust timeout for emulation/FPGA */
	count = NVRAM_TIMEOUT_COUNT;
	if (CHIP_REV_IS_SLOW(bp))
		count *= 100;

	/* wait for completion */
	rc = -EBUSY;
	for (i = 0; i < count; i++) {
		udelay(5);
		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
		if (val & MCPR_NVM_COMMAND_DONE) {
			rc = 0;
			break;
		}
	}

	return rc;
}

9227
#define BYTE_OFFSET(offset)		(8 * (offset & 0x03))
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static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
			      int buf_size)
{
	int rc;
	u32 cmd_flags;
	u32 align_offset;
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	__be32 val;
9236

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	if (offset + buf_size > bp->common.flash_size) {
		DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
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				  " buf_size (0x%x) > flash_size (0x%x)\n",
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		   offset, buf_size, bp->common.flash_size);
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		return -EINVAL;
	}

	/* request access to nvram interface */
	rc = bnx2x_acquire_nvram_lock(bp);
	if (rc)
		return rc;

	/* enable access to nvram interface */
	bnx2x_enable_nvram_access(bp);

	cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
	align_offset = (offset & ~0x03);
	rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);

	if (rc == 0) {
		val &= ~(0xff << BYTE_OFFSET(offset));
		val |= (*data_buf << BYTE_OFFSET(offset));

		/* nvram data is returned as an array of bytes
		 * convert it back to cpu order */
		val = be32_to_cpu(val);

		rc = bnx2x_nvram_write_dword(bp, align_offset, val,
					     cmd_flags);
	}

	/* disable access to nvram interface */
	bnx2x_disable_nvram_access(bp);
	bnx2x_release_nvram_lock(bp);

	return rc;
}

static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
			     int buf_size)
{
	int rc;
	u32 cmd_flags;
	u32 val;
	u32 written_so_far;

9283
	if (buf_size == 1)	/* ethtool */
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		return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);

	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
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		DP(BNX2X_MSG_NVM,
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9288
		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
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		   offset, buf_size);
		return -EINVAL;
	}

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	if (offset + buf_size > bp->common.flash_size) {
		DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
9295
				  " buf_size (0x%x) > flash_size (0x%x)\n",
9296
		   offset, buf_size, bp->common.flash_size);
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		return -EINVAL;
	}

	/* request access to nvram interface */
	rc = bnx2x_acquire_nvram_lock(bp);
	if (rc)
		return rc;

	/* enable access to nvram interface */
	bnx2x_enable_nvram_access(bp);

	written_so_far = 0;
	cmd_flags = MCPR_NVM_COMMAND_FIRST;
	while ((written_so_far < buf_size) && (rc == 0)) {
		if (written_so_far == (buf_size - sizeof(u32)))
			cmd_flags |= MCPR_NVM_COMMAND_LAST;
		else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
			cmd_flags |= MCPR_NVM_COMMAND_LAST;
		else if ((offset % NVRAM_PAGE_SIZE) == 0)
			cmd_flags |= MCPR_NVM_COMMAND_FIRST;

		memcpy(&val, data_buf, 4);

		rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);

		/* advance to the next dword */
		offset += sizeof(u32);
		data_buf += sizeof(u32);
		written_so_far += sizeof(u32);
		cmd_flags = 0;
	}

	/* disable access to nvram interface */
	bnx2x_disable_nvram_access(bp);
	bnx2x_release_nvram_lock(bp);

	return rc;
}

static int bnx2x_set_eeprom(struct net_device *dev,
			    struct ethtool_eeprom *eeprom, u8 *eebuf)
{
	struct bnx2x *bp = netdev_priv(dev);
	int rc;

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	if (!netif_running(dev))
		return -EAGAIN;

9345
	DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
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	   DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
	   eeprom->len, eeprom->len);

	/* parameters already validated in ethtool_set_eeprom */

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9352
	/* If the magic number is PHY (0x00504859) upgrade the PHY FW */
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	if (eeprom->magic == 0x00504859)
		if (bp->port.pmf) {

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			bnx2x_acquire_phy_lock(bp);
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			rc = bnx2x_flash_download(bp, BP_PORT(bp),
					     bp->link_params.ext_phy_config,
					     (bp->state != BNX2X_STATE_CLOSED),
					     eebuf, eeprom->len);
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			if ((bp->state == BNX2X_STATE_OPEN) ||
			    (bp->state == BNX2X_STATE_DISABLED)) {
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				rc |= bnx2x_link_reset(&bp->link_params,
9364
						       &bp->link_vars, 1);
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				rc |= bnx2x_phy_init(&bp->link_params,
						     &bp->link_vars);
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			}
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			bnx2x_release_phy_lock(bp);
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		} else /* Only the PMF can access the PHY */
			return -EINVAL;
	else
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		rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
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	return rc;
}

static int bnx2x_get_coalesce(struct net_device *dev,
			      struct ethtool_coalesce *coal)
{
	struct bnx2x *bp = netdev_priv(dev);

	memset(coal, 0, sizeof(struct ethtool_coalesce));

	coal->rx_coalesce_usecs = bp->rx_ticks;
	coal->tx_coalesce_usecs = bp->tx_ticks;

	return 0;
}

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9391
#define BNX2X_MAX_COALES_TOUT  (0xf0*12) /* Maximal coalescing timeout in us */
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static int bnx2x_set_coalesce(struct net_device *dev,
			      struct ethtool_coalesce *coal)
{
	struct bnx2x *bp = netdev_priv(dev);

	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
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	if (bp->rx_ticks > BNX2X_MAX_COALES_TOUT)
		bp->rx_ticks = BNX2X_MAX_COALES_TOUT;
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	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
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	if (bp->tx_ticks > BNX2X_MAX_COALES_TOUT)
		bp->tx_ticks = BNX2X_MAX_COALES_TOUT;
9404

9405
	if (netif_running(dev))
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		bnx2x_update_coalesce(bp);

	return 0;
}

static void bnx2x_get_ringparam(struct net_device *dev,
				struct ethtool_ringparam *ering)
{
	struct bnx2x *bp = netdev_priv(dev);

	ering->rx_max_pending = MAX_RX_AVAIL;
	ering->rx_mini_max_pending = 0;
	ering->rx_jumbo_max_pending = 0;

	ering->rx_pending = bp->rx_ring_size;
	ering->rx_mini_pending = 0;
	ering->rx_jumbo_pending = 0;

	ering->tx_max_pending = MAX_TX_AVAIL;
	ering->tx_pending = bp->tx_ring_size;
}

static int bnx2x_set_ringparam(struct net_device *dev,
			       struct ethtool_ringparam *ering)
{
	struct bnx2x *bp = netdev_priv(dev);
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	int rc = 0;
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	if ((ering->rx_pending > MAX_RX_AVAIL) ||
	    (ering->tx_pending > MAX_TX_AVAIL) ||
	    (ering->tx_pending <= MAX_SKB_FRAGS + 4))
		return -EINVAL;

	bp->rx_ring_size = ering->rx_pending;
	bp->tx_ring_size = ering->tx_pending;

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	if (netif_running(dev)) {
		bnx2x_nic_unload(bp, UNLOAD_NORMAL);
		rc = bnx2x_nic_load(bp, LOAD_NORMAL);
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	}

9447
	return rc;
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}

static void bnx2x_get_pauseparam(struct net_device *dev,
				 struct ethtool_pauseparam *epause)
{
	struct bnx2x *bp = netdev_priv(dev);

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	epause->autoneg = (bp->link_params.req_flow_ctrl ==
			   BNX2X_FLOW_CTRL_AUTO) &&
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			  (bp->link_params.req_line_speed == SPEED_AUTO_NEG);

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	epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
			    BNX2X_FLOW_CTRL_RX);
	epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
			    BNX2X_FLOW_CTRL_TX);
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	DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
	   DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
}

static int bnx2x_set_pauseparam(struct net_device *dev,
				struct ethtool_pauseparam *epause)
{
	struct bnx2x *bp = netdev_priv(dev);

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	if (IS_E1HMF(bp))
		return 0;

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	DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
	   DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);

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	bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
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	if (epause->rx_pause)
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		bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_RX;
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	if (epause->tx_pause)
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		bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_TX;
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	if (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
		bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
9491

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	if (epause->autoneg) {
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		if (!(bp->port.supported & SUPPORTED_Autoneg)) {
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			DP(NETIF_MSG_LINK, "autoneg not supported\n");
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			return -EINVAL;
		}
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		if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
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			bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
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	}
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	DP(NETIF_MSG_LINK,
	   "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
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	if (netif_running(dev)) {
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		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
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		bnx2x_link_set(bp);
	}
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	return 0;
}

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static int bnx2x_set_flags(struct net_device *dev, u32 data)
{
	struct bnx2x *bp = netdev_priv(dev);
	int changed = 0;
	int rc = 0;

	/* TPA requires Rx CSUM offloading */
	if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
		if (!(dev->features & NETIF_F_LRO)) {
			dev->features |= NETIF_F_LRO;
			bp->flags |= TPA_ENABLE_FLAG;
			changed = 1;
		}

	} else if (dev->features & NETIF_F_LRO) {
		dev->features &= ~NETIF_F_LRO;
		bp->flags &= ~TPA_ENABLE_FLAG;
		changed = 1;
	}

	if (changed && netif_running(dev)) {
		bnx2x_nic_unload(bp, UNLOAD_NORMAL);
		rc = bnx2x_nic_load(bp, LOAD_NORMAL);
	}

	return rc;
}

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static u32 bnx2x_get_rx_csum(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

	return bp->rx_csum;
}

static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
{
	struct bnx2x *bp = netdev_priv(dev);
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	int rc = 0;
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	bp->rx_csum = data;
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	/* Disable TPA, when Rx CSUM is disabled. Otherwise all
	   TPA'ed packets will be discarded due to wrong TCP CSUM */
	if (!data) {
		u32 flags = ethtool_op_get_flags(dev);

		rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
	}

	return rc;
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}

static int bnx2x_set_tso(struct net_device *dev, u32 data)
{
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	if (data) {
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		dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
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		dev->features |= NETIF_F_TSO6;
	} else {
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		dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
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		dev->features &= ~NETIF_F_TSO6;
	}

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	return 0;
}

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static const struct {
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	char string[ETH_GSTRING_LEN];
} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
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	{ "register_test (offline)" },
	{ "memory_test (offline)" },
	{ "loopback_test (offline)" },
	{ "nvram_test (online)" },
	{ "interrupt_test (online)" },
	{ "link_test (online)" },
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	{ "idle check (online)" }
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};

static int bnx2x_self_test_count(struct net_device *dev)
{
	return BNX2X_NUM_TESTS;
}

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static int bnx2x_test_registers(struct bnx2x *bp)
{
	int idx, i, rc = -ENODEV;
	u32 wr_val = 0;
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	int port = BP_PORT(bp);
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	static const struct {
		u32  offset0;
		u32  offset1;
		u32  mask;
	} reg_tbl[] = {
/* 0 */		{ BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
		{ DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
		{ HC_REG_AGG_INT_0,                    4, 0x000003ff },
		{ PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
		{ PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
		{ PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
		{ PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
		{ PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
		{ PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
		{ PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
/* 10 */	{ PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
		{ QM_REG_CONNNUM_0,                    4, 0x000fffff },
		{ TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
		{ SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
		{ SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
		{ XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
		{ XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
		{ XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
		{ NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
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		{ NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
/* 20 */	{ NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
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		{ NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
		{ NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
		{ NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
		{ NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
		{ NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
		{ NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
		{ NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
		{ NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
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		{ NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
/* 30 */	{ NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
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		{ NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
		{ NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
		{ NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
		{ NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
		{ NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
		{ NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },

		{ 0xffffffff, 0, 0x00000000 }
	};

	if (!netif_running(bp->dev))
		return rc;

	/* Repeat the test twice:
	   First by writing 0x00000000, second by writing 0xffffffff */
	for (idx = 0; idx < 2; idx++) {

		switch (idx) {
		case 0:
			wr_val = 0;
			break;
		case 1:
			wr_val = 0xffffffff;
			break;
		}

		for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
			u32 offset, mask, save_val, val;

			offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
			mask = reg_tbl[i].mask;

			save_val = REG_RD(bp, offset);

			REG_WR(bp, offset, wr_val);
			val = REG_RD(bp, offset);

			/* Restore the original register's value */
			REG_WR(bp, offset, save_val);

			/* verify that value is as expected value */
			if ((val & mask) != (wr_val & mask))
				goto test_reg_exit;
		}
	}

	rc = 0;

test_reg_exit:
	return rc;
}

static int bnx2x_test_memory(struct bnx2x *bp)
{
	int i, j, rc = -ENODEV;
	u32 val;
	static const struct {
		u32 offset;
		int size;
	} mem_tbl[] = {
		{ CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
		{ CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
		{ CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
		{ DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
		{ TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
		{ UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
		{ XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },

		{ 0xffffffff, 0 }
	};
	static const struct {
		char *name;
		u32 offset;
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		u32 e1_mask;
		u32 e1h_mask;
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	} prty_tbl[] = {
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		{ "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0 },
		{ "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2 },
		{ "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0 },
		{ "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0 },
		{ "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0 },
		{ "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0 },

		{ NULL, 0xffffffff, 0, 0 }
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	};

	if (!netif_running(bp->dev))
		return rc;

	/* Go through all the memories */
	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
		for (j = 0; j < mem_tbl[i].size; j++)
			REG_RD(bp, mem_tbl[i].offset + j*4);

	/* Check the parity status */
	for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
		val = REG_RD(bp, prty_tbl[i].offset);
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		if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
		    (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
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			DP(NETIF_MSG_HW,
			   "%s is 0x%x\n", prty_tbl[i].name, val);
			goto test_mem_exit;
		}
	}

	rc = 0;

test_mem_exit:
	return rc;
}

static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
{
	int cnt = 1000;

	if (link_up)
		while (bnx2x_link_test(bp) && cnt--)
			msleep(10);
}

static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
{
	unsigned int pkt_size, num_pkts, i;
	struct sk_buff *skb;
	unsigned char *packet;
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	struct bnx2x_fastpath *fp_rx = &bp->fp[0];
	struct bnx2x_fastpath *fp_tx = &bp->fp[bp->num_rx_queues];
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	u16 tx_start_idx, tx_idx;
	u16 rx_start_idx, rx_idx;
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	u16 pkt_prod, bd_prod;
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	struct sw_tx_bd *tx_buf;
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	struct eth_tx_start_bd *tx_start_bd;
	struct eth_tx_parse_bd *pbd = NULL;
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	dma_addr_t mapping;
	union eth_rx_cqe *cqe;
	u8 cqe_fp_flags;
	struct sw_rx_bd *rx_buf;
	u16 len;
	int rc = -ENODEV;

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	/* check the loopback mode */
	switch (loopback_mode) {
	case BNX2X_PHY_LOOPBACK:
		if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10)
			return -EINVAL;
		break;
	case BNX2X_MAC_LOOPBACK:
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		bp->link_params.loopback_mode = LOOPBACK_BMAC;
		bnx2x_phy_init(&bp->link_params, &bp->link_vars);
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		break;
	default:
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		return -EINVAL;
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	}
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	/* prepare the loopback packet */
	pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
		     bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
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	skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
	if (!skb) {
		rc = -ENOMEM;
		goto test_loopback_exit;
	}
	packet = skb_put(skb, pkt_size);
	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
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	memset(packet + ETH_ALEN, 0, ETH_ALEN);
	memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
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	for (i = ETH_HLEN; i < pkt_size; i++)
		packet[i] = (unsigned char) (i & 0xff);

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	/* send the loopback packet */
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	num_pkts = 0;
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	tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
	rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
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	pkt_prod = fp_tx->tx_pkt_prod++;
	tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
	tx_buf->first_bd = fp_tx->tx_bd_prod;
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	tx_buf->skb = skb;
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	tx_buf->flags = 0;
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	bd_prod = TX_BD(fp_tx->tx_bd_prod);
	tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
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	mapping = pci_map_single(bp->pdev, skb->data,
				 skb_headlen(skb), PCI_DMA_TODEVICE);
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	tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
	tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
	tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
	tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
	tx_start_bd->vlan = cpu_to_le16(pkt_prod);
	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
	tx_start_bd->general_data = ((UNICAST_ADDRESS <<
				ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT) | 1);

	/* turn on parsing and get a BD */
	bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
	pbd = &fp_tx->tx_desc_ring[bd_prod].parse_bd;

	memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
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	wmb();

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	fp_tx->tx_db.data.prod += 2;
	barrier();
	DOORBELL(bp, fp_tx->index - bp->num_rx_queues, fp_tx->tx_db.raw);
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	mmiowb();

	num_pkts++;
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	fp_tx->tx_bd_prod += 2; /* start + pbd */
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	bp->dev->trans_start = jiffies;

	udelay(100);

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	tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
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	if (tx_idx != tx_start_idx + num_pkts)
		goto test_loopback_exit;

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	rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
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	if (rx_idx != rx_start_idx + num_pkts)
		goto test_loopback_exit;

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	cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
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	cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
	if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
		goto test_loopback_rx_exit;

	len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
	if (len != pkt_size)
		goto test_loopback_rx_exit;

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	rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
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	skb = rx_buf->skb;
	skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
	for (i = ETH_HLEN; i < pkt_size; i++)
		if (*(skb->data + i) != (unsigned char) (i & 0xff))
			goto test_loopback_rx_exit;

	rc = 0;

test_loopback_rx_exit:

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	fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
	fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
	fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
	fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
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	/* Update producers */
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	bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
			     fp_rx->rx_sge_prod);
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test_loopback_exit:
	bp->link_params.loopback_mode = LOOPBACK_NONE;

	return rc;
}

static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
{
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	int rc = 0, res;
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	if (!netif_running(bp->dev))
		return BNX2X_LOOPBACK_FAILED;

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	bnx2x_netif_stop(bp, 1);
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	bnx2x_acquire_phy_lock(bp);
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	res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
	if (res) {
		DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
		rc |= BNX2X_PHY_LOOPBACK_FAILED;
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	}

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	res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
	if (res) {
		DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
		rc |= BNX2X_MAC_LOOPBACK_FAILED;
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	}

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	bnx2x_release_phy_lock(bp);
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	bnx2x_netif_start(bp);

	return rc;
}

#define CRC32_RESIDUAL			0xdebb20e3

static int bnx2x_test_nvram(struct bnx2x *bp)
{
	static const struct {
		int offset;
		int size;
	} nvram_tbl[] = {
		{     0,  0x14 }, /* bootstrap */
		{  0x14,  0xec }, /* dir */
		{ 0x100, 0x350 }, /* manuf_info */
		{ 0x450,  0xf0 }, /* feature_info */
		{ 0x640,  0x64 }, /* upgrade_key_info */
		{ 0x6a4,  0x64 },
		{ 0x708,  0x70 }, /* manuf_key_info */
		{ 0x778,  0x70 },
		{     0,     0 }
	};
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	__be32 buf[0x350 / 4];
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	u8 *data = (u8 *)buf;
	int i, rc;
	u32 magic, csum;

	rc = bnx2x_nvram_read(bp, 0, data, 4);
	if (rc) {
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		DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
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		goto test_nvram_exit;
	}

	magic = be32_to_cpu(buf[0]);
	if (magic != 0x669955aa) {
		DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
		rc = -ENODEV;
		goto test_nvram_exit;
	}

	for (i = 0; nvram_tbl[i].size; i++) {

		rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
				      nvram_tbl[i].size);
		if (rc) {
			DP(NETIF_MSG_PROBE,
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			   "nvram_tbl[%d] read data (rc %d)\n", i, rc);
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			goto test_nvram_exit;
		}

		csum = ether_crc_le(nvram_tbl[i].size, data);
		if (csum != CRC32_RESIDUAL) {
			DP(NETIF_MSG_PROBE,
			   "nvram_tbl[%d] csum value (0x%08x)\n", i, csum);
			rc = -ENODEV;
			goto test_nvram_exit;
		}
	}

test_nvram_exit:
	return rc;
}

static int bnx2x_test_intr(struct bnx2x *bp)
{
	struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
	int i, rc;

	if (!netif_running(bp->dev))
		return -ENODEV;

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	config->hdr.length = 0;
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	if (CHIP_IS_E1(bp))
		config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
	else
		config->hdr.offset = BP_FUNC(bp);
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	config->hdr.client_id = bp->fp->cl_id;
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	config->hdr.reserved1 = 0;

	rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
			   U64_HI(bnx2x_sp_mapping(bp, mac_config)),
			   U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
	if (rc == 0) {
		bp->set_mac_pending++;
		for (i = 0; i < 10; i++) {
			if (!bp->set_mac_pending)
				break;
			msleep_interruptible(10);
		}
		if (i == 10)
			rc = -ENODEV;
	}

	return rc;
}

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static void bnx2x_self_test(struct net_device *dev,
			    struct ethtool_test *etest, u64 *buf)
{
	struct bnx2x *bp = netdev_priv(dev);

	memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);

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	if (!netif_running(dev))
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		return;

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	/* offline tests are not supported in MF mode */
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	if (IS_E1HMF(bp))
		etest->flags &= ~ETH_TEST_FL_OFFLINE;

	if (etest->flags & ETH_TEST_FL_OFFLINE) {
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		int port = BP_PORT(bp);
		u32 val;
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		u8 link_up;

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		/* save current value of input enable for TX port IF */
		val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
		/* disable input for TX port IF */
		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);

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		link_up = bp->link_vars.link_up;
		bnx2x_nic_unload(bp, UNLOAD_NORMAL);
		bnx2x_nic_load(bp, LOAD_DIAG);
		/* wait until link state is restored */
		bnx2x_wait_for_link(bp, link_up);

		if (bnx2x_test_registers(bp) != 0) {
			buf[0] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
		if (bnx2x_test_memory(bp) != 0) {
			buf[1] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
		buf[2] = bnx2x_test_loopback(bp, link_up);
		if (buf[2] != 0)
			etest->flags |= ETH_TEST_FL_FAILED;
10054

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		bnx2x_nic_unload(bp, UNLOAD_NORMAL);
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		/* restore input for TX port IF */
		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);

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		bnx2x_nic_load(bp, LOAD_NORMAL);
		/* wait until link state is restored */
		bnx2x_wait_for_link(bp, link_up);
	}
	if (bnx2x_test_nvram(bp) != 0) {
		buf[3] = 1;
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		etest->flags |= ETH_TEST_FL_FAILED;
	}
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	if (bnx2x_test_intr(bp) != 0) {
		buf[4] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;
	}
	if (bp->port.pmf)
		if (bnx2x_link_test(bp) != 0) {
			buf[5] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}

#ifdef BNX2X_EXTRA_DEBUG
	bnx2x_panic_dump(bp);
#endif
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}

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static const struct {
	long offset;
	int size;
	u8 string[ETH_GSTRING_LEN];
} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
/* 1 */	{ Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
	{ Q_STATS_OFFSET32(error_bytes_received_hi),
						8, "[%d]: rx_error_bytes" },
	{ Q_STATS_OFFSET32(total_unicast_packets_received_hi),
						8, "[%d]: rx_ucast_packets" },
	{ Q_STATS_OFFSET32(total_multicast_packets_received_hi),
						8, "[%d]: rx_mcast_packets" },
	{ Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
						8, "[%d]: rx_bcast_packets" },
	{ Q_STATS_OFFSET32(no_buff_discard_hi),	8, "[%d]: rx_discards" },
	{ Q_STATS_OFFSET32(rx_err_discard_pkt),
					 4, "[%d]: rx_phy_ip_err_discards"},
	{ Q_STATS_OFFSET32(rx_skb_alloc_failed),
					 4, "[%d]: rx_skb_alloc_discard" },
	{ Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },

/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi),	8, "[%d]: tx_bytes" },
	{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
							8, "[%d]: tx_packets" }
};

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static const struct {
	long offset;
	int size;
	u32 flags;
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#define STATS_FLAGS_PORT		1
#define STATS_FLAGS_FUNC		2
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#define STATS_FLAGS_BOTH		(STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
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	u8 string[ETH_GSTRING_LEN];
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} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
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/* 1 */	{ STATS_OFFSET32(total_bytes_received_hi),
				8, STATS_FLAGS_BOTH, "rx_bytes" },
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	{ STATS_OFFSET32(error_bytes_received_hi),
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				8, STATS_FLAGS_BOTH, "rx_error_bytes" },
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	{ STATS_OFFSET32(total_unicast_packets_received_hi),
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				8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
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	{ STATS_OFFSET32(total_multicast_packets_received_hi),
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				8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
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	{ STATS_OFFSET32(total_broadcast_packets_received_hi),
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				8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
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	{ STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
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				8, STATS_FLAGS_PORT, "rx_crc_errors" },
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	{ STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
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				8, STATS_FLAGS_PORT, "rx_align_errors" },
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	{ STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
				8, STATS_FLAGS_PORT, "rx_undersize_packets" },
	{ STATS_OFFSET32(etherstatsoverrsizepkts_hi),
				8, STATS_FLAGS_PORT, "rx_oversize_packets" },
/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
				8, STATS_FLAGS_PORT, "rx_fragments" },
	{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
				8, STATS_FLAGS_PORT, "rx_jabbers" },
	{ STATS_OFFSET32(no_buff_discard_hi),
				8, STATS_FLAGS_BOTH, "rx_discards" },
	{ STATS_OFFSET32(mac_filter_discard),
				4, STATS_FLAGS_PORT, "rx_filtered_packets" },
	{ STATS_OFFSET32(xxoverflow_discard),
				4, STATS_FLAGS_PORT, "rx_fw_discards" },
	{ STATS_OFFSET32(brb_drop_hi),
				8, STATS_FLAGS_PORT, "rx_brb_discard" },
	{ STATS_OFFSET32(brb_truncate_hi),
				8, STATS_FLAGS_PORT, "rx_brb_truncate" },
	{ STATS_OFFSET32(pause_frames_received_hi),
				8, STATS_FLAGS_PORT, "rx_pause_frames" },
	{ STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
				8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
	{ STATS_OFFSET32(nig_timer_max),
			4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
				4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
	{ STATS_OFFSET32(rx_skb_alloc_failed),
				4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
	{ STATS_OFFSET32(hw_csum_err),
				4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },

	{ STATS_OFFSET32(total_bytes_transmitted_hi),
				8, STATS_FLAGS_BOTH, "tx_bytes" },
	{ STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
				8, STATS_FLAGS_PORT, "tx_error_bytes" },
	{ STATS_OFFSET32(total_unicast_packets_transmitted_hi),
				8, STATS_FLAGS_BOTH, "tx_packets" },
	{ STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
				8, STATS_FLAGS_PORT, "tx_mac_errors" },
	{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
				8, STATS_FLAGS_PORT, "tx_carrier_errors" },
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	{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
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				8, STATS_FLAGS_PORT, "tx_single_collisions" },
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	{ STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
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				8, STATS_FLAGS_PORT, "tx_multi_collisions" },
10177
/* 30 */{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
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				8, STATS_FLAGS_PORT, "tx_deferred" },
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	{ STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
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				8, STATS_FLAGS_PORT, "tx_excess_collisions" },
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	{ STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
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				8, STATS_FLAGS_PORT, "tx_late_collisions" },
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	{ STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
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				8, STATS_FLAGS_PORT, "tx_total_collisions" },
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	{ STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
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				8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
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	{ STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
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			8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
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	{ STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
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			8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
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	{ STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
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			8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
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	{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
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			8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
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	{ STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
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			8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
10197
/* 40 */{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
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			8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
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	{ STATS_OFFSET32(pause_frames_sent_hi),
				8, STATS_FLAGS_PORT, "tx_pause_frames" }
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};

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#define IS_PORT_STAT(i) \
	((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
#define IS_FUNC_STAT(i)		(bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
#define IS_E1HMF_MODE_STAT(bp) \
			(IS_E1HMF(bp) && !(bp->msglevel & BNX2X_MSG_STATS))
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static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
{
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	struct bnx2x *bp = netdev_priv(dev);
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	int i, j, k;
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	switch (stringset) {
	case ETH_SS_STATS:
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		if (is_multi(bp)) {
			k = 0;
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			for_each_rx_queue(bp, i) {
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				for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
					sprintf(buf + (k + j)*ETH_GSTRING_LEN,
						bnx2x_q_stats_arr[j].string, i);
				k += BNX2X_NUM_Q_STATS;
			}
			if (IS_E1HMF_MODE_STAT(bp))
				break;
			for (j = 0; j < BNX2X_NUM_STATS; j++)
				strcpy(buf + (k + j)*ETH_GSTRING_LEN,
				       bnx2x_stats_arr[j].string);
		} else {
			for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
				if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
					continue;
				strcpy(buf + j*ETH_GSTRING_LEN,
				       bnx2x_stats_arr[i].string);
				j++;
			}
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		}
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		break;

	case ETH_SS_TEST:
		memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
		break;
	}
}

static int bnx2x_get_stats_count(struct net_device *dev)
{
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	struct bnx2x *bp = netdev_priv(dev);
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	int i, num_stats;
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10251
	if (is_multi(bp)) {
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		num_stats = BNX2X_NUM_Q_STATS * bp->num_rx_queues;
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		if (!IS_E1HMF_MODE_STAT(bp))
			num_stats += BNX2X_NUM_STATS;
	} else {
		if (IS_E1HMF_MODE_STAT(bp)) {
			num_stats = 0;
			for (i = 0; i < BNX2X_NUM_STATS; i++)
				if (IS_FUNC_STAT(i))
					num_stats++;
		} else
			num_stats = BNX2X_NUM_STATS;
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	}
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	return num_stats;
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}

static void bnx2x_get_ethtool_stats(struct net_device *dev,
				    struct ethtool_stats *stats, u64 *buf)
{
	struct bnx2x *bp = netdev_priv(dev);
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	u32 *hw_stats, *offset;
	int i, j, k;
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	if (is_multi(bp)) {
		k = 0;
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		for_each_rx_queue(bp, i) {
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			hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
			for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
				if (bnx2x_q_stats_arr[j].size == 0) {
					/* skip this counter */
					buf[k + j] = 0;
					continue;
				}
				offset = (hw_stats +
					  bnx2x_q_stats_arr[j].offset);
				if (bnx2x_q_stats_arr[j].size == 4) {
					/* 4-byte counter */
					buf[k + j] = (u64) *offset;
					continue;
				}
				/* 8-byte counter */
				buf[k + j] = HILO_U64(*offset, *(offset + 1));
			}
			k += BNX2X_NUM_Q_STATS;
		}
		if (IS_E1HMF_MODE_STAT(bp))
			return;
		hw_stats = (u32 *)&bp->eth_stats;
		for (j = 0; j < BNX2X_NUM_STATS; j++) {
			if (bnx2x_stats_arr[j].size == 0) {
				/* skip this counter */
				buf[k + j] = 0;
				continue;
			}
			offset = (hw_stats + bnx2x_stats_arr[j].offset);
			if (bnx2x_stats_arr[j].size == 4) {
				/* 4-byte counter */
				buf[k + j] = (u64) *offset;
				continue;
			}
			/* 8-byte counter */
			buf[k + j] = HILO_U64(*offset, *(offset + 1));
10314
		}
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	} else {
		hw_stats = (u32 *)&bp->eth_stats;
		for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
			if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
				continue;
			if (bnx2x_stats_arr[i].size == 0) {
				/* skip this counter */
				buf[j] = 0;
				j++;
				continue;
			}
			offset = (hw_stats + bnx2x_stats_arr[i].offset);
			if (bnx2x_stats_arr[i].size == 4) {
				/* 4-byte counter */
				buf[j] = (u64) *offset;
				j++;
				continue;
			}
			/* 8-byte counter */
			buf[j] = HILO_U64(*offset, *(offset + 1));
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10335
			j++;
10336 10337 10338 10339 10340 10341 10342
		}
	}
}

static int bnx2x_phys_id(struct net_device *dev, u32 data)
{
	struct bnx2x *bp = netdev_priv(dev);
10343
	int port = BP_PORT(bp);
10344 10345
	int i;

10346 10347 10348 10349 10350 10351
	if (!netif_running(dev))
		return 0;

	if (!bp->port.pmf)
		return 0;

10352 10353 10354 10355
	if (data == 0)
		data = 2;

	for (i = 0; i < (data * 2); i++) {
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10356
		if ((i % 2) == 0)
10357
			bnx2x_set_led(bp, port, LED_MODE_OPER, SPEED_1000,
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10358 10359 10360
				      bp->link_params.hw_led_mode,
				      bp->link_params.chip_id);
		else
10361
			bnx2x_set_led(bp, port, LED_MODE_OFF, 0,
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10362 10363 10364
				      bp->link_params.hw_led_mode,
				      bp->link_params.chip_id);

10365 10366 10367 10368 10369
		msleep_interruptible(500);
		if (signal_pending(current))
			break;
	}

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10370
	if (bp->link_vars.link_up)
10371
		bnx2x_set_led(bp, port, LED_MODE_OPER,
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10372 10373 10374
			      bp->link_vars.line_speed,
			      bp->link_params.hw_led_mode,
			      bp->link_params.chip_id);
10375 10376 10377 10378 10379

	return 0;
}

static struct ethtool_ops bnx2x_ethtool_ops = {
10380 10381 10382
	.get_settings		= bnx2x_get_settings,
	.set_settings		= bnx2x_set_settings,
	.get_drvinfo		= bnx2x_get_drvinfo,
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10383 10384
	.get_regs_len		= bnx2x_get_regs_len,
	.get_regs		= bnx2x_get_regs,
10385 10386
	.get_wol		= bnx2x_get_wol,
	.set_wol		= bnx2x_set_wol,
10387 10388 10389
	.get_msglevel		= bnx2x_get_msglevel,
	.set_msglevel		= bnx2x_set_msglevel,
	.nway_reset		= bnx2x_nway_reset,
10390
	.get_link		= bnx2x_get_link,
10391 10392 10393 10394 10395 10396 10397 10398 10399 10400 10401 10402
	.get_eeprom_len		= bnx2x_get_eeprom_len,
	.get_eeprom		= bnx2x_get_eeprom,
	.set_eeprom		= bnx2x_set_eeprom,
	.get_coalesce		= bnx2x_get_coalesce,
	.set_coalesce		= bnx2x_set_coalesce,
	.get_ringparam		= bnx2x_get_ringparam,
	.set_ringparam		= bnx2x_set_ringparam,
	.get_pauseparam		= bnx2x_get_pauseparam,
	.set_pauseparam		= bnx2x_set_pauseparam,
	.get_rx_csum		= bnx2x_get_rx_csum,
	.set_rx_csum		= bnx2x_set_rx_csum,
	.get_tx_csum		= ethtool_op_get_tx_csum,
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10403
	.set_tx_csum		= ethtool_op_set_tx_hw_csum,
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	.set_flags		= bnx2x_set_flags,
	.get_flags		= ethtool_op_get_flags,
	.get_sg			= ethtool_op_get_sg,
	.set_sg			= ethtool_op_set_sg,
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	.get_tso		= ethtool_op_get_tso,
	.set_tso		= bnx2x_set_tso,
	.self_test_count	= bnx2x_self_test_count,
10411 10412
	.self_test		= bnx2x_self_test,
	.get_strings		= bnx2x_get_strings,
10413 10414
	.phys_id		= bnx2x_phys_id,
	.get_stats_count	= bnx2x_get_stats_count,
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	.get_ethtool_stats	= bnx2x_get_ethtool_stats,
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};

/* end of ethtool_ops */

/****************************************************************************
* General service functions
****************************************************************************/

static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
{
	u16 pmcsr;

	pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);

	switch (state) {
	case PCI_D0:
10432
		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
10433 10434 10435 10436
				      ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
				       PCI_PM_CTRL_PME_STATUS));

		if (pmcsr & PCI_PM_CTRL_STATE_MASK)
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10437
			/* delay required during transition out of D3hot */
10438
			msleep(20);
10439
		break;
10440

10441 10442 10443
	case PCI_D3hot:
		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
		pmcsr |= 3;
10444

10445 10446
		if (bp->wol)
			pmcsr |= PCI_PM_CTRL_PME_ENABLE;
10447

10448 10449
		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
				      pmcsr);
10450

10451 10452 10453 10454 10455 10456 10457 10458 10459
		/* No more memory access after this point until
		* device is brought back to D0.
		*/
		break;

	default:
		return -EINVAL;
	}
	return 0;
10460 10461
}

10462 10463 10464 10465 10466 10467 10468 10469 10470 10471 10472 10473
static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
{
	u16 rx_cons_sb;

	/* Tell compiler that status block fields can change */
	barrier();
	rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
	if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
		rx_cons_sb++;
	return (fp->rx_comp_cons != rx_cons_sb);
}

10474 10475 10476 10477
/*
 * net_device service functions
 */

10478 10479 10480 10481 10482 10483 10484 10485 10486
static int bnx2x_poll(struct napi_struct *napi, int budget)
{
	struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
						 napi);
	struct bnx2x *bp = fp->bp;
	int work_done = 0;

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
10487
		goto poll_panic;
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#endif

	prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
	prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);

	bnx2x_update_fpsb_idx(fp);

10495
	if (bnx2x_has_rx_work(fp)) {
10496
		work_done = bnx2x_rx_int(fp, budget);
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10498 10499 10500 10501
		/* must not complete if we consumed full budget */
		if (work_done >= budget)
			goto poll_again;
	}
10502

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10503
	/* bnx2x_has_rx_work() reads the status block, thus we need to
10504
	 * ensure that status block indices have been actually read
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10505
	 * (bnx2x_update_fpsb_idx) prior to this check (bnx2x_has_rx_work)
10506
	 * so that we won't write the "newer" value of the status block to IGU
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	 * (if there was a DMA right after bnx2x_has_rx_work and
10508 10509 10510 10511 10512 10513
	 * if there is no rmb, the memory reading (bnx2x_update_fpsb_idx)
	 * may be postponed to right before bnx2x_ack_sb). In this case
	 * there will never be another interrupt until there is another update
	 * of the status block, while there is still unhandled work.
	 */
	rmb();
10514

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10515
	if (!bnx2x_has_rx_work(fp)) {
10516
#ifdef BNX2X_STOP_ON_ERROR
10517
poll_panic:
10518
#endif
10519
		napi_complete(napi);
10520

10521
		bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
10522
			     le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
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		bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
10524 10525
			     le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
	}
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10527
poll_again:
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	return work_done;
}

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/* we split the first BD into headers and data BDs
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 * to ease the pain of our fellow microcode engineers
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10534 10535 10536 10537 10538 10539
 * we use one mapping for both BDs
 * So far this has only been observed to happen
 * in Other Operating Systems(TM)
 */
static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
				   struct bnx2x_fastpath *fp,
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10540 10541
				   struct sw_tx_bd *tx_buf,
				   struct eth_tx_start_bd **tx_bd, u16 hlen,
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10542 10543
				   u16 bd_prod, int nbd)
{
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10544
	struct eth_tx_start_bd *h_tx_bd = *tx_bd;
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	struct eth_tx_bd *d_tx_bd;
	dma_addr_t mapping;
	int old_len = le16_to_cpu(h_tx_bd->nbytes);

	/* first fix first BD */
	h_tx_bd->nbd = cpu_to_le16(nbd);
	h_tx_bd->nbytes = cpu_to_le16(hlen);

	DP(NETIF_MSG_TX_QUEUED,	"TSO split header size is %d "
	   "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi,
	   h_tx_bd->addr_lo, h_tx_bd->nbd);

	/* now get a new data BD
	 * (after the pbd) and fill it */
	bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
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10560
	d_tx_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
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10561 10562 10563 10564 10565 10566 10567

	mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
			   le32_to_cpu(h_tx_bd->addr_lo)) + hlen;

	d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
	d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
	d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
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	/* this marks the BD as one that has no individual mapping */
	tx_buf->flags |= BNX2X_TSO_SPLIT_BD;

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	DP(NETIF_MSG_TX_QUEUED,
	   "TSO split data size is %d (%x:%x)\n",
	   d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);

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10576 10577
	/* update tx_bd */
	*tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
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	return bd_prod;
}

static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
{
	if (fix > 0)
		csum = (u16) ~csum_fold(csum_sub(csum,
				csum_partial(t_header - fix, fix, 0)));

	else if (fix < 0)
		csum = (u16) ~csum_fold(csum_add(csum,
				csum_partial(t_header, -fix, 0)));

	return swab16(csum);
}

static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
{
	u32 rc;

	if (skb->ip_summed != CHECKSUM_PARTIAL)
		rc = XMIT_PLAIN;

	else {
10603
		if (skb->protocol == htons(ETH_P_IPV6)) {
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10604 10605 10606 10607 10608 10609 10610 10611 10612 10613 10614 10615 10616 10617 10618 10619 10620 10621 10622 10623
			rc = XMIT_CSUM_V6;
			if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
				rc |= XMIT_CSUM_TCP;

		} else {
			rc = XMIT_CSUM_V4;
			if (ip_hdr(skb)->protocol == IPPROTO_TCP)
				rc |= XMIT_CSUM_TCP;
		}
	}

	if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
		rc |= XMIT_GSO_V4;

	else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
		rc |= XMIT_GSO_V6;

	return rc;
}

10624
#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
10625 10626 10627
/* check if packet requires linearization (packet is too fragmented)
   no need to check fragmentation if page size > 8K (there will be no
   violation to FW restrictions) */
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static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
			     u32 xmit_type)
{
	int to_copy = 0;
	int hlen = 0;
	int first_bd_sz = 0;

	/* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
	if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {

		if (xmit_type & XMIT_GSO) {
			unsigned short lso_mss = skb_shinfo(skb)->gso_size;
			/* Check if LSO packet needs to be copied:
			   3 = 1 (for headers BD) + 2 (for PBD and last BD) */
			int wnd_size = MAX_FETCH_BD - 3;
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10643
			/* Number of windows to check */
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			int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
			int wnd_idx = 0;
			int frag_idx = 0;
			u32 wnd_sum = 0;

			/* Headers length */
			hlen = (int)(skb_transport_header(skb) - skb->data) +
				tcp_hdrlen(skb);

			/* Amount of data (w/o headers) on linear part of SKB*/
			first_bd_sz = skb_headlen(skb) - hlen;

			wnd_sum  = first_bd_sz;

			/* Calculate the first sum - it's special */
			for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
				wnd_sum +=
					skb_shinfo(skb)->frags[frag_idx].size;

			/* If there was data on linear skb data - check it */
			if (first_bd_sz > 0) {
				if (unlikely(wnd_sum < lso_mss)) {
					to_copy = 1;
					goto exit_lbl;
				}

				wnd_sum -= first_bd_sz;
			}

			/* Others are easier: run through the frag list and
			   check all windows */
			for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
				wnd_sum +=
			  skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1].size;

				if (unlikely(wnd_sum < lso_mss)) {
					to_copy = 1;
					break;
				}
				wnd_sum -=
					skb_shinfo(skb)->frags[wnd_idx].size;
			}
		} else {
			/* in non-LSO too fragmented packet should always
			   be linearized */
			to_copy = 1;
		}
	}

exit_lbl:
	if (unlikely(to_copy))
		DP(NETIF_MSG_TX_QUEUED,
		   "Linearization IS REQUIRED for %s packet. "
		   "num_frags %d  hlen %d  first_bd_sz %d\n",
		   (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
		   skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);

	return to_copy;
}
10703
#endif
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10704 10705

/* called with netif_tx_lock
10706
 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
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 * netif_wake_queue()
10708 10709 10710 10711
 */
static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);
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10712
	struct bnx2x_fastpath *fp, *fp_stat;
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	struct netdev_queue *txq;
10714
	struct sw_tx_bd *tx_buf;
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	struct eth_tx_start_bd *tx_start_bd;
	struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
10717 10718
	struct eth_tx_parse_bd *pbd = NULL;
	u16 pkt_prod, bd_prod;
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10719
	int nbd, fp_index;
10720
	dma_addr_t mapping;
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	u32 xmit_type = bnx2x_xmit_type(bp, skb);
	int i;
	u8 hlen = 0;
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	__le16 pkt_size = 0;
10725 10726 10727 10728 10729 10730

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return NETDEV_TX_BUSY;
#endif

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	fp_index = skb_get_queue_mapping(skb);
	txq = netdev_get_tx_queue(dev, fp_index);

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	fp = &bp->fp[fp_index + bp->num_rx_queues];
	fp_stat = &bp->fp[fp_index];
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10736

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10737
	if (unlikely(bnx2x_tx_avail(fp) < (skb_shinfo(skb)->nr_frags + 3))) {
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10738
		fp_stat->eth_q_stats.driver_xoff++;
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10739
		netif_tx_stop_queue(txq);
10740 10741 10742 10743
		BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
		return NETDEV_TX_BUSY;
	}

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	DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x  protocol %x  protocol(%x,%x)"
	   "  gso type %x  xmit_type %x\n",
	   skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
	   ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);

10749
#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
10750 10751 10752
	/* First, check if we need to linearize the skb (due to FW
	   restrictions). No need to check fragmentation if page size > 8K
	   (there will be no violation to FW restrictions) */
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	if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
		/* Statistics of linearization */
		bp->lin_cnt++;
		if (skb_linearize(skb) != 0) {
			DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
			   "silently dropping this SKB\n");
			dev_kfree_skb_any(skb);
10760
			return NETDEV_TX_OK;
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10761 10762
		}
	}
10763
#endif
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10764

10765
	/*
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10766
	Please read carefully. First we use one BD which we mark as start,
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10767
	then we have a parsing info BD (used for TSO or xsum),
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	and only then we have the rest of the TSO BDs.
10769 10770
	(don't forget to mark the last one as last,
	and to unmap only AFTER you write to the BD ...)
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10771
	And above all, all pdb sizes are in words - NOT DWORDS!
10772 10773 10774
	*/

	pkt_prod = fp->tx_pkt_prod++;
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10775
	bd_prod = TX_BD(fp->tx_bd_prod);
10776

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10777
	/* get a tx_buf and first BD */
10778
	tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
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10779
	tx_start_bd = &fp->tx_desc_ring[bd_prod].start_bd;
10780

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10781 10782 10783
	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
	tx_start_bd->general_data = (UNICAST_ADDRESS <<
				     ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
10784
	/* header nbd */
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10785
	tx_start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
10786

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10787 10788 10789
	/* remember the first BD of the packet */
	tx_buf->first_bd = fp->tx_bd_prod;
	tx_buf->skb = skb;
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10790
	tx_buf->flags = 0;
10791 10792 10793

	DP(NETIF_MSG_TX_QUEUED,
	   "sending pkt %u @%p  next_idx %u  bd %u @%p\n",
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10794
	   pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
10795

10796 10797 10798
#ifdef BCM_VLAN
	if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb) &&
	    (bp->flags & HW_VLAN_TX_FLAG)) {
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10799 10800
		tx_start_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
		tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
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10801
	} else
10802
#endif
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10803
		tx_start_bd->vlan = cpu_to_le16(pkt_prod);
10804

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10805 10806 10807
	/* turn on parsing and get a BD */
	bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
	pbd = &fp->tx_desc_ring[bd_prod].parse_bd;
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10808

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10809
	memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
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10810 10811

	if (xmit_type & XMIT_CSUM) {
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10812
		hlen = (skb_network_header(skb) - skb->data) / 2;
10813 10814

		/* for now NS flag is not used in Linux */
10815 10816 10817
		pbd->global_data =
			(hlen | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
				 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
10818

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10819 10820 10821 10822
		pbd->ip_hlen = (skb_transport_header(skb) -
				skb_network_header(skb)) / 2;

		hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
10823

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10824
		pbd->total_hlen = cpu_to_le16(hlen);
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10825
		hlen = hlen*2;
10826

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10827
		tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
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10828 10829

		if (xmit_type & XMIT_CSUM_V4)
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10830
			tx_start_bd->bd_flags.as_bitfield |=
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10831 10832
						ETH_TX_BD_FLAGS_IP_CSUM;
		else
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10833 10834
			tx_start_bd->bd_flags.as_bitfield |=
						ETH_TX_BD_FLAGS_IPV6;
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10835 10836 10837 10838 10839 10840 10841

		if (xmit_type & XMIT_CSUM_TCP) {
			pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);

		} else {
			s8 fix = SKB_CS_OFF(skb); /* signed! */

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10842
			pbd->global_data |= ETH_TX_PARSE_BD_UDP_CS_FLG;
10843

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10844
			DP(NETIF_MSG_TX_QUEUED,
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10845 10846
			   "hlen %d  fix %d  csum before fix %x\n",
			   le16_to_cpu(pbd->total_hlen), fix, SKB_CS(skb));
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10847 10848 10849 10850 10851 10852 10853 10854 10855

			/* HW bug: fixup the CSUM */
			pbd->tcp_pseudo_csum =
				bnx2x_csum_fix(skb_transport_header(skb),
					       SKB_CS(skb), fix);

			DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
			   pbd->tcp_pseudo_csum);
		}
10856 10857 10858
	}

	mapping = pci_map_single(bp->pdev, skb->data,
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10859
				 skb_headlen(skb), PCI_DMA_TODEVICE);
10860

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10861 10862 10863 10864 10865 10866
	tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
	tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
	nbd = skb_shinfo(skb)->nr_frags + 2; /* start_bd + pbd + frags */
	tx_start_bd->nbd = cpu_to_le16(nbd);
	tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
	pkt_size = tx_start_bd->nbytes;
10867 10868

	DP(NETIF_MSG_TX_QUEUED, "first bd @%p  addr (%x:%x)  nbd %d"
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10869
	   "  nbytes %d  flags %x  vlan %x\n",
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10870 10871 10872
	   tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
	   le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
	   tx_start_bd->bd_flags.as_bitfield, le16_to_cpu(tx_start_bd->vlan));
10873

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10874
	if (xmit_type & XMIT_GSO) {
10875 10876 10877 10878 10879 10880

		DP(NETIF_MSG_TX_QUEUED,
		   "TSO packet len %d  hlen %d  total len %d  tso size %d\n",
		   skb->len, hlen, skb_headlen(skb),
		   skb_shinfo(skb)->gso_size);

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10881
		tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
10882

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10883
		if (unlikely(skb_headlen(skb) > hlen))
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10884 10885
			bd_prod = bnx2x_tx_split(bp, fp, tx_buf, &tx_start_bd,
						 hlen, bd_prod, ++nbd);
10886 10887 10888

		pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
		pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
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10889 10890 10891 10892 10893
		pbd->tcp_flags = pbd_tcp_flags(skb);

		if (xmit_type & XMIT_GSO_V4) {
			pbd->ip_id = swab16(ip_hdr(skb)->id);
			pbd->tcp_pseudo_csum =
10894 10895 10896
				swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
							  ip_hdr(skb)->daddr,
							  0, IPPROTO_TCP, 0));
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10897 10898 10899 10900 10901 10902 10903

		} else
			pbd->tcp_pseudo_csum =
				swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
							&ipv6_hdr(skb)->daddr,
							0, IPPROTO_TCP, 0));

10904 10905
		pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
	}
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10906
	tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
10907

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10908 10909
	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
10910

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10911
		bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
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10912 10913 10914
		tx_data_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
		if (total_pkt_bd == NULL)
			total_pkt_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
10915

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10916 10917
		mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
				       frag->size, PCI_DMA_TODEVICE);
10918

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10919 10920 10921 10922
		tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
		tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
		tx_data_bd->nbytes = cpu_to_le16(frag->size);
		le16_add_cpu(&pkt_size, frag->size);
10923

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10924
		DP(NETIF_MSG_TX_QUEUED,
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10925 10926 10927
		   "frag %d  bd @%p  addr (%x:%x)  nbytes %d\n",
		   i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
		   le16_to_cpu(tx_data_bd->nbytes));
10928 10929
	}

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10930
	DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
10931 10932 10933

	bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));

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10934
	/* now send a tx doorbell, counting the next BD
10935 10936 10937 10938 10939
	 * if the packet contains or ends with it
	 */
	if (TX_BD_POFF(bd_prod) < nbd)
		nbd++;

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10940 10941 10942
	if (total_pkt_bd != NULL)
		total_pkt_bd->total_pkt_bytes = pkt_size;

10943 10944 10945 10946 10947 10948
	if (pbd)
		DP(NETIF_MSG_TX_QUEUED,
		   "PBD @%p  ip_data %x  ip_hlen %u  ip_id %u  lso_mss %u"
		   "  tcp_flags %x  xsum %x  seq %u  hlen %u\n",
		   pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
		   pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
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10949
		   pbd->tcp_send_seq, le16_to_cpu(pbd->total_hlen));
10950

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10951
	DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d  bd %u\n", nbd, bd_prod);
10952

10953 10954 10955 10956 10957 10958 10959 10960 10961
	/*
	 * Make sure that the BD data is updated before updating the producer
	 * since FW might read the BD right after the producer is updated.
	 * This is only applicable for weak-ordered memory model archs such
	 * as IA-64. The following barrier is also mandatory since FW will
	 * assumes packets must have BDs.
	 */
	wmb();

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10962 10963 10964
	fp->tx_db.data.prod += nbd;
	barrier();
	DOORBELL(bp, fp->index - bp->num_rx_queues, fp->tx_db.raw);
10965 10966 10967

	mmiowb();

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10968
	fp->tx_bd_prod += nbd;
10969 10970

	if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
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10971
		netif_tx_stop_queue(txq);
10972 10973 10974
		/* We want bnx2x_tx_int to "see" the updated tx_bd_prod
		   if we put Tx into XOFF state. */
		smp_mb();
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10975
		fp_stat->eth_q_stats.driver_xoff++;
10976
		if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
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10977
			netif_tx_wake_queue(txq);
10978
	}
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10979
	fp_stat->tx_pkt++;
10980 10981 10982 10983

	return NETDEV_TX_OK;
}

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Yitchak Gertner committed
10984
/* called with rtnl_lock */
10985 10986 10987 10988
static int bnx2x_open(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

10989 10990
	netif_carrier_off(dev);

10991 10992
	bnx2x_set_power_state(bp, PCI_D0);

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Yitchak Gertner committed
10993
	return bnx2x_nic_load(bp, LOAD_OPEN);
10994 10995
}

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Yitchak Gertner committed
10996
/* called with rtnl_lock */
10997 10998 10999 11000 11001
static int bnx2x_close(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

	/* Unload the driver, release IRQs */
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11002 11003 11004 11005
	bnx2x_nic_unload(bp, UNLOAD_CLOSE);
	if (atomic_read(&bp->pdev->enable_cnt) == 1)
		if (!CHIP_REV_IS_SLOW(bp))
			bnx2x_set_power_state(bp, PCI_D3hot);
11006 11007 11008 11009

	return 0;
}

11010
/* called with netif_tx_lock from dev_mcast.c */
11011 11012 11013 11014 11015 11016 11017 11018 11019 11020 11021 11022 11023 11024 11025 11026 11027 11028 11029 11030 11031 11032 11033 11034 11035 11036 11037 11038 11039 11040 11041 11042 11043 11044 11045 11046 11047 11048 11049 11050 11051 11052 11053 11054
static void bnx2x_set_rx_mode(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);
	u32 rx_mode = BNX2X_RX_MODE_NORMAL;
	int port = BP_PORT(bp);

	if (bp->state != BNX2X_STATE_OPEN) {
		DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
		return;
	}

	DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);

	if (dev->flags & IFF_PROMISC)
		rx_mode = BNX2X_RX_MODE_PROMISC;

	else if ((dev->flags & IFF_ALLMULTI) ||
		 ((dev->mc_count > BNX2X_MAX_MULTICAST) && CHIP_IS_E1(bp)))
		rx_mode = BNX2X_RX_MODE_ALLMULTI;

	else { /* some multicasts */
		if (CHIP_IS_E1(bp)) {
			int i, old, offset;
			struct dev_mc_list *mclist;
			struct mac_configuration_cmd *config =
						bnx2x_sp(bp, mcast_config);

			for (i = 0, mclist = dev->mc_list;
			     mclist && (i < dev->mc_count);
			     i++, mclist = mclist->next) {

				config->config_table[i].
					cam_entry.msb_mac_addr =
					swab16(*(u16 *)&mclist->dmi_addr[0]);
				config->config_table[i].
					cam_entry.middle_mac_addr =
					swab16(*(u16 *)&mclist->dmi_addr[2]);
				config->config_table[i].
					cam_entry.lsb_mac_addr =
					swab16(*(u16 *)&mclist->dmi_addr[4]);
				config->config_table[i].cam_entry.flags =
							cpu_to_le16(port);
				config->config_table[i].
					target_table_entry.flags = 0;
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11055 11056 11057
				config->config_table[i].target_table_entry.
					clients_bit_vector =
						cpu_to_le32(1 << BP_L_ID(bp));
11058 11059 11060 11061 11062 11063 11064 11065 11066 11067 11068 11069
				config->config_table[i].
					target_table_entry.vlan_id = 0;

				DP(NETIF_MSG_IFUP,
				   "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
				   config->config_table[i].
						cam_entry.msb_mac_addr,
				   config->config_table[i].
						cam_entry.middle_mac_addr,
				   config->config_table[i].
						cam_entry.lsb_mac_addr);
			}
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11070
			old = config->hdr.length;
11071 11072 11073 11074
			if (old > i) {
				for (; i < old; i++) {
					if (CAM_IS_INVALID(config->
							   config_table[i])) {
11075
						/* already invalidated */
11076 11077 11078 11079 11080 11081 11082 11083 11084 11085 11086 11087 11088
						break;
					}
					/* invalidate */
					CAM_INVALIDATE(config->
						       config_table[i]);
				}
			}

			if (CHIP_REV_IS_SLOW(bp))
				offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
			else
				offset = BNX2X_MAX_MULTICAST*(1 + port);

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11089
			config->hdr.length = i;
11090
			config->hdr.offset = offset;
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11091
			config->hdr.client_id = bp->fp->cl_id;
11092 11093 11094 11095 11096 11097 11098 11099 11100 11101 11102 11103 11104 11105 11106 11107 11108 11109 11110
			config->hdr.reserved1 = 0;

			bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
				   U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
				   U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
				      0);
		} else { /* E1H */
			/* Accept one or more multicasts */
			struct dev_mc_list *mclist;
			u32 mc_filter[MC_HASH_SIZE];
			u32 crc, bit, regidx;
			int i;

			memset(mc_filter, 0, 4 * MC_HASH_SIZE);

			for (i = 0, mclist = dev->mc_list;
			     mclist && (i < dev->mc_count);
			     i++, mclist = mclist->next) {

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11111 11112
				DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
				   mclist->dmi_addr);
11113 11114 11115 11116 11117 11118 11119 11120 11121 11122 11123 11124 11125 11126 11127 11128 11129 11130 11131

				crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN);
				bit = (crc >> 24) & 0xff;
				regidx = bit >> 5;
				bit &= 0x1f;
				mc_filter[regidx] |= (1 << bit);
			}

			for (i = 0; i < MC_HASH_SIZE; i++)
				REG_WR(bp, MC_HASH_OFFSET(bp, i),
				       mc_filter[i]);
		}
	}

	bp->rx_mode = rx_mode;
	bnx2x_set_storm_rx_mode(bp);
}

/* called with rtnl_lock */
11132 11133 11134 11135 11136
static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
{
	struct sockaddr *addr = p;
	struct bnx2x *bp = netdev_priv(dev);

11137
	if (!is_valid_ether_addr((u8 *)(addr->sa_data)))
11138 11139 11140
		return -EINVAL;

	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
11141 11142
	if (netif_running(dev)) {
		if (CHIP_IS_E1(bp))
11143
			bnx2x_set_mac_addr_e1(bp, 1);
11144
		else
11145
			bnx2x_set_mac_addr_e1h(bp, 1);
11146
	}
11147 11148 11149 11150

	return 0;
}

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11151
/* called with rtnl_lock */
11152 11153 11154 11155
static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct mii_ioctl_data *data = if_mii(ifr);
	struct bnx2x *bp = netdev_priv(dev);
11156
	int port = BP_PORT(bp);
11157 11158 11159 11160
	int err;

	switch (cmd) {
	case SIOCGMIIPHY:
11161
		data->phy_id = bp->port.phy_addr;
11162

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11163
		/* fallthrough */
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11164

11165
	case SIOCGMIIREG: {
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11166
		u16 mii_regval;
11167

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11168 11169
		if (!netif_running(dev))
			return -EAGAIN;
11170

11171
		mutex_lock(&bp->port.phy_mutex);
11172
		err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr,
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11173 11174 11175
				      DEFAULT_PHY_DEV_ADDR,
				      (data->reg_num & 0x1f), &mii_regval);
		data->val_out = mii_regval;
11176
		mutex_unlock(&bp->port.phy_mutex);
11177 11178 11179 11180 11181 11182 11183
		return err;
	}

	case SIOCSMIIREG:
		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

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11184 11185 11186
		if (!netif_running(dev))
			return -EAGAIN;

11187
		mutex_lock(&bp->port.phy_mutex);
11188
		err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr,
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11189 11190
				       DEFAULT_PHY_DEV_ADDR,
				       (data->reg_num & 0x1f), data->val_in);
11191
		mutex_unlock(&bp->port.phy_mutex);
11192 11193 11194 11195 11196 11197 11198 11199 11200 11201
		return err;

	default:
		/* do nothing */
		break;
	}

	return -EOPNOTSUPP;
}

11202
/* called with rtnl_lock */
11203 11204 11205
static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
{
	struct bnx2x *bp = netdev_priv(dev);
11206
	int rc = 0;
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	if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
	    ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
		return -EINVAL;

	/* This does not race with packet allocation
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11213
	 * because the actual alloc size is
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	 * only updated as part of load
	 */
	dev->mtu = new_mtu;

	if (netif_running(dev)) {
11219 11220
		bnx2x_nic_unload(bp, UNLOAD_NORMAL);
		rc = bnx2x_nic_load(bp, LOAD_NORMAL);
11221
	}
11222 11223

	return rc;
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}

static void bnx2x_tx_timeout(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

#ifdef BNX2X_STOP_ON_ERROR
	if (!bp->panic)
		bnx2x_panic();
#endif
	/* This allows the netif to be shutdown gracefully before resetting */
	schedule_work(&bp->reset_task);
}

#ifdef BCM_VLAN
11239
/* called with rtnl_lock */
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static void bnx2x_vlan_rx_register(struct net_device *dev,
				   struct vlan_group *vlgrp)
{
	struct bnx2x *bp = netdev_priv(dev);

	bp->vlgrp = vlgrp;
11246 11247 11248 11249 11250 11251 11252 11253 11254 11255

	/* Set flags according to the required capabilities */
	bp->flags &= ~(HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);

	if (dev->features & NETIF_F_HW_VLAN_TX)
		bp->flags |= HW_VLAN_TX_FLAG;

	if (dev->features & NETIF_F_HW_VLAN_RX)
		bp->flags |= HW_VLAN_RX_FLAG;

11256
	if (netif_running(dev))
11257
		bnx2x_set_client_config(bp);
11258
}
11259

11260 11261 11262 11263 11264 11265 11266 11267 11268 11269 11270 11271 11272
#endif

#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
static void poll_bnx2x(struct net_device *dev)
{
	struct bnx2x *bp = netdev_priv(dev);

	disable_irq(bp->pdev->irq);
	bnx2x_interrupt(bp->pdev->irq, dev);
	enable_irq(bp->pdev->irq);
}
#endif

11273 11274 11275 11276
static const struct net_device_ops bnx2x_netdev_ops = {
	.ndo_open		= bnx2x_open,
	.ndo_stop		= bnx2x_close,
	.ndo_start_xmit		= bnx2x_start_xmit,
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	.ndo_set_multicast_list	= bnx2x_set_rx_mode,
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	.ndo_set_mac_address	= bnx2x_change_mac_addr,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_do_ioctl		= bnx2x_ioctl,
	.ndo_change_mtu		= bnx2x_change_mtu,
	.ndo_tx_timeout		= bnx2x_tx_timeout,
#ifdef BCM_VLAN
	.ndo_vlan_rx_register	= bnx2x_vlan_rx_register,
#endif
#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
	.ndo_poll_controller	= poll_bnx2x,
#endif
};

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static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
				    struct net_device *dev)
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{
	struct bnx2x *bp;
	int rc;

	SET_NETDEV_DEV(dev, &pdev->dev);
	bp = netdev_priv(dev);

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	bp->dev = dev;
	bp->pdev = pdev;
11302
	bp->flags = 0;
11303
	bp->func = PCI_FUNC(pdev->devfn);
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	rc = pci_enable_device(pdev);
	if (rc) {
		printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
		goto err_out;
	}

	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
		printk(KERN_ERR PFX "Cannot find PCI device base address,"
		       " aborting\n");
		rc = -ENODEV;
		goto err_out_disable;
	}

	if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
		printk(KERN_ERR PFX "Cannot find second PCI device"
		       " base address, aborting\n");
		rc = -ENODEV;
		goto err_out_disable;
	}

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	if (atomic_read(&pdev->enable_cnt) == 1) {
		rc = pci_request_regions(pdev, DRV_MODULE_NAME);
		if (rc) {
			printk(KERN_ERR PFX "Cannot obtain PCI resources,"
			       " aborting\n");
			goto err_out_disable;
		}
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		pci_set_master(pdev);
		pci_save_state(pdev);
	}
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	bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
	if (bp->pm_cap == 0) {
		printk(KERN_ERR PFX "Cannot find power management"
		       " capability, aborting\n");
		rc = -EIO;
		goto err_out_release;
	}

	bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
	if (bp->pcie_cap == 0) {
		printk(KERN_ERR PFX "Cannot find PCI Express capability,"
		       " aborting\n");
		rc = -EIO;
		goto err_out_release;
	}

11353
	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
11354
		bp->flags |= USING_DAC_FLAG;
11355
		if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
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			printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
			       " failed, aborting\n");
			rc = -EIO;
			goto err_out_release;
		}

11362
	} else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
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		printk(KERN_ERR PFX "System does not support DMA,"
		       " aborting\n");
		rc = -EIO;
		goto err_out_release;
	}

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	dev->mem_start = pci_resource_start(pdev, 0);
	dev->base_addr = dev->mem_start;
	dev->mem_end = pci_resource_end(pdev, 0);
11372 11373 11374

	dev->irq = pdev->irq;

11375
	bp->regview = pci_ioremap_bar(pdev, 0);
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	if (!bp->regview) {
		printk(KERN_ERR PFX "Cannot map register space, aborting\n");
		rc = -ENOMEM;
		goto err_out_release;
	}

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	bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
					min_t(u64, BNX2X_DB_SIZE,
					      pci_resource_len(pdev, 2)));
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	if (!bp->doorbells) {
		printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
		rc = -ENOMEM;
		goto err_out_unmap;
	}

	bnx2x_set_power_state(bp, PCI_D0);

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	/* clean indirect addresses */
	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
			       PCICFG_VENDOR_ID_OFFSET);
	REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
	REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
	REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
	REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
11400

11401
	dev->watchdog_timeo = TX_TIMEOUT;
11402

11403
	dev->netdev_ops = &bnx2x_netdev_ops;
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	dev->ethtool_ops = &bnx2x_ethtool_ops;
	dev->features |= NETIF_F_SG;
	dev->features |= NETIF_F_HW_CSUM;
	if (bp->flags & USING_DAC_FLAG)
		dev->features |= NETIF_F_HIGHDMA;
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	dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
	dev->features |= NETIF_F_TSO6;
11411 11412
#ifdef BCM_VLAN
	dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
11413
	bp->flags |= (HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);
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	dev->vlan_features |= NETIF_F_SG;
	dev->vlan_features |= NETIF_F_HW_CSUM;
	if (bp->flags & USING_DAC_FLAG)
		dev->vlan_features |= NETIF_F_HIGHDMA;
	dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
	dev->vlan_features |= NETIF_F_TSO6;
11421
#endif
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	return 0;

err_out_unmap:
	if (bp->regview) {
		iounmap(bp->regview);
		bp->regview = NULL;
	}
	if (bp->doorbells) {
		iounmap(bp->doorbells);
		bp->doorbells = NULL;
	}

err_out_release:
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	if (atomic_read(&pdev->enable_cnt) == 1)
		pci_release_regions(pdev);
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err_out_disable:
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);

err_out:
	return rc;
}

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static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp)
{
	u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);

	val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
	return val;
}

/* return value of 1=2.5GHz 2=5GHz */
static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp)
{
	u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);

	val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
	return val;
}
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static int __devinit bnx2x_check_firmware(struct bnx2x *bp)
{
	struct bnx2x_fw_file_hdr *fw_hdr;
	struct bnx2x_fw_file_section *sections;
	u16 *ops_offsets;
	u32 offset, len, num_ops;
	int i;
	const struct firmware *firmware = bp->firmware;
	const u8 * fw_ver;

	if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
		return -EINVAL;

	fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
	sections = (struct bnx2x_fw_file_section *)fw_hdr;

	/* Make sure none of the offsets and sizes make us read beyond
	 * the end of the firmware data */
	for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
		offset = be32_to_cpu(sections[i].offset);
		len = be32_to_cpu(sections[i].len);
		if (offset + len > firmware->size) {
			printk(KERN_ERR PFX "Section %d length is out of bounds\n", i);
			return -EINVAL;
		}
	}

	/* Likewise for the init_ops offsets */
	offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
	ops_offsets = (u16 *)(firmware->data + offset);
	num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);

	for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
		if (be16_to_cpu(ops_offsets[i]) > num_ops) {
			printk(KERN_ERR PFX "Section offset %d is out of bounds\n", i);
			return -EINVAL;
		}
	}

	/* Check FW version */
	offset = be32_to_cpu(fw_hdr->fw_version.offset);
	fw_ver = firmware->data + offset;
	if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
	    (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
	    (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
	    (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
		printk(KERN_ERR PFX "Bad FW version:%d.%d.%d.%d."
				    " Should be %d.%d.%d.%d\n",
		       fw_ver[0], fw_ver[1], fw_ver[2],
		       fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
		       BCM_5710_FW_MINOR_VERSION,
		       BCM_5710_FW_REVISION_VERSION,
		       BCM_5710_FW_ENGINEERING_VERSION);
                return -EINVAL;
	}

	return 0;
}

static void inline be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
{
	u32 i;
	const __be32 *source = (const __be32*)_source;
	u32 *target = (u32*)_target;

	for (i = 0; i < n/4; i++)
		target[i] = be32_to_cpu(source[i]);
}

/*
   Ops array is stored in the following format:
   {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
 */
static void inline bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
{
	u32 i, j, tmp;
	const __be32 *source = (const __be32*)_source;
	struct raw_op *target = (struct raw_op*)_target;

	for (i = 0, j = 0; i < n/8; i++, j+=2) {
		tmp = be32_to_cpu(source[j]);
		target[i].op = (tmp >> 24) & 0xff;
		target[i].offset =  tmp & 0xffffff;
		target[i].raw_data = be32_to_cpu(source[j+1]);
	}
}
static void inline be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
{
	u32 i;
	u16 *target = (u16*)_target;
	const __be16 *source = (const __be16*)_source;

	for (i = 0; i < n/2; i++)
		target[i] = be16_to_cpu(source[i]);
}

#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
	do {   \
		u32 len = be32_to_cpu(fw_hdr->arr.len);   \
		bp->arr = kmalloc(len, GFP_KERNEL);  \
		if (!bp->arr) { \
			printk(KERN_ERR PFX "Failed to allocate %d bytes for "#arr"\n", len); \
			goto lbl; \
		} \
		func(bp->firmware->data + \
			be32_to_cpu(fw_hdr->arr.offset), \
			(u8*)bp->arr, len); \
	} while (0)


static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
{
	char fw_file_name[40] = {0};
        int rc, offset;
	struct bnx2x_fw_file_hdr *fw_hdr;

	/* Create a FW file name */
	if (CHIP_IS_E1(bp))
                offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1);
	else
		offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1H);

	sprintf(fw_file_name + offset, "%d.%d.%d.%d.fw",
		BCM_5710_FW_MAJOR_VERSION,
                BCM_5710_FW_MINOR_VERSION,
                BCM_5710_FW_REVISION_VERSION,
                BCM_5710_FW_ENGINEERING_VERSION);

	printk(KERN_INFO PFX "Loading %s\n", fw_file_name);

	rc = request_firmware(&bp->firmware, fw_file_name, dev);
	if (rc) {
		printk(KERN_ERR PFX "Can't load firmware file %s\n", fw_file_name);
		goto request_firmware_exit;
	}

	rc = bnx2x_check_firmware(bp);
	if (rc) {
		printk(KERN_ERR PFX "Corrupt firmware file %s\n", fw_file_name);
		goto request_firmware_exit;
	}

	fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;

	/* Initialize the pointers to the init arrays */
	/* Blob */
	BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);

	/* Opcodes */
	BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);

	/* Offsets */
	BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, be16_to_cpu_n);

	/* STORMs firmware */
	bp->tsem_int_table_data = bp->firmware->data +
		be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
	bp->tsem_pram_data      = bp->firmware->data +
		be32_to_cpu(fw_hdr->tsem_pram_data.offset);
	bp->usem_int_table_data = bp->firmware->data +
		be32_to_cpu(fw_hdr->usem_int_table_data.offset);
	bp->usem_pram_data      = bp->firmware->data +
		be32_to_cpu(fw_hdr->usem_pram_data.offset);
	bp->xsem_int_table_data = bp->firmware->data +
		be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
	bp->xsem_pram_data      = bp->firmware->data +
		be32_to_cpu(fw_hdr->xsem_pram_data.offset);
	bp->csem_int_table_data = bp->firmware->data +
		be32_to_cpu(fw_hdr->csem_int_table_data.offset);
	bp->csem_pram_data      = bp->firmware->data +
		be32_to_cpu(fw_hdr->csem_pram_data.offset);

	return 0;
init_offsets_alloc_err:
	kfree(bp->init_ops);
init_ops_alloc_err:
	kfree(bp->init_data);
request_firmware_exit:
	release_firmware(bp->firmware);

	return rc;
}


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11648 11649 11650 11651 11652 11653
static int __devinit bnx2x_init_one(struct pci_dev *pdev,
				    const struct pci_device_id *ent)
{
	static int version_printed;
	struct net_device *dev = NULL;
	struct bnx2x *bp;
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	int rc;
11655 11656 11657 11658 11659

	if (version_printed++ == 0)
		printk(KERN_INFO "%s", version);

	/* dev zeroed in init_etherdev */
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	dev = alloc_etherdev_mq(sizeof(*bp), MAX_CONTEXT);
11661 11662
	if (!dev) {
		printk(KERN_ERR PFX "Cannot allocate net device\n");
11663
		return -ENOMEM;
11664
	}
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	bp = netdev_priv(dev);
	bp->msglevel = debug;

11669
	rc = bnx2x_init_dev(pdev, dev);
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	if (rc < 0) {
		free_netdev(dev);
		return rc;
	}

	pci_set_drvdata(pdev, dev);

11677
	rc = bnx2x_init_bp(bp);
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	if (rc)
		goto init_one_exit;

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	/* Set init arrays */
	rc = bnx2x_init_firmware(bp, &pdev->dev);
	if (rc) {
		printk(KERN_ERR PFX "Error loading firmware\n");
		goto init_one_exit;
	}

11688
	rc = register_netdev(dev);
11689
	if (rc) {
11690
		dev_err(&pdev->dev, "Cannot register net device\n");
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		goto init_one_exit;
	}

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	printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
11695
	       " IRQ %d, ", dev->name, board_info[ent->driver_data].name,
11696
	       (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
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	       bnx2x_get_pcie_width(bp),
	       (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
	       dev->base_addr, bp->pdev->irq);
11700
	printk(KERN_CONT "node addr %pM\n", dev->dev_addr);
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11702
	return 0;
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init_one_exit:
	if (bp->regview)
		iounmap(bp->regview);

	if (bp->doorbells)
		iounmap(bp->doorbells);

	free_netdev(dev);

	if (atomic_read(&pdev->enable_cnt) == 1)
		pci_release_regions(pdev);

	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);

	return rc;
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}

static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
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	struct bnx2x *bp;

	if (!dev) {
		printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
		return;
	}
	bp = netdev_priv(dev);
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	unregister_netdev(dev);

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	kfree(bp->init_ops_offsets);
	kfree(bp->init_ops);
	kfree(bp->init_data);
	release_firmware(bp->firmware);

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	if (bp->regview)
		iounmap(bp->regview);

	if (bp->doorbells)
		iounmap(bp->doorbells);

	free_netdev(dev);
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	if (atomic_read(&pdev->enable_cnt) == 1)
		pci_release_regions(pdev);

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	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
}

static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct net_device *dev = pci_get_drvdata(pdev);
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	struct bnx2x *bp;

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	if (!dev) {
		printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
		return -ENODEV;
	}
	bp = netdev_priv(dev);
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	rtnl_lock();
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	pci_save_state(pdev);
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	if (!netif_running(dev)) {
		rtnl_unlock();
		return 0;
	}
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	netif_device_detach(dev);

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	bnx2x_nic_unload(bp, UNLOAD_CLOSE);
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	bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
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	rtnl_unlock();

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	return 0;
}

static int bnx2x_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
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	struct bnx2x *bp;
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	int rc;

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	if (!dev) {
		printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
		return -ENODEV;
	}
	bp = netdev_priv(dev);
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	rtnl_lock();

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	pci_restore_state(pdev);
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	if (!netif_running(dev)) {
		rtnl_unlock();
		return 0;
	}

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	bnx2x_set_power_state(bp, PCI_D0);
	netif_device_attach(dev);

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	rc = bnx2x_nic_load(bp, LOAD_OPEN);
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	rtnl_unlock();

	return rc;
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}

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static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
{
	int i;

	bp->state = BNX2X_STATE_ERROR;

	bp->rx_mode = BNX2X_RX_MODE_NONE;

	bnx2x_netif_stop(bp, 0);

	del_timer_sync(&bp->timer);
	bp->stats_state = STATS_STATE_DISABLED;
	DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");

	/* Release IRQs */
	bnx2x_free_irq(bp);

	if (CHIP_IS_E1(bp)) {
		struct mac_configuration_cmd *config =
						bnx2x_sp(bp, mcast_config);

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		for (i = 0; i < config->hdr.length; i++)
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			CAM_INVALIDATE(config->config_table[i]);
	}

	/* Free SKBs, SGEs, TPA pool and driver internals */
	bnx2x_free_skbs(bp);
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	for_each_rx_queue(bp, i)
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		bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
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	for_each_rx_queue(bp, i)
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		netif_napi_del(&bnx2x_fp(bp, i, napi));
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	bnx2x_free_mem(bp);

	bp->state = BNX2X_STATE_CLOSED;

	netif_carrier_off(bp->dev);

	return 0;
}

static void bnx2x_eeh_recover(struct bnx2x *bp)
{
	u32 val;

	mutex_init(&bp->port.phy_mutex);

	bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
	bp->link_params.shmem_base = bp->common.shmem_base;
	BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);

	if (!bp->common.shmem_base ||
	    (bp->common.shmem_base < 0xA0000) ||
	    (bp->common.shmem_base >= 0xC0000)) {
		BNX2X_DEV_INFO("MCP not active\n");
		bp->flags |= NO_MCP_FLAG;
		return;
	}

	val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
	if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
		!= (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
		BNX2X_ERR("BAD MCP validity signature\n");

	if (!BP_NOMCP(bp)) {
		bp->fw_seq = (SHMEM_RD(bp, func_mb[BP_FUNC(bp)].drv_mb_header)
			      & DRV_MSG_SEQ_NUMBER_MASK);
		BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
	}
}

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/**
 * bnx2x_io_error_detected - called when PCI error is detected
 * @pdev: Pointer to PCI device
 * @state: The current pci connection state
 *
 * This function is called after a PCI bus error affecting
 * this device has been detected.
 */
static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
						pci_channel_state_t state)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2x *bp = netdev_priv(dev);

	rtnl_lock();

	netif_device_detach(dev);

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	if (state == pci_channel_io_perm_failure) {
		rtnl_unlock();
		return PCI_ERS_RESULT_DISCONNECT;
	}

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	if (netif_running(dev))
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		bnx2x_eeh_nic_unload(bp);
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	pci_disable_device(pdev);

	rtnl_unlock();

	/* Request a slot reset */
	return PCI_ERS_RESULT_NEED_RESET;
}

/**
 * bnx2x_io_slot_reset - called after the PCI bus has been reset
 * @pdev: Pointer to PCI device
 *
 * Restart the card from scratch, as if from a cold-boot.
 */
static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2x *bp = netdev_priv(dev);

	rtnl_lock();

	if (pci_enable_device(pdev)) {
		dev_err(&pdev->dev,
			"Cannot re-enable PCI device after reset\n");
		rtnl_unlock();
		return PCI_ERS_RESULT_DISCONNECT;
	}

	pci_set_master(pdev);
	pci_restore_state(pdev);

	if (netif_running(dev))
		bnx2x_set_power_state(bp, PCI_D0);

	rtnl_unlock();

	return PCI_ERS_RESULT_RECOVERED;
}

/**
 * bnx2x_io_resume - called when traffic can start flowing again
 * @pdev: Pointer to PCI device
 *
 * This callback is called when the error recovery driver tells us that
 * its OK to resume normal operation.
 */
static void bnx2x_io_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2x *bp = netdev_priv(dev);

	rtnl_lock();

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	bnx2x_eeh_recover(bp);

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	if (netif_running(dev))
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		bnx2x_nic_load(bp, LOAD_NORMAL);
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	netif_device_attach(dev);

	rtnl_unlock();
}

static struct pci_error_handlers bnx2x_err_handler = {
	.error_detected = bnx2x_io_error_detected,
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	.slot_reset     = bnx2x_io_slot_reset,
	.resume         = bnx2x_io_resume,
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};

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static struct pci_driver bnx2x_pci_driver = {
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	.name        = DRV_MODULE_NAME,
	.id_table    = bnx2x_pci_tbl,
	.probe       = bnx2x_init_one,
	.remove      = __devexit_p(bnx2x_remove_one),
	.suspend     = bnx2x_suspend,
	.resume      = bnx2x_resume,
	.err_handler = &bnx2x_err_handler,
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};

static int __init bnx2x_init(void)
{
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	int ret;

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	bnx2x_wq = create_singlethread_workqueue("bnx2x");
	if (bnx2x_wq == NULL) {
		printk(KERN_ERR PFX "Cannot create workqueue\n");
		return -ENOMEM;
	}

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	ret = pci_register_driver(&bnx2x_pci_driver);
	if (ret) {
		printk(KERN_ERR PFX "Cannot register driver\n");
		destroy_workqueue(bnx2x_wq);
	}
	return ret;
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}

static void __exit bnx2x_cleanup(void)
{
	pci_unregister_driver(&bnx2x_pci_driver);
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	destroy_workqueue(bnx2x_wq);
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}

module_init(bnx2x_init);
module_exit(bnx2x_cleanup);

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