amd64-agp.c 19.5 KB
Newer Older
1
/*
2
 * Copyright 2001-2003 SuSE Labs.
3
 * Distributed under the GNU public license, v2.
4
 *
5
 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 7 8 9
 * It also includes support for the AMD 8151 AGP bridge,
 * although it doesn't actually do much, as all the real
 * work is done in the northbridge(s).
 */
10

11
#include <linux/config.h>
12 13 14 15 16 17
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"

18
/* Will need to be increased if AMD64 ever goes >8-way. */
19 20
#define MAX_HAMMER_GARTS   8

21 22 23 24 25
/* PTE bits. */
#define GPTE_VALID	1
#define GPTE_COHERENT	2

/* Aperture control register bits. */
26 27 28
#define GARTEN		(1<<0)
#define DISGARTCPU	(1<<4)
#define DISGARTIO	(1<<5)
29 30

/* GART cache control register bits. */
31 32
#define INVGART		(1<<0)
#define GARTPTEERR	(1<<1)
33

34 35 36 37 38 39 40
/* K8 On-cpu GART registers */
#define AMD64_GARTAPERTURECTL	0x90
#define AMD64_GARTAPERTUREBASE	0x94
#define AMD64_GARTTABLEBASE	0x98
#define AMD64_GARTCACHECTL	0x9c
#define AMD64_GARTEN		(1<<0)

41 42 43 44 45 46 47 48
/* NVIDIA K8 registers */
#define NVIDIA_X86_64_0_APBASE		0x10
#define NVIDIA_X86_64_1_APBASE1		0x50
#define NVIDIA_X86_64_1_APLIMIT1	0x54
#define NVIDIA_X86_64_1_APSIZE		0xa8
#define NVIDIA_X86_64_1_APBASE2		0xd8
#define NVIDIA_X86_64_1_APLIMIT2	0xdc

Dave Jones's avatar
Dave Jones committed
49 50 51 52 53
/* ULi K8 registers */
#define ULI_X86_64_BASE_ADDR		0x10
#define ULI_X86_64_HTT_FEA_REG		0x50
#define ULI_X86_64_ENU_SCR_REG		0x54

54 55 56
static int nr_garts;
static struct pci_dev * hammers[MAX_HAMMER_GARTS];

57
static struct resource *aperture_resource;
58 59
static int __initdata agp_try_unsupported;

60 61 62
static int gart_iterator;
#define for_each_nb() for(gart_iterator=0;gart_iterator<nr_garts;gart_iterator++)

63
static void flush_amd64_tlb(struct pci_dev *dev)
64 65 66
{
	u32 tmp;

67
	pci_read_config_dword (dev, AMD64_GARTCACHECTL, &tmp);
68
	tmp |= INVGART;
69
	pci_write_config_dword (dev, AMD64_GARTCACHECTL, tmp);
70 71
}

72
static void amd64_tlbflush(struct agp_memory *temp)
73 74
{
	for_each_nb()
75
		flush_amd64_tlb(hammers[gart_iterator]);
76 77
}

78
static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
79 80
{
	int i, j, num_entries;
81
	long long tmp;
82 83
	u32 pte;

84
	num_entries = agp_num_entries();
85 86 87 88 89

	if (type != 0 || mem->type != 0)
		return -EINVAL;

	/* Make sure we can fit the range in the gatt table. */
90 91
	/* FIXME: could wrap */
	if (((unsigned long)pg_start + mem->page_count) > num_entries)
92 93 94 95 96 97
		return -EINVAL;

	j = pg_start;

	/* gatt table should be empty. */
	while (j < (pg_start + mem->page_count)) {
98
		if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
99 100 101 102 103
			return -EBUSY;
		j++;
	}

	if (mem->is_flushed == FALSE) {
104
		global_cache_flush();
105 106 107 108
		mem->is_flushed = TRUE;
	}

	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
109
		tmp = agp_bridge->driver->mask_memory(mem->memory[i], mem->type);
110

Jeff Garzik's avatar
Jeff Garzik committed
111 112 113
		BUG_ON(tmp & 0xffffff0000000ffcULL);
		pte = (tmp & 0x000000ff00000000ULL) >> 28;
		pte |=(tmp & 0x00000000fffff000ULL);
114
		pte |= GPTE_VALID | GPTE_COHERENT;
115

116
		writel(pte, agp_bridge->gatt_table+j);
117
		readl(agp_bridge->gatt_table+j);	/* PCI Posting. */
118
	}
119
	amd64_tlbflush(mem);
120 121 122 123 124 125 126 127
	return 0;
}

/*
 * This hack alters the order element according
 * to the size of a long. It sucks. I totally disown this, even
 * though it does appear to work for the most part.
 */
128
static struct aper_size_info_32 amd64_aperture_sizes[7] =
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145
{
	{32,   8192,   3+(sizeof(long)/8), 0 },
	{64,   16384,  4+(sizeof(long)/8), 1<<1 },
	{128,  32768,  5+(sizeof(long)/8), 1<<2 },
	{256,  65536,  6+(sizeof(long)/8), 1<<1 | 1<<2 },
	{512,  131072, 7+(sizeof(long)/8), 1<<3 },
	{1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
	{2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
};


/*
 * Get the current Aperture size from the x86-64.
 * Note, that there may be multiple x86-64's, but we just return
 * the value from the first one we find. The set_size functions
 * keep the rest coherent anyway. Or at least should do.
 */
146
static int amd64_fetch_size(void)
147 148 149 150 151 152
{
	struct pci_dev *dev;
	int i;
	u32 temp;
	struct aper_size_info_32 *values;

153 154 155 156
	dev = hammers[0];
	if (dev==NULL)
		return 0;

157
	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
158
	temp = (temp & 0xe);
159
	values = A_SIZE_32(amd64_aperture_sizes);
160

161
	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
162 163 164 165 166 167
		if (temp == values[i].size_value) {
			agp_bridge->previous_size =
			    agp_bridge->current_size = (void *) (values + i);

			agp_bridge->aperture_size_idx = i;
			return values[i].size;
168 169 170 171 172 173 174 175 176
		}
	}
	return 0;
}

/*
 * In a multiprocessor x86-64 system, this function gets
 * called once for each CPU.
 */
177
static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
178 179 180 181 182 183
{
	u64 aperturebase;
	u32 tmp;
	u64 addr, aper_base;

	/* Address to map to */
184
	pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
185 186 187 188 189 190 191 192
	aperturebase = tmp << 25;
	aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);

	/* address of the mappings table */
	addr = (u64) gatt_table;
	addr >>= 12;
	tmp = (u32) addr<<4;
	tmp &= ~0xf;
193
	pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
194 195

	/* Enable GART translation for this hammer. */
196
	pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
197 198
	tmp |= GARTEN;
	tmp &= ~(DISGARTCPU | DISGARTIO);
199
	pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
200 201

	/* keep CPU's coherent. */
202
	flush_amd64_tlb (hammer);
203

204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220
	return aper_base;
}


static struct aper_size_info_32 amd_8151_sizes[7] =
{
	{2048, 524288, 9, 0x00000000 },	/* 0 0 0 0 0 0 */
	{1024, 262144, 8, 0x00000400 },	/* 1 0 0 0 0 0 */
	{512,  131072, 7, 0x00000600 },	/* 1 1 0 0 0 0 */
	{256,  65536,  6, 0x00000700 },	/* 1 1 1 0 0 0 */
	{128,  32768,  5, 0x00000720 },	/* 1 1 1 1 0 0 */
	{64,   16384,  4, 0x00000730 },	/* 1 1 1 1 1 0 */
	{32,   8192,   3, 0x00000738 } 	/* 1 1 1 1 1 1 */
};

static int amd_8151_configure(void)
{
221
	unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
222 223

	/* Configure AGP regs in each x86-64 host bridge. */
224 225
	for_each_nb() {
		agp_bridge->gart_bus_addr =
226
				amd64_configure(hammers[gart_iterator],gatt_bus);
227 228 229 230 231
	}
	return 0;
}


232
static void amd64_cleanup(void)
233 234 235
{
	u32 tmp;

236
	for_each_nb() {
237
		/* disable gart translation */
238 239 240
		pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp);
		tmp &= ~AMD64_GARTEN;
		pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp);
241 242 243 244
	}
}


245 246 247
struct agp_bridge_driver amd_8151_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= amd_8151_sizes,
248 249 250
	.size_type		= U32_APER_SIZE,
	.num_aperture_sizes	= 7,
	.configure		= amd_8151_configure,
251 252 253
	.fetch_size		= amd64_fetch_size,
	.cleanup		= amd64_cleanup,
	.tlb_flush		= amd64_tlbflush,
254
	.mask_memory		= agp_generic_mask_memory,
255
	.masks			= NULL,
256 257 258 259
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= agp_generic_create_gatt_table,
	.free_gatt_table	= agp_generic_free_gatt_table,
260
	.insert_memory		= amd64_insert_memory,
261 262 263 264 265 266
	.remove_memory		= agp_generic_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_destroy_page	= agp_generic_destroy_page,
};
267

268
/* Some basic sanity checks for the aperture. */
269
static int __devinit aperture_valid(u64 aper, u32 size)
270
{
271
	u32 pfn, c;
272
	if (aper == 0) {
273
		printk(KERN_ERR PFX "No aperture\n");
274
		return 0;
275 276
	}
	if (size < 32*1024*1024) {
277
		printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
278 279
		return 0;
	}
280 281
	if (aper + size > 0xffffffff) {
		printk(KERN_ERR PFX "Aperture out of bounds\n");
282
		return 0;
283
	}
284
	pfn = aper >> PAGE_SHIFT;
285
	for (c = 0; c < size/PAGE_SIZE; c++) {
286 287
		if (!pfn_valid(pfn + c))
			break;
288
		if (!PageReserved(pfn_to_page(pfn + c))) {
289
			printk(KERN_ERR PFX "Aperture pointing to RAM\n");
290 291 292
			return 0;
		}
	}
293

294
	/* Request the Aperture. This catches cases when someone else
295
	   already put a mapping in there - happens with some very broken BIOS
296

297 298
	   Maybe better to use pci_assign_resource/pci_enable_device instead
	   trusting the bridges? */
299 300
	if (!aperture_resource &&
	    !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
301
		printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
302 303 304
		return 0;
	}
	return 1;
305
}
306

307
/*
308
 * W*s centric BIOS sometimes only set up the aperture in the AGP
309
 * bridge, not the northbridge. On AMD64 this is handled early
310
 * in aperture.c, but when GART_IOMMU is not enabled or we run
311
 * on a 32bit kernel this needs to be redone.
312 313 314
 * Unfortunately it is impossible to fix the aperture here because it's too late
 * to allocate that much memory. But at least error out cleanly instead of
 * crashing.
315 316
 */
static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
317 318 319 320 321 322 323 324
								 u16 cap)
{
	u32 aper_low, aper_hi;
	u64 aper, nb_aper;
	int order = 0;
	u32 nb_order, nb_base;
	u16 apsize;

325
	pci_read_config_dword(nb, 0x90, &nb_order);
326
	nb_order = (nb_order >> 1) & 7;
327 328 329
	pci_read_config_dword(nb, 0x94, &nb_base);
	nb_aper = nb_base << 25;
	if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
330 331 332 333 334
		return 0;
	}

	/* Northbridge seems to contain crap. Try the AGP bridge. */

335 336 337
	pci_read_config_word(agp, cap+0x14, &apsize);
	if (apsize == 0xffff)
		return -1;
338 339 340

	apsize &= 0xfff;
	/* Some BIOS use weird encodings not in the AGPv3 table. */
341 342 343
	if (apsize & 0xff)
		apsize |= 0xf00;
	order = 7 - hweight16(apsize);
344 345 346

	pci_read_config_dword(agp, 0x10, &aper_low);
	pci_read_config_dword(agp, 0x14, &aper_hi);
347
	aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
348
	printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
349
	if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
350 351 352 353
		return -1;

	pci_write_config_dword(nb, 0x90, order << 1);
	pci_write_config_dword(nb, 0x94, aper >> 25);
354 355

	return 0;
356
}
357

358
static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
359 360 361 362 363
{
	struct pci_dev *loop_dev = NULL;
	int i = 0;

	/* cache pci_devs of northbridges. */
364
	while ((loop_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, loop_dev))
365
			!= NULL) {
366
		if (i == MAX_HAMMER_GARTS) {
367 368 369
			printk(KERN_ERR PFX "Too many northbridges for AGP\n");
			return -1;
		}
370
		if (fix_northbridge(loop_dev, pdev, cap_ptr) < 0) {
371
			printk(KERN_ERR PFX "No usable aperture found.\n");
372
#ifdef __x86_64__
373
			/* should port this to i386 */
374
			printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
375 376
#endif
			return -1;
377
		}
378
		hammers[i++] = loop_dev;
379
	}
380
		nr_garts = i;
381 382 383 384 385
	return i == 0 ? -1 : 0;
}

/* Handle AMD 8151 quirks */
static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
386
{
387 388 389 390 391 392 393 394 395 396
	char *revstring;
	u8 rev_id;

	pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
	switch (rev_id) {
	case 0x01: revstring="A0"; break;
	case 0x02: revstring="A1"; break;
	case 0x11: revstring="B0"; break;
	case 0x12: revstring="B1"; break;
	case 0x13: revstring="B2"; break;
397
	case 0x14: revstring="B3"; break;
398
	default:   revstring="??"; break;
399
	}
400 401 402 403 404 405 406 407 408 409 410

	printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);

	/*
	 * Work around errata.
	 * Chips before B2 stepping incorrectly reporting v3.5
	 */
	if (rev_id < 0x13) {
		printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
		bridge->major_version = 3;
		bridge->minor_version = 0;
411
	}
412
}
413

Dave Jones's avatar
Dave Jones committed
414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468

static struct aper_size_info_32 uli_sizes[7] =
{
	{256, 65536, 6, 10},
	{128, 32768, 5, 9},
	{64, 16384, 4, 8},
	{32, 8192, 3, 7},
	{16, 4096, 2, 6},
	{8, 2048, 1, 4},
	{4, 1024, 0, 3}
};
static int __devinit uli_agp_init(struct pci_dev *pdev)
{
	u32 httfea,baseaddr,enuscr;
	struct pci_dev *dev1;
	int i;
	unsigned size = amd64_fetch_size();
	printk(KERN_INFO "Setting up ULi AGP. \n");
	dev1 = pci_find_slot ((unsigned int)pdev->bus->number,PCI_DEVFN(0,0));
	if (dev1 == NULL) {
		printk(KERN_INFO PFX "Detected a ULi chipset, "
			"but could not fine the secondary device.\n");
		return -ENODEV;
	}

	for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
		if (uli_sizes[i].size == size)
			break;

	if (i == ARRAY_SIZE(uli_sizes)) {
		printk(KERN_INFO PFX "No ULi size found for %d\n", size);
		return -ENODEV;
	}

	/* shadow x86-64 registers into ULi registers */
	pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &httfea);

	/* if x86-64 aperture base is beyond 4G, exit here */
	if ((httfea & 0x7fff) >> (32 - 25))
		return -ENODEV;

	httfea = (httfea& 0x7fff) << 25;

	pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
	baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
	baseaddr|= httfea;
	pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);

	enuscr= httfea+ (size * 1024 * 1024) - 1;
	pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
	pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
	return 0;
}


469 470 471 472 473 474 475 476 477 478 479
static struct aper_size_info_32 nforce3_sizes[5] =
{
	{512,  131072, 7, 0x00000000 },
	{256,  65536,  6, 0x00000008 },
	{128,  32768,  5, 0x0000000C },
	{64,   16384,  4, 0x0000000E },
	{32,   8192,   3, 0x0000000F }
};

/* Handle shadow device of the Nvidia NForce3 */
/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
480 481
static int __devinit nforce3_agp_init(struct pci_dev *pdev)
{
482
	u32 tmp, apbase, apbar, aplimit;
483
	struct pci_dev *dev1;
484
	int i;
485
	unsigned size = amd64_fetch_size();
486 487 488 489 490 491 492 493 494

	printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");

	dev1 = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(11, 0));
	if (dev1 == NULL) {
		printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
			"nForce3 chipset, but could not find "
			"the secondary device.\n");
		return -ENODEV;
495
	}
496

497
	for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
498
		if (nforce3_sizes[i].size == size)
499
			break;
500 501

	if (i == ARRAY_SIZE(nforce3_sizes)) {
502 503
		printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
		return -ENODEV;
504
	}
505

506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531
	pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
	tmp &= ~(0xf);
	tmp |= nforce3_sizes[i].size_value;
	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);

	/* shadow x86-64 registers into NVIDIA registers */
	pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &apbase);

	/* if x86-64 aperture base is beyond 4G, exit here */
	if ( (apbase & 0x7fff) >> (32 - 25) )
		 return -ENODEV;

	apbase = (apbase & 0x7fff) << 25;

	pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
	apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
	apbar |= apbase;
	pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);

	aplimit = apbase + (size * 1024 * 1024) - 1;
	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);

	return 0;
532 533
}

534 535
static int __devinit agp_amd64_probe(struct pci_dev *pdev,
				     const struct pci_device_id *ent)
536
{
537
	struct agp_bridge_data *bridge;
538
	u8 cap_ptr;
539

540 541
	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	if (!cap_ptr)
542
		return -ENODEV;
543

544
	/* Could check for AGPv3 here */
545

546 547 548 549
	bridge = agp_alloc_bridge();
	if (!bridge)
		return -ENOMEM;

550 551
	if (pdev->vendor == PCI_VENDOR_ID_AMD &&
	    pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
552
		amd8151_init(pdev, bridge);
553
	} else {
554
		printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
555 556
	}

557 558 559
	bridge->driver = &amd_8151_driver;
	bridge->dev = pdev;
	bridge->capndx = cap_ptr;
560 561

	/* Fill in the mode register */
562
	pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
563

564
	if (cache_nbs(pdev, cap_ptr) == -1) {
565
		agp_put_bridge(bridge);
566
		return -ENODEV;
567
	}
568

569
	if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
570
		int ret = nforce3_agp_init(pdev);
571 572
		if (ret) {
			agp_put_bridge(bridge);
573 574 575 576
			return ret;
		}
	}

Dave Jones's avatar
Dave Jones committed
577 578 579 580 581 582 583 584
	if (pdev->vendor == PCI_VENDOR_ID_AL) {
		int ret = uli_agp_init(pdev);
		if (ret) {
			agp_put_bridge(bridge);
			return ret;
		}
	}

585 586
	pci_set_drvdata(pdev, bridge);
	return agp_add_bridge(bridge);
587
}
588

589
static void __devexit agp_amd64_remove(struct pci_dev *pdev)
590
{
591 592
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

593 594
	release_mem_region(virt_to_phys(bridge->gatt_table_real),
			   amd64_aperture_sizes[bridge->aperture_size_idx].size);
595 596
	agp_remove_bridge(bridge);
	agp_put_bridge(bridge);
597 598
}

599
static struct pci_device_id agp_amd64_pci_table[] = {
600 601 602 603 604 605 606 607
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_AMD,
	.device		= PCI_DEVICE_ID_AMD_8151_0,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
Dave Jones's avatar
Dave Jones committed
608 609 610 611 612 613 614 615 616
	/* ULi M1689 */
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_AL,
	.device		= PCI_DEVICE_ID_AL_M1689,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
617 618 619 620 621 622 623 624 625
	/* VIA K8T800Pro */
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_VIA,
	.device		= PCI_DEVICE_ID_VIA_K8T800PRO_0,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
Dave Jones's avatar
Dave Jones committed
626
	/* VIA K8T800 */
627 628 629 630
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_VIA,
Dave Jones's avatar
Dave Jones committed
631 632 633 634 635 636 637 638 639 640
	.device		= PCI_DEVICE_ID_VIA_8385_0,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	/* VIA K8M800 / K8N800 */
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_VIA,
	.device		= PCI_DEVICE_ID_VIA_8380_0,
641 642 643
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
644
	/* VIA K8T890 */
645 646 647
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
648
	.vendor		= PCI_VENDOR_ID_VIA,
649
	.device		= PCI_DEVICE_ID_VIA_3238_0,
650 651 652
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
653 654 655 656 657 658 659 660 661
	/* VIA K8T800/K8M800/K8N800 */
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_VIA,
	.device		= PCI_DEVICE_ID_VIA_838X_1,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
662 663 664 665 666 667 668 669 670 671 672 673 674 675
	/* NForce3 */
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_NVIDIA,
	.device		= PCI_DEVICE_ID_NVIDIA_NFORCE3,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_NVIDIA,
	.device		= PCI_DEVICE_ID_NVIDIA_NFORCE3S,
676 677 678
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
679 680 681 682 683 684 685 686 687
	/* SIS 755 */
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_SI,
	.device		= PCI_DEVICE_ID_SI_755,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
688 689 690
	{ }
};

691
MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
692

693 694 695 696 697
static struct pci_driver agp_amd64_pci_driver = {
	.name		= "agpgart-amd64",
	.id_table	= agp_amd64_pci_table,
	.probe		= agp_amd64_probe,
	.remove		= agp_amd64_remove,
698 699
};

700

701
/* Not static due to IOMMU code calling it early. */
702
int __init agp_amd64_init(void)
703
{
704
	int err = 0;
705 706 707 708 709
	static struct pci_device_id amd64nb[] = {
		{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
		{ },
	};

710 711
	if (agp_off)
		return -EINVAL;
712
	if (pci_module_init(&agp_amd64_pci_driver) > 0) {
713
		struct pci_dev *dev;
714
		if (!agp_try_unsupported && !agp_try_unsupported_boot) {
715
			printk(KERN_INFO PFX "No supported AGP bridge found.\n");
716
#ifdef MODULE
717
			printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
718
#else
719
			printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
720
#endif
721 722 723
			return -ENODEV;
		}

724
		/* First check that we have at least one AMD64 NB */
725
		if (!pci_dev_present(amd64nb))
726 727 728 729 730
			return -ENODEV;

		/* Look for any AGP bridge */
		dev = NULL;
		err = -ENODEV;
731
		for_each_pci_dev(dev) {
732 733
			if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
				continue;
734
			/* Only one bridge supported right now */
735
			if (agp_amd64_probe(dev, NULL) == 0) {
736 737
				err = 0;
				break;
738 739
			}
		}
740 741
	}
	return err;
742 743
}

744
static void __exit agp_amd64_cleanup(void)
745
{
746 747
	if (aperture_resource)
		release_resource(aperture_resource);
748
	pci_unregister_driver(&agp_amd64_pci_driver);
749 750
}

751
/* On AMD64 the PCI driver needs to initialize this driver early
752 753
   for the IOMMU, so it has to be called via a backdoor. */
#ifndef CONFIG_GART_IOMMU
754 755
module_init(agp_amd64_init);
module_exit(agp_amd64_cleanup);
756
#endif
757

758 759
MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
MODULE_PARM(agp_try_unsupported, "1i");
Dave Jones's avatar
Dave Jones committed
760
MODULE_LICENSE("GPL");