xilinx_uartps.c 51 KB
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// SPDX-License-Identifier: GPL-2.0+
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/*
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 * Cadence UART driver (found in Xilinx Zynq)
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 *
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 * 2011 - 2014 (C) Xilinx Inc.
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 *
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 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
 * still shows in the naming of this file, the kconfig symbols and some symbols
 * in the code.
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 */

#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/console.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <linux/tty.h>
#include <linux/tty_flip.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/iopoll.h>
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#define CDNS_UART_TTY_NAME	"ttyPS"
#define CDNS_UART_NAME		"xuartps"
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#define CDNS_UART_MAJOR		0	/* use dynamic node allocation */
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#define CDNS_UART_FIFO_SIZE	64	/* FIFO size */
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#define CDNS_UART_REGISTER_SPACE	0x1000
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#define TX_TIMEOUT		500000
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/* Rx Trigger level */
static int rx_trigger_level = 56;
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module_param(rx_trigger_level, uint, 0444);
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MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");

/* Rx Timeout */
static int rx_timeout = 10;
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module_param(rx_timeout, uint, 0444);
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MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");

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/* Register offsets for the UART. */
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#define CDNS_UART_CR		0x00  /* Control Register */
#define CDNS_UART_MR		0x04  /* Mode Register */
#define CDNS_UART_IER		0x08  /* Interrupt Enable */
#define CDNS_UART_IDR		0x0C  /* Interrupt Disable */
#define CDNS_UART_IMR		0x10  /* Interrupt Mask */
#define CDNS_UART_ISR		0x14  /* Interrupt Status */
#define CDNS_UART_BAUDGEN	0x18  /* Baud Rate Generator */
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#define CDNS_UART_RXTOUT	0x1C  /* RX Timeout */
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#define CDNS_UART_RXWM		0x20  /* RX FIFO Trigger Level */
#define CDNS_UART_MODEMCR	0x24  /* Modem Control */
#define CDNS_UART_MODEMSR	0x28  /* Modem Status */
#define CDNS_UART_SR		0x2C  /* Channel Status */
#define CDNS_UART_FIFO		0x30  /* FIFO */
#define CDNS_UART_BAUDDIV	0x34  /* Baud Rate Divider */
#define CDNS_UART_FLOWDEL	0x38  /* Flow Delay */
#define CDNS_UART_IRRX_PWIDTH	0x3C  /* IR Min Received Pulse Width */
#define CDNS_UART_IRTX_PWIDTH	0x40  /* IR Transmitted pulse Width */
#define CDNS_UART_TXWM		0x44  /* TX FIFO Trigger Level */
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#define CDNS_UART_RXBS		0x48  /* RX FIFO byte status register */
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/* Control Register Bit Definitions */
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#define CDNS_UART_CR_STOPBRK	0x00000100  /* Stop TX break */
#define CDNS_UART_CR_STARTBRK	0x00000080  /* Set TX break */
#define CDNS_UART_CR_TX_DIS	0x00000020  /* TX disabled. */
#define CDNS_UART_CR_TX_EN	0x00000010  /* TX enabled */
#define CDNS_UART_CR_RX_DIS	0x00000008  /* RX disabled. */
#define CDNS_UART_CR_RX_EN	0x00000004  /* RX enabled */
#define CDNS_UART_CR_TXRST	0x00000002  /* TX logic reset */
#define CDNS_UART_CR_RXRST	0x00000001  /* RX logic reset */
#define CDNS_UART_CR_RST_TO	0x00000040  /* Restart Timeout Counter */
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#define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
#define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
#define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
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/*
 * Mode Register:
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 * The mode register (MR) defines the mode of transfer as well as the data
 * format. If this register is modified during transmission or reception,
 * data validity cannot be guaranteed.
 */
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#define CDNS_UART_MR_CLKSEL		0x00000001  /* Pre-scalar selection */
#define CDNS_UART_MR_CHMODE_L_LOOP	0x00000200  /* Local loop back mode */
#define CDNS_UART_MR_CHMODE_NORM	0x00000000  /* Normal mode */
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#define CDNS_UART_MR_CHMODE_MASK	0x00000300  /* Mask for mode bits */
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#define CDNS_UART_MR_STOPMODE_2_BIT	0x00000080  /* 2 stop bits */
#define CDNS_UART_MR_STOPMODE_1_BIT	0x00000000  /* 1 stop bit */
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#define CDNS_UART_MR_PARITY_NONE	0x00000020  /* No parity mode */
#define CDNS_UART_MR_PARITY_MARK	0x00000018  /* Mark parity mode */
#define CDNS_UART_MR_PARITY_SPACE	0x00000010  /* Space parity mode */
#define CDNS_UART_MR_PARITY_ODD		0x00000008  /* Odd parity mode */
#define CDNS_UART_MR_PARITY_EVEN	0x00000000  /* Even parity mode */
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#define CDNS_UART_MR_CHARLEN_6_BIT	0x00000006  /* 6 bits data */
#define CDNS_UART_MR_CHARLEN_7_BIT	0x00000004  /* 7 bits data */
#define CDNS_UART_MR_CHARLEN_8_BIT	0x00000000  /* 8 bits data */
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/*
 * Interrupt Registers:
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 * Interrupt control logic uses the interrupt enable register (IER) and the
 * interrupt disable register (IDR) to set the value of the bits in the
 * interrupt mask register (IMR). The IMR determines whether to pass an
 * interrupt to the interrupt status register (ISR).
 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 * Reading either IER or IDR returns 0x00.
 * All four registers have the same bit definitions.
 */
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#define CDNS_UART_IXR_TOUT	0x00000100 /* RX Timeout error interrupt */
#define CDNS_UART_IXR_PARITY	0x00000080 /* Parity error interrupt */
#define CDNS_UART_IXR_FRAMING	0x00000040 /* Framing error interrupt */
#define CDNS_UART_IXR_OVERRUN	0x00000020 /* Overrun error interrupt */
#define CDNS_UART_IXR_TXFULL	0x00000010 /* TX FIFO Full interrupt */
#define CDNS_UART_IXR_TXEMPTY	0x00000008 /* TX FIFO empty interrupt */
#define CDNS_UART_ISR_RXEMPTY	0x00000002 /* RX FIFO empty interrupt */
#define CDNS_UART_IXR_RXTRIG	0x00000001 /* RX FIFO trigger interrupt */
#define CDNS_UART_IXR_RXFULL	0x00000004 /* RX FIFO full interrupt. */
#define CDNS_UART_IXR_RXEMPTY	0x00000002 /* RX FIFO empty interrupt. */
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#define CDNS_UART_IXR_RXMASK	0x000021e7 /* Valid RX bit mask */
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	/*
	 * Do not enable parity error interrupt for the following
	 * reason: When parity error interrupt is enabled, each Rx
	 * parity error always results in 2 events. The first one
	 * being parity error interrupt and the second one with a
	 * proper Rx interrupt with the incoming data.  Disabling
	 * parity error interrupt ensures better handling of parity
	 * error events. With this change, for a parity error case, we
	 * get a Rx interrupt with parity error set in ISR register
	 * and we still handle parity errors in the desired way.
	 */

#define CDNS_UART_RX_IRQS	(CDNS_UART_IXR_FRAMING | \
				 CDNS_UART_IXR_OVERRUN | \
				 CDNS_UART_IXR_RXTRIG |	 \
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				 CDNS_UART_IXR_TOUT)

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/* Goes in read_status_mask for break detection as the HW doesn't do it*/
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#define CDNS_UART_IXR_BRK	0x00002000
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#define CDNS_UART_RXBS_SUPPORT BIT(1)
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/*
 * Modem Control register:
 * The read/write Modem Control register controls the interface with the modem
 * or data set, or a peripheral device emulating a modem.
 */
#define CDNS_UART_MODEMCR_FCM	0x00000020 /* Automatic flow control mode */
#define CDNS_UART_MODEMCR_RTS	0x00000002 /* Request to send output control */
#define CDNS_UART_MODEMCR_DTR	0x00000001 /* Data Terminal Ready */

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/*
 * Modem Status register:
 * The read/write Modem Status register reports the interface with the modem
 * or data set, or a peripheral device emulating a modem.
 */
#define CDNS_UART_MODEMSR_DCD	BIT(7) /* Data Carrier Detect */
#define CDNS_UART_MODEMSR_RI	BIT(6) /* Ting Indicator */
#define CDNS_UART_MODEMSR_DSR	BIT(5) /* Data Set Ready */
#define CDNS_UART_MODEMSR_CTS	BIT(4) /* Clear To Send */

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/*
 * Channel Status Register:
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 * The channel status register (CSR) is provided to enable the control logic
 * to monitor the status of bits in the channel interrupt status register,
 * even if these are masked out by the interrupt mask register.
 */
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#define CDNS_UART_SR_RXEMPTY	0x00000002 /* RX FIFO empty */
#define CDNS_UART_SR_TXEMPTY	0x00000008 /* TX FIFO empty */
#define CDNS_UART_SR_TXFULL	0x00000010 /* TX FIFO full */
#define CDNS_UART_SR_RXTRIG	0x00000001 /* Rx Trigger */
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#define CDNS_UART_SR_TACTIVE	0x00000800 /* TX state machine active */
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/* baud dividers min/max values */
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#define CDNS_UART_BDIV_MIN	4
#define CDNS_UART_BDIV_MAX	255
#define CDNS_UART_CD_MAX	65535
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#define UART_AUTOSUSPEND_TIMEOUT	3000
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/**
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 * struct cdns_uart - device data
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 * @port:		Pointer to the UART port
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 * @uartclk:		Reference clock
 * @pclk:		APB clock
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 * @cdns_uart_driver:	Pointer to UART driver
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 * @baud:		Current baud rate
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 * @id:			Port ID
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 * @clk_rate_change_nb:	Notifier block for clock changes
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 * @quirks:		Flags for RXBS support.
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 */
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struct cdns_uart {
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	struct uart_port	*port;
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	struct clk		*uartclk;
	struct clk		*pclk;
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	struct uart_driver	*cdns_uart_driver;
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	unsigned int		baud;
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	int			id;
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	struct notifier_block	clk_rate_change_nb;
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	u32			quirks;
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	bool cts_override;
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};
struct cdns_platform_data {
	u32 quirks;
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};
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#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
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		clk_rate_change_nb)
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/**
 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 * @dev_id: Id of the UART port
 * @isrstatus: The interrupt status register value as read
 * Return: None
 */
static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
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{
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	struct uart_port *port = (struct uart_port *)dev_id;
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	struct cdns_uart *cdns_uart = port->private_data;
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	unsigned int data;
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	unsigned int rxbs_status = 0;
	unsigned int status_mask;
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	unsigned int framerrprocessed = 0;
	char status = TTY_NORMAL;
	bool is_rxbs_support;
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	is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;

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	while ((readl(port->membase + CDNS_UART_SR) &
		CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
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		if (is_rxbs_support)
			rxbs_status = readl(port->membase + CDNS_UART_RXBS);
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		data = readl(port->membase + CDNS_UART_FIFO);
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		port->icount.rx++;
		/*
		 * There is no hardware break detection in Zynq, so we interpret
		 * framing error with all-zeros data as a break sequence.
		 * Most of the time, there's another non-zero byte at the
		 * end of the sequence.
		 */
		if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
			if (!data) {
				port->read_status_mask |= CDNS_UART_IXR_BRK;
				framerrprocessed = 1;
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				continue;
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			}
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		}
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		if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
			port->icount.brk++;
			status = TTY_BREAK;
			if (uart_handle_break(port))
				continue;
		}
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		isrstatus &= port->read_status_mask;
		isrstatus &= ~port->ignore_status_mask;
		status_mask = port->read_status_mask;
		status_mask &= ~port->ignore_status_mask;

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		if (data &&
		    (port->read_status_mask & CDNS_UART_IXR_BRK)) {
			port->read_status_mask &= ~CDNS_UART_IXR_BRK;
			port->icount.brk++;
			if (uart_handle_break(port))
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				continue;
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		}
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		if (uart_handle_sysrq_char(port, data))
			continue;

		if (is_rxbs_support) {
			if ((rxbs_status & CDNS_UART_RXBS_PARITY)
			    && (status_mask & CDNS_UART_IXR_PARITY)) {
				port->icount.parity++;
				status = TTY_PARITY;
			}
			if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
			    && (status_mask & CDNS_UART_IXR_PARITY)) {
				port->icount.frame++;
				status = TTY_FRAME;
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			}
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		} else {
			if (isrstatus & CDNS_UART_IXR_PARITY) {
				port->icount.parity++;
				status = TTY_PARITY;
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			}
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			if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
			    !framerrprocessed) {
				port->icount.frame++;
				status = TTY_FRAME;
			}
		}
		if (isrstatus & CDNS_UART_IXR_OVERRUN) {
			port->icount.overrun++;
			tty_insert_flip_char(&port->state->port, 0,
					     TTY_OVERRUN);
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		}
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		tty_insert_flip_char(&port->state->port, data, status);
		isrstatus = 0;
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	}
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	spin_unlock(&port->lock);
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	tty_flip_buffer_push(&port->state->port);
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	spin_lock(&port->lock);
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}

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/**
 * cdns_uart_handle_tx - Handle the bytes to be Txed.
 * @dev_id: Id of the UART port
 * Return: None
 */
static void cdns_uart_handle_tx(void *dev_id)
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{
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	struct uart_port *port = (struct uart_port *)dev_id;
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	unsigned int numbytes;

	if (uart_circ_empty(&port->state->xmit)) {
		writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
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	} else {
		numbytes = port->fifosize;
		while (numbytes && !uart_circ_empty(&port->state->xmit) &&
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		       !(readl(port->membase + CDNS_UART_SR) &
						CDNS_UART_SR_TXFULL)) {
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			/*
			 * Get the data from the UART circular buffer
			 * and write it to the cdns_uart's TX_FIFO
			 * register.
			 */
			writel(
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				port->state->xmit.buf[port->state->xmit.tail],
					port->membase + CDNS_UART_FIFO);
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			port->icount.tx++;

			/*
			 * Adjust the tail of the UART buffer and wrap
			 * the buffer if it reaches limit.
			 */
			port->state->xmit.tail =
				(port->state->xmit.tail + 1) &
					(UART_XMIT_SIZE - 1);

			numbytes--;
		}
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		if (uart_circ_chars_pending(
				&port->state->xmit) < WAKEUP_CHARS)
			uart_write_wakeup(port);
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	}
}

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/**
 * cdns_uart_isr - Interrupt handler
 * @irq: Irq number
 * @dev_id: Id of the port
 *
 * Return: IRQHANDLED
 */
static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
{
	struct uart_port *port = (struct uart_port *)dev_id;
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	unsigned int isrstatus;
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	spin_lock(&port->lock);
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	/* Read the interrupt status register to determine which
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	 * interrupt(s) is/are active and clear them.
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	 */
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	isrstatus = readl(port->membase + CDNS_UART_ISR);
	writel(isrstatus, port->membase + CDNS_UART_ISR);
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	if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
		cdns_uart_handle_tx(dev_id);
		isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
	}
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	/*
	 * Skip RX processing if RX is disabled as RXEMPTY will never be set
	 * as read bytes will not be removed from the FIFO.
	 */
	if (isrstatus & CDNS_UART_IXR_RXMASK &&
	    !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
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		cdns_uart_handle_rx(dev_id, isrstatus);
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	spin_unlock(&port->lock);
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	return IRQ_HANDLED;
}

/**
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 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
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 * @clk: UART module input clock
 * @baud: Desired baud rate
 * @rbdiv: BDIV value (return value)
 * @rcd: CD value (return value)
 * @div8: Value for clk_sel bit in mod (return value)
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 * Return: baud rate, requested baud when possible, or actual baud when there
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 *	was too much error, zero if no valid divisors are found.
 *
 * Formula to obtain baud rate is
 *	baud_tx/rx rate = clk/CD * (BDIV + 1)
 *	input_clk = (Uart User Defined Clock or Apb Clock)
 *		depends on UCLKEN in MR Reg
 *	clk = input_clk or input_clk/8;
 *		depends on CLKS in MR reg
 *	CD and BDIV depends on values in
 *			baud rate generate register
 *			baud rate clock divisor register
 */
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static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
		unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
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{
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	u32 cd, bdiv;
	unsigned int calc_baud;
	unsigned int bestbaud = 0;
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	unsigned int bauderror;
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	unsigned int besterror = ~0;
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	if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
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		*div8 = 1;
		clk /= 8;
	} else {
		*div8 = 0;
	}
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	for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
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		cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
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		if (cd < 1 || cd > CDNS_UART_CD_MAX)
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			continue;

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		calc_baud = clk / (cd * (bdiv + 1));
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		if (baud > calc_baud)
			bauderror = baud - calc_baud;
		else
			bauderror = calc_baud - baud;

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		if (besterror > bauderror) {
			*rbdiv = bdiv;
			*rcd = cd;
			bestbaud = calc_baud;
			besterror = bauderror;
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		}
	}
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	/* use the values when percent error is acceptable */
	if (((besterror * 100) / baud) < 3)
		bestbaud = baud;

	return bestbaud;
}
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/**
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 * cdns_uart_set_baud_rate - Calculate and set the baud rate
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 * @port: Handle to the uart port structure
 * @baud: Baud rate to set
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 * Return: baud rate, requested baud when possible, or actual baud when there
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 *	   was too much error, zero if no valid divisors are found.
 */
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static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
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		unsigned int baud)
{
	unsigned int calc_baud;
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	u32 cd = 0, bdiv = 0;
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	u32 mreg;
	int div8;
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	struct cdns_uart *cdns_uart = port->private_data;
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	calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
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			&div8);

	/* Write new divisors to hardware */
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	mreg = readl(port->membase + CDNS_UART_MR);
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	if (div8)
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		mreg |= CDNS_UART_MR_CLKSEL;
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	else
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		mreg &= ~CDNS_UART_MR_CLKSEL;
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	writel(mreg, port->membase + CDNS_UART_MR);
	writel(cd, port->membase + CDNS_UART_BAUDGEN);
	writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
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	cdns_uart->baud = baud;
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	return calc_baud;
}

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#ifdef CONFIG_COMMON_CLK
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/**
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 * cdns_uart_clk_notitifer_cb - Clock notifier callback
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 * @nb:		Notifier block
 * @event:	Notify event
 * @data:	Notifier data
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 * Return:	NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
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 */
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static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
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		unsigned long event, void *data)
{
	u32 ctrl_reg;
	struct uart_port *port;
	int locked = 0;
	struct clk_notifier_data *ndata = data;
	unsigned long flags = 0;
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	struct cdns_uart *cdns_uart = to_cdns_uart(nb);
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	port = cdns_uart->port;
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	if (port->suspended)
		return NOTIFY_OK;

	switch (event) {
	case PRE_RATE_CHANGE:
	{
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		u32 bdiv, cd;
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		int div8;

		/*
		 * Find out if current baud-rate can be achieved with new clock
		 * frequency.
		 */
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		if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
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					&bdiv, &cd, &div8)) {
			dev_warn(port->dev, "clock rate change rejected\n");
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			return NOTIFY_BAD;
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		}
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		spin_lock_irqsave(&cdns_uart->port->lock, flags);
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		/* Disable the TX and RX to set baud rate */
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		ctrl_reg = readl(port->membase + CDNS_UART_CR);
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		ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
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		writel(ctrl_reg, port->membase + CDNS_UART_CR);
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		spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
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		return NOTIFY_OK;
	}
	case POST_RATE_CHANGE:
		/*
		 * Set clk dividers to generate correct baud with new clock
		 * frequency.
		 */

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		spin_lock_irqsave(&cdns_uart->port->lock, flags);
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		locked = 1;
		port->uartclk = ndata->new_rate;

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		cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
				cdns_uart->baud);
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		/* fall through */
	case ABORT_RATE_CHANGE:
		if (!locked)
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			spin_lock_irqsave(&cdns_uart->port->lock, flags);
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		/* Set TX/RX Reset */
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		ctrl_reg = readl(port->membase + CDNS_UART_CR);
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		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
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		writel(ctrl_reg, port->membase + CDNS_UART_CR);
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		while (readl(port->membase + CDNS_UART_CR) &
558
				(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
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			cpu_relax();

		/*
		 * Clear the RX disable and TX disable bits and then set the TX
		 * enable bit and RX enable bit to enable the transmitter and
		 * receiver.
		 */
566 567
		writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
		ctrl_reg = readl(port->membase + CDNS_UART_CR);
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		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
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		writel(ctrl_reg, port->membase + CDNS_UART_CR);
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572
		spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
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		return NOTIFY_OK;
	default:
		return NOTIFY_DONE;
	}
}
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#endif
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/**
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 * cdns_uart_start_tx -  Start transmitting bytes
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 * @port: Handle to the uart port structure
584
 */
585
static void cdns_uart_start_tx(struct uart_port *port)
586
{
587
	unsigned int status;
588

589
	if (uart_tx_stopped(port))
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		return;

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	/*
	 * Set the TX enable bit and clear the TX disable bit to enable the
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	 * transmitter.
	 */
596
	status = readl(port->membase + CDNS_UART_CR);
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	status &= ~CDNS_UART_CR_TX_DIS;
	status |= CDNS_UART_CR_TX_EN;
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	writel(status, port->membase + CDNS_UART_CR);
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	if (uart_circ_empty(&port->state->xmit))
		return;

604
	cdns_uart_handle_tx(port);
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606
	writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
607
	/* Enable the TX Empty interrupt */
608
	writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
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}

/**
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 * cdns_uart_stop_tx - Stop TX
613
 * @port: Handle to the uart port structure
614
 */
615
static void cdns_uart_stop_tx(struct uart_port *port)
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{
	unsigned int regval;

619
	regval = readl(port->membase + CDNS_UART_CR);
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	regval |= CDNS_UART_CR_TX_DIS;
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	/* Disable the transmitter */
622
	writel(regval, port->membase + CDNS_UART_CR);
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}

/**
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 * cdns_uart_stop_rx - Stop RX
627
 * @port: Handle to the uart port structure
628
 */
629
static void cdns_uart_stop_rx(struct uart_port *port)
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{
	unsigned int regval;

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	/* Disable RX IRQs */
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	writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
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	/* Disable the receiver */
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	regval = readl(port->membase + CDNS_UART_CR);
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	regval |= CDNS_UART_CR_RX_DIS;
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	writel(regval, port->membase + CDNS_UART_CR);
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}

/**
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 * cdns_uart_tx_empty -  Check whether TX is empty
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 * @port: Handle to the uart port structure
 *
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 * Return: TIOCSER_TEMT on success, 0 otherwise
 */
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static unsigned int cdns_uart_tx_empty(struct uart_port *port)
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{
	unsigned int status;

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	status = readl(port->membase + CDNS_UART_SR) &
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		       (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);
	return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;
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}

/**
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 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
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 *			transmitting char breaks
 * @port: Handle to the uart port structure
 * @ctl: Value based on which start or stop decision is taken
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 */
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static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
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{
	unsigned int status;
	unsigned long flags;

	spin_lock_irqsave(&port->lock, flags);

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	status = readl(port->membase + CDNS_UART_CR);
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	if (ctl == -1)
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		writel(CDNS_UART_CR_STARTBRK | status,
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				port->membase + CDNS_UART_CR);
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	else {
676
		if ((status & CDNS_UART_CR_STOPBRK) == 0)
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			writel(CDNS_UART_CR_STOPBRK | status,
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					port->membase + CDNS_UART_CR);
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	}
	spin_unlock_irqrestore(&port->lock, flags);
}

/**
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 * cdns_uart_set_termios - termios operations, handling data length, parity,
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 *				stop bits, flow control, baud rate
 * @port: Handle to the uart port structure
 * @termios: Handle to the input termios structure
 * @old: Values of the previously saved termios structure
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 */
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static void cdns_uart_set_termios(struct uart_port *port,
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				struct ktermios *termios, struct ktermios *old)
{
693
	u32 cval = 0;
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	unsigned int baud, minbaud, maxbaud;
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	unsigned long flags;
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	unsigned int ctrl_reg, mode_reg;

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	spin_lock_irqsave(&port->lock, flags);
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	/* Disable the TX and RX to set baud rate */
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	ctrl_reg = readl(port->membase + CDNS_UART_CR);
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	ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
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	writel(ctrl_reg, port->membase + CDNS_UART_CR);
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	/*
	 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
	 * min and max baud should be calculated here based on port->uartclk.
	 * this way we get a valid baud and can safely call set_baud()
	 */
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	minbaud = port->uartclk /
			((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
	maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
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	baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
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	baud = cdns_uart_set_baud_rate(port, baud);
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	if (tty_termios_baud_rate(termios))
		tty_termios_encode_baud_rate(termios, baud, baud);

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	/* Update the per-port timeout. */
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	uart_update_timeout(port, termios->c_cflag, baud);

	/* Set TX/RX Reset */
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	ctrl_reg = readl(port->membase + CDNS_UART_CR);
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	ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
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	writel(ctrl_reg, port->membase + CDNS_UART_CR);
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	while (readl(port->membase + CDNS_UART_CR) &
		(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
		cpu_relax();

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	/*
	 * Clear the RX disable and TX disable bits and then set the TX enable
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	 * bit and RX enable bit to enable the transmitter and receiver.
	 */
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	ctrl_reg = readl(port->membase + CDNS_UART_CR);
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	ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
	ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
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	writel(ctrl_reg, port->membase + CDNS_UART_CR);
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	writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
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	port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
			CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
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	port->ignore_status_mask = 0;

	if (termios->c_iflag & INPCK)
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		port->read_status_mask |= CDNS_UART_IXR_PARITY |
		CDNS_UART_IXR_FRAMING;
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	if (termios->c_iflag & IGNPAR)
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		port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
			CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
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	/* ignore all characters if CREAD is not set */
	if ((termios->c_cflag & CREAD) == 0)
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		port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
			CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
			CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
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759
	mode_reg = readl(port->membase + CDNS_UART_MR);
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	/* Handling Data Size */
	switch (termios->c_cflag & CSIZE) {
	case CS6:
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		cval |= CDNS_UART_MR_CHARLEN_6_BIT;
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		break;
	case CS7:
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		cval |= CDNS_UART_MR_CHARLEN_7_BIT;
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		break;
	default:
	case CS8:
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		cval |= CDNS_UART_MR_CHARLEN_8_BIT;
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		termios->c_cflag &= ~CSIZE;
		termios->c_cflag |= CS8;
		break;
	}

	/* Handling Parity and Stop Bits length */
	if (termios->c_cflag & CSTOPB)
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		cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
780
	else
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		cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
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	if (termios->c_cflag & PARENB) {
		/* Mark or Space parity */
		if (termios->c_cflag & CMSPAR) {
			if (termios->c_cflag & PARODD)
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				cval |= CDNS_UART_MR_PARITY_MARK;
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			else
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				cval |= CDNS_UART_MR_PARITY_SPACE;
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		} else {
			if (termios->c_cflag & PARODD)
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				cval |= CDNS_UART_MR_PARITY_ODD;
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			else
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				cval |= CDNS_UART_MR_PARITY_EVEN;
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		}
	} else {
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		cval |= CDNS_UART_MR_PARITY_NONE;
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	}
	cval |= mode_reg & 1;
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	writel(cval, port->membase + CDNS_UART_MR);
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	cval = readl(port->membase + CDNS_UART_MODEMCR);
	if (termios->c_cflag & CRTSCTS)
		cval |= CDNS_UART_MODEMCR_FCM;
	else
		cval &= ~CDNS_UART_MODEMCR_FCM;
	writel(cval, port->membase + CDNS_UART_MODEMCR);

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	spin_unlock_irqrestore(&port->lock, flags);
}

/**
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 * cdns_uart_startup - Called when an application opens a cdns_uart port
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 * @port: Handle to the uart port structure
 *
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 * Return: 0 on success, negative errno otherwise
817
 */
818
static int cdns_uart_startup(struct uart_port *port)
819
{
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	struct cdns_uart *cdns_uart = port->private_data;
	bool is_brk_support;
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	int ret;
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	unsigned long flags;
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	unsigned int status = 0;
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	is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;

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	spin_lock_irqsave(&port->lock, flags);

830
	/* Disable the TX and RX */
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	writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
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			port->membase + CDNS_UART_CR);
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	/* Set the Control Register with TX/RX Enable, TX/RX Reset,
	 * no break chars.
	 */
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	writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
838
			port->membase + CDNS_UART_CR);
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	while (readl(port->membase + CDNS_UART_CR) &
		(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
		cpu_relax();

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	/*
	 * Clear the RX disable bit and then set the RX enable bit to enable
	 * the receiver.
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	 */
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	status = readl(port->membase + CDNS_UART_CR);
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	status &= ~CDNS_UART_CR_RX_DIS;
850
	status |= CDNS_UART_CR_RX_EN;
851
	writel(status, port->membase + CDNS_UART_CR);
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	/* Set the Mode Register with normal mode,8 data bits,1 stop bit,
	 * no parity.
	 */
856
	writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
857
		| CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
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		port->membase + CDNS_UART_MR);
859

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	/*
	 * Set the RX FIFO Trigger level to use most of the FIFO, but it
	 * can be tuned with a module parameter
	 */
864
	writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
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866 867 868 869
	/*
	 * Receive Timeout register is enabled but it
	 * can be tuned with a module parameter
	 */
870
	writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
871

872
	/* Clear out any pending interrupts before enabling them */
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	writel(readl(port->membase + CDNS_UART_ISR),
			port->membase + CDNS_UART_ISR);
875

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	spin_unlock_irqrestore(&port->lock, flags);

	ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
	if (ret) {
		dev_err(port->dev, "request_irq '%d' failed with %d\n",
			port->irq, ret);
		return ret;
	}

885
	/* Set the Interrupt Registers with desired interrupts */
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	if (is_brk_support)
		writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
					port->membase + CDNS_UART_IER);
	else
		writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
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892
	return 0;
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}

/**
896
 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
897
 * @port: Handle to the uart port structure
898
 */
899
static void cdns_uart_shutdown(struct uart_port *port)
900 901
{
	int status;
902 903 904
	unsigned long flags;

	spin_lock_irqsave(&port->lock, flags);
905 906

	/* Disable interrupts */
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	status = readl(port->membase + CDNS_UART_IMR);
	writel(status, port->membase + CDNS_UART_IDR);
	writel(0xffffffff, port->membase + CDNS_UART_ISR);
910 911

	/* Disable the TX and RX */
912
	writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
913
			port->membase + CDNS_UART_CR);
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	spin_unlock_irqrestore(&port->lock, flags);

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	free_irq(port->irq, port);
}

/**
921
 * cdns_uart_type - Set UART type to cdns_uart port
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 * @port: Handle to the uart port structure
 *
924 925
 * Return: string on success, NULL otherwise
 */
926
static const char *cdns_uart_type(struct uart_port *port)
927
{
928
	return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
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}

/**
932
 * cdns_uart_verify_port - Verify the port params
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 * @port: Handle to the uart port structure
 * @ser: Handle to the structure whose members are compared
 *
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 * Return: 0 on success, negative errno otherwise.
937
 */
938
static int cdns_uart_verify_port(struct uart_port *port,
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					struct serial_struct *ser)
{
	if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
		return -EINVAL;
	if (port->irq != ser->irq)
		return -EINVAL;
	if (ser->io_type != UPIO_MEM)
		return -EINVAL;
	if (port->iobase != ser->port)
		return -EINVAL;
	if (ser->hub6 != 0)
		return -EINVAL;
	return 0;
}

/**
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 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 *				called when the driver adds a cdns_uart port via
957 958 959
 *				uart_add_one_port()
 * @port: Handle to the uart port structure
 *
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 * Return: 0 on success, negative errno otherwise.
961
 */
962
static int cdns_uart_request_port(struct uart_port *port)
963
{
964 965
	if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
					 CDNS_UART_NAME)) {
966 967 968
		return -ENOMEM;
	}

969
	port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
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	if (!port->membase) {
		dev_err(port->dev, "Unable to map registers\n");
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		release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
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		return -ENOMEM;
	}
	return 0;
}

/**
979
 * cdns_uart_release_port - Release UART port
980
 * @port: Handle to the uart port structure
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981
 *
982 983
 * Release the memory region attached to a cdns_uart port. Called when the
 * driver removes a cdns_uart port via uart_remove_one_port().
984
 */
985
static void cdns_uart_release_port(struct uart_port *port)
986
{
987
	release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
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	iounmap(port->membase);
	port->membase = NULL;
}

/**
993
 * cdns_uart_config_port - Configure UART port
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 * @port: Handle to the uart port structure
 * @flags: If any
996
 */
997
static void cdns_uart_config_port(struct uart_port *port, int flags)
998
{
999
	if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
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		port->type = PORT_XUARTPS;
}

/**
1004
 * cdns_uart_get_mctrl - Get the modem control state
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 * @port: Handle to the uart port structure
 *
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 * Return: the modem control state
 */
1009
static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1010
{
1011 1012
	u32 val;
	unsigned int mctrl = 0;
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	struct cdns_uart *cdns_uart_data = port->private_data;

	if (cdns_uart_data->cts_override)
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		return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;

	val = readl(port->membase + CDNS_UART_MODEMSR);
	if (val & CDNS_UART_MODEMSR_CTS)
		mctrl |= TIOCM_CTS;
	if (val & CDNS_UART_MODEMSR_DSR)
		mctrl |= TIOCM_DSR;
	if (val & CDNS_UART_MODEMSR_RI)
		mctrl |= TIOCM_RNG;
	if (val & CDNS_UART_MODEMSR_DCD)
		mctrl |= TIOCM_CAR;

	return mctrl;
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}

1031
static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1032
{
1033
	u32 val;
1034
	u32 mode_reg;
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	struct cdns_uart *cdns_uart_data = port->private_data;

	if (cdns_uart_data->cts_override)
		return;
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1040
	val = readl(port->membase + CDNS_UART_MODEMCR);
1041
	mode_reg = readl(port->membase + CDNS_UART_MR);
1042

1043
	val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1044
	mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1045

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	if (mctrl & TIOCM_RTS)
		val |= CDNS_UART_MODEMCR_RTS;
	if (mctrl & TIOCM_DTR)
		val |= CDNS_UART_MODEMCR_DTR;
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	if (mctrl & TIOCM_LOOP)
		mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
	else
		mode_reg |= CDNS_UART_MR_CHMODE_NORM;
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1055
	writel(val, port->membase + CDNS_UART_MODEMCR);
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	writel(mode_reg, port->membase + CDNS_UART_MR);
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}

1059
#ifdef CONFIG_CONSOLE_POLL
1060
static int cdns_uart_poll_get_char(struct uart_port *port)
1061 1062
{
	int c;
1063
	unsigned long flags;
1064

1065
	spin_lock_irqsave(&port->lock, flags);
1066 1067

	/* Check if FIFO is empty */
1068
	if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1069 1070
		c = NO_POLL_CHAR;
	else /* Read a character */
1071
		c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
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1073
	spin_unlock_irqrestore(&port->lock, flags);
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	return c;
}

1078
static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1079
{
1080
	unsigned long flags;
1081

1082
	spin_lock_irqsave(&port->lock, flags);
1083 1084

	/* Wait until FIFO is empty */
1085
	while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
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		cpu_relax();

	/* Write a character */
1089
	writel(c, port->membase + CDNS_UART_FIFO);
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	/* Wait until FIFO is empty */
1092
	while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1093 1094
		cpu_relax();

1095
	spin_unlock_irqrestore(&port->lock, flags);
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}
#endif

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static void cdns_uart_pm(struct uart_port *port, unsigned int state,
		   unsigned int oldstate)
{
	switch (state) {
	case UART_PM_STATE_OFF:
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		pm_runtime_mark_last_busy(port->dev);
		pm_runtime_put_autosuspend(port->dev);
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		break;
	default:
1108
		pm_runtime_get_sync(port->dev);
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		break;
	}
}

1113
static const struct uart_ops cdns_uart_ops = {
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	.set_mctrl	= cdns_uart_set_mctrl,
	.get_mctrl	= cdns_uart_get_mctrl,
	.start_tx	= cdns_uart_start_tx,
	.stop_tx	= cdns_uart_stop_tx,
	.stop_rx	= cdns_uart_stop_rx,
	.tx_empty	= cdns_uart_tx_empty,
	.break_ctl	= cdns_uart_break_ctl,
	.set_termios	= cdns_uart_set_termios,
	.startup	= cdns_uart_startup,
	.shutdown	= cdns_uart_shutdown,
1124
	.pm		= cdns_uart_pm,
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	.type		= cdns_uart_type,
	.verify_port	= cdns_uart_verify_port,
	.request_port	= cdns_uart_request_port,
	.release_port	= cdns_uart_release_port,
	.config_port	= cdns_uart_config_port,
1130
#ifdef CONFIG_CONSOLE_POLL
1131 1132
	.poll_get_char	= cdns_uart_poll_get_char,
	.poll_put_char	= cdns_uart_poll_put_char,
1133
#endif
1134 1135 1136 1137
};

#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
/**
1138
 * cdns_uart_console_putchar - write the character to the FIFO buffer
1139 1140
 * @port: Handle to the uart port structure
 * @ch: Character to be written
1141
 */
1142
static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1143
{
1144 1145
	while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
		cpu_relax();
1146
	writel(ch, port->membase + CDNS_UART_FIFO);
1147 1148
}

1149
static void cdns_early_write(struct console *con, const char *s,
1150
				    unsigned n)
1151 1152 1153 1154 1155 1156 1157 1158 1159
{
	struct earlycon_device *dev = con->data;

	uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
}

static int __init cdns_early_console_setup(struct earlycon_device *device,
					   const char *opt)
{
1160 1161 1162
	struct uart_port *port = &device->port;

	if (!port->membase)
1163 1164
		return -ENODEV;

1165 1166 1167 1168 1169 1170 1171
	/* initialise control register */
	writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
	       port->membase + CDNS_UART_CR);

	/* only set baud if specified on command line - otherwise
	 * assume it has been initialized by a boot loader.
	 */
1172
	if (port->uartclk && device->baud) {
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		u32 cd = 0, bdiv = 0;
		u32 mr;
		int div8;

		cdns_uart_calc_baud_divs(port->uartclk, device->baud,
					 &bdiv, &cd, &div8);
		mr = CDNS_UART_MR_PARITY_NONE;
		if (div8)
			mr |= CDNS_UART_MR_CLKSEL;

		writel(mr,   port->membase + CDNS_UART_MR);
		writel(cd,   port->membase + CDNS_UART_BAUDGEN);
		writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
	}

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	device->con->write = cdns_early_write;

	return 0;
}
1192 1193 1194
OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1195
OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1196

1197 1198 1199 1200

/* Static pointer to console port */
static struct uart_port *console_port;

1201
/**
1202
 * cdns_uart_console_write - perform write operation
1203
 * @co: Console handle
1204 1205
 * @s: Pointer to character array
 * @count: No of characters
1206
 */
1207
static void cdns_uart_console_write(struct console *co, const char *s,
1208 1209
				unsigned int count)
{
1210
	struct uart_port *port = console_port;
1211
	unsigned long flags = 0;
1212
	unsigned int imr, ctrl;
1213 1214
	int locked = 1;

1215 1216 1217
	if (port->sysrq)
		locked = 0;
	else if (oops_in_progress)
1218 1219 1220 1221 1222
		locked = spin_trylock_irqsave(&port->lock, flags);
	else
		spin_lock_irqsave(&port->lock, flags);

	/* save and disable interrupt */
1223 1224
	imr = readl(port->membase + CDNS_UART_IMR);
	writel(imr, port->membase + CDNS_UART_IDR);
1225

1226 1227 1228 1229
	/*
	 * Make sure that the tx part is enabled. Set the TX enable bit and
	 * clear the TX disable bit to enable the transmitter.
	 */
1230
	ctrl = readl(port->membase + CDNS_UART_CR);
1231 1232
	ctrl &= ~CDNS_UART_CR_TX_DIS;
	ctrl |= CDNS_UART_CR_TX_EN;
1233
	writel(ctrl, port->membase + CDNS_UART_CR);
1234

1235
	uart_console_write(port, s, count, cdns_uart_console_putchar);
1236 1237 1238 1239
	while ((readl(port->membase + CDNS_UART_SR) &
			(CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
			CDNS_UART_SR_TXEMPTY)
		cpu_relax();
1240

1241
	/* restore interrupt state */
1242
	writel(imr, port->membase + CDNS_UART_IER);
1243 1244 1245 1246 1247 1248

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

/**
1249
 * cdns_uart_console_setup - Initialize the uart to default config
1250 1251 1252
 * @co: Console handle
 * @options: Initial settings of uart
 *
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Soren Brinkmann committed
1253
 * Return: 0 on success, negative errno otherwise.
1254
 */
1255
static int cdns_uart_console_setup(struct console *co, char *options)
1256
{
1257 1258
	struct uart_port *port = console_port;

1259 1260 1261 1262 1263
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

1264
	if (!port->membase) {
1265 1266
		pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
			 co->index);
1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
		return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}
#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */

1277 1278
#ifdef CONFIG_PM_SLEEP
/**
1279
 * cdns_uart_suspend - suspend event
1280 1281
 * @device: Pointer to the device structure
 *
1282
 * Return: 0
1283
 */
1284
static int cdns_uart_suspend(struct device *device)
1285 1286
{
	struct uart_port *port = dev_get_drvdata(device);
1287
	struct cdns_uart *cdns_uart = port->private_data;
1288
	int may_wake;
1289

1290 1291
	may_wake = device_may_wakeup(device);

1292
	if (console_suspend_enabled && uart_console(port) && may_wake) {
1293 1294 1295 1296
		unsigned long flags = 0;

		spin_lock_irqsave(&port->lock, flags);
		/* Empty the receive FIFO 1st before making changes */
1297
		while (!(readl(port->membase + CDNS_UART_SR) &
1298
					CDNS_UART_SR_RXEMPTY))
1299
			readl(port->membase + CDNS_UART_FIFO);
1300
		/* set RX trigger level to 1 */
1301
		writel(1, port->membase + CDNS_UART_RXWM);
1302
		/* disable RX timeout interrups */
1303
		writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1304 1305 1306
		spin_unlock_irqrestore(&port->lock, flags);
	}

1307 1308 1309 1310
	/*
	 * Call the API provided in serial_core.c file which handles
	 * the suspend.
	 */
1311
	return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1312 1313 1314
}

/**
1315
 * cdns_uart_resume - Resume after a previous suspend
1316 1317
 * @device: Pointer to the device structure
 *
1318
 * Return: 0
1319
 */
1320
static int cdns_uart_resume(struct device *device)
1321 1322
{
	struct uart_port *port = dev_get_drvdata(device);
1323
	struct cdns_uart *cdns_uart = port->private_data;
1324 1325
	unsigned long flags = 0;
	u32 ctrl_reg;
1326 1327 1328
	int may_wake;

	may_wake = device_may_wakeup(device);
1329

1330
	if (console_suspend_enabled && uart_console(port) && !may_wake) {
1331 1332
		clk_enable(cdns_uart->pclk);
		clk_enable(cdns_uart->uartclk);
1333 1334 1335 1336

		spin_lock_irqsave(&port->lock, flags);

		/* Set TX/RX Reset */
1337
		ctrl_reg = readl(port->membase + CDNS_UART_CR);
1338
		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1339 1340
		writel(ctrl_reg, port->membase + CDNS_UART_CR);
		while (readl(port->membase + CDNS_UART_CR) &
1341
				(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1342 1343 1344
			cpu_relax();

		/* restore rx timeout value */
1345
		writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1346
		/* Enable Tx/Rx */
1347
		ctrl_reg = readl(port->membase + CDNS_UART_CR);
1348 1349
		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1350
		writel(ctrl_reg, port->membase + CDNS_UART_CR);
1351

1352 1353
		clk_disable(cdns_uart->uartclk);
		clk_disable(cdns_uart->pclk);
1354 1355 1356 1357
		spin_unlock_irqrestore(&port->lock, flags);
	} else {
		spin_lock_irqsave(&port->lock, flags);
		/* restore original rx trigger level */
1358
		writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1359
		/* enable RX timeout interrupt */
1360
		writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
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		spin_unlock_irqrestore(&port->lock, flags);
	}

1364
	return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1365 1366
}
#endif /* ! CONFIG_PM_SLEEP */
1367 1368
static int __maybe_unused cdns_runtime_suspend(struct device *dev)
{
1369
	struct uart_port *port = dev_get_drvdata(dev);
1370
	struct cdns_uart *cdns_uart = port->private_data;
1371

1372 1373 1374 1375 1376 1377 1378
	clk_disable(cdns_uart->uartclk);
	clk_disable(cdns_uart->pclk);
	return 0;
};

static int __maybe_unused cdns_runtime_resume(struct device *dev)
{
1379
	struct uart_port *port = dev_get_drvdata(dev);
1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391
	struct cdns_uart *cdns_uart = port->private_data;

	clk_enable(cdns_uart->pclk);
	clk_enable(cdns_uart->uartclk);
	return 0;
};

static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
	SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
			   cdns_runtime_resume, NULL)
};
1392

1393 1394 1395 1396 1397 1398 1399 1400
static const struct cdns_platform_data zynqmp_uart_def = {
				.quirks = CDNS_UART_RXBS_SUPPORT, };

/* Match table for of_platform binding */
static const struct of_device_id cdns_uart_of_match[] = {
	{ .compatible = "xlnx,xuartps", },
	{ .compatible = "cdns,uart-r1p8", },
	{ .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1401
	{ .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1402 1403 1404 1405
	{}
};
MODULE_DEVICE_TABLE(of, cdns_uart_of_match);

1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430
/*
 * Maximum number of instances without alias IDs but if there is alias
 * which target "< MAX_UART_INSTANCES" range this ID can't be used.
 */
#define MAX_UART_INSTANCES	32

/* Stores static aliases list */
static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
static int alias_bitmap_initialized;

/* Stores actual bitmap of allocated IDs with alias IDs together */
static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
/* Protect bitmap operations to have unique IDs */
static DEFINE_MUTEX(bitmap_lock);

static int cdns_get_id(struct platform_device *pdev)
{
	int id, ret;

	mutex_lock(&bitmap_lock);

	/* Alias list is stable that's why get alias bitmap only once */
	if (!alias_bitmap_initialized) {
		ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
					      alias_bitmap, MAX_UART_INSTANCES);
1431
		if (ret && ret != -EOVERFLOW) {
1432
			mutex_unlock(&bitmap_lock);
1433
			return ret;
1434
		}
1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489

		alias_bitmap_initialized++;
	}

	/* Make sure that alias ID is not taken by instance without alias */
	bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);

	dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
		MAX_UART_INSTANCES, bitmap);

	/* Look for a serialN alias */
	id = of_alias_get_id(pdev->dev.of_node, "serial");
	if (id < 0) {
		dev_warn(&pdev->dev,
			 "No serial alias passed. Using the first free id\n");

		/*
		 * Start with id 0 and check if there is no serial0 alias
		 * which points to device which is compatible with this driver.
		 * If alias exists then try next free position.
		 */
		id = 0;

		for (;;) {
			dev_info(&pdev->dev, "Checking id %d\n", id);
			id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);

			/* No free empty instance */
			if (id == MAX_UART_INSTANCES) {
				dev_err(&pdev->dev, "No free ID\n");
				mutex_unlock(&bitmap_lock);
				return -EINVAL;
			}

			dev_dbg(&pdev->dev, "The empty id is %d\n", id);
			/* Check if ID is empty */
			if (!test_and_set_bit(id, bitmap)) {
				/* Break the loop if bit is taken */
				dev_dbg(&pdev->dev,
					"Selected ID %d allocation passed\n",
					id);
				break;
			}
			dev_dbg(&pdev->dev,
				"Selected ID %d allocation failed\n", id);
			/* if taking bit fails then try next one */
			id++;
		}
	}

	mutex_unlock(&bitmap_lock);

	return id;
}

1490
/**
1491
 * cdns_uart_probe - Platform driver probe
1492 1493
 * @pdev: Pointer to the platform device structure
 *
Soren Brinkmann's avatar
Soren Brinkmann committed
1494
 * Return: 0 on success, negative errno otherwise
1495
 */
1496
static int cdns_uart_probe(struct platform_device *pdev)
1497
{
1498
	int rc, irq;
1499
	struct uart_port *port;
1500
	struct resource *res;
1501
	struct cdns_uart *cdns_uart_data;
1502
	const struct of_device_id *match;
1503 1504 1505 1506 1507
	struct uart_driver *cdns_uart_uart_driver;
	char *driver_name;
#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
	struct console *cdns_uart_console;
#endif
1508

1509
	cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1510
			GFP_KERNEL);
1511
	if (!cdns_uart_data)
1512
		return -ENOMEM;
1513 1514 1515
	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;
1516

1517 1518 1519 1520 1521 1522
	cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
					     sizeof(*cdns_uart_uart_driver),
					     GFP_KERNEL);
	if (!cdns_uart_uart_driver)
		return -ENOMEM;

1523
	cdns_uart_data->id = cdns_get_id(pdev);
1524
	if (cdns_uart_data->id < 0)
1525
		return cdns_uart_data->id;
1526

1527 1528
	/* There is a need to use unique driver name */
	driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1529
				     CDNS_UART_NAME, cdns_uart_data->id);
1530 1531 1532 1533
	if (!driver_name) {
		rc = -ENOMEM;
		goto err_out_id;
	}
1534 1535 1536 1537

	cdns_uart_uart_driver->owner = THIS_MODULE;
	cdns_uart_uart_driver->driver_name = driver_name;
	cdns_uart_uart_driver->dev_name	= CDNS_UART_TTY_NAME;
1538
	cdns_uart_uart_driver->major = CDNS_UART_MAJOR;
1539
	cdns_uart_uart_driver->minor = cdns_uart_data->id;
1540 1541
	cdns_uart_uart_driver->nr = 1;

1542
#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1543 1544
	cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
					 GFP_KERNEL);
1545 1546
	if (!cdns_uart_console)
		return -ENOMEM;
1547 1548 1549

	strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
		sizeof(cdns_uart_console->name));
1550
	cdns_uart_console->index = cdns_uart_data->id;
1551 1552 1553 1554 1555 1556
	cdns_uart_console->write = cdns_uart_console_write;
	cdns_uart_console->device = uart_console_device;
	cdns_uart_console->setup = cdns_uart_console_setup;
	cdns_uart_console->flags = CON_PRINTBUFFER;
	cdns_uart_console->data = cdns_uart_uart_driver;
	cdns_uart_uart_driver->cons = cdns_uart_console;
1557 1558
#endif

1559 1560 1561
	rc = uart_register_driver(cdns_uart_uart_driver);
	if (rc < 0) {
		dev_err(&pdev->dev, "Failed to register driver\n");
1562
		goto err_out_id;
1563 1564
	}

1565 1566 1567 1568 1569 1570 1571
	cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;

	/*
	 * Setting up proper name_base needs to be done after uart
	 * registration because tty_driver structure is not filled.
	 * name_base is 0 by default.
	 */
1572
	cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1573

1574 1575 1576 1577 1578 1579 1580
	match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
	if (match && match->data) {
		const struct cdns_platform_data *data = match->data;

		cdns_uart_data->quirks = data->quirks;
	}

1581
	cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1582 1583 1584 1585 1586
	if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
		rc = PTR_ERR(cdns_uart_data->pclk);
		goto err_out_unregister_driver;
	}

1587 1588
	if (IS_ERR(cdns_uart_data->pclk)) {
		cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1589 1590 1591 1592 1593
		if (IS_ERR(cdns_uart_data->pclk)) {
			rc = PTR_ERR(cdns_uart_data->pclk);
			goto err_out_unregister_driver;
		}
		dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1594
	}
1595 1596 1597 1598

	cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
	if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
		rc = PTR_ERR(cdns_uart_data->uartclk);
1599
		goto err_out_unregister_driver;
1600 1601 1602 1603
	}

	if (IS_ERR(cdns_uart_data->uartclk)) {
		cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1604 1605 1606 1607 1608
		if (IS_ERR(cdns_uart_data->uartclk)) {
			rc = PTR_ERR(cdns_uart_data->uartclk);
			goto err_out_unregister_driver;
		}
		dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1609 1610
	}

1611
	rc = clk_prepare_enable(cdns_uart_data->pclk);
1612
	if (rc) {
1613
		dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1614
		goto err_out_unregister_driver;
1615
	}
1616
	rc = clk_prepare_enable(cdns_uart_data->uartclk);
1617
	if (rc) {
1618
		dev_err(&pdev->dev, "Unable to enable device clock.\n");
1619
		goto err_out_clk_dis_pclk;
1620 1621 1622
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1623 1624 1625 1626
	if (!res) {
		rc = -ENODEV;
		goto err_out_clk_disable;
	}
1627

1628 1629 1630
	irq = platform_get_irq(pdev, 0);
	if (irq <= 0) {
		rc = -ENXIO;
1631 1632
		goto err_out_clk_disable;
	}
1633

1634
#ifdef CONFIG_COMMON_CLK
1635 1636 1637 1638
	cdns_uart_data->clk_rate_change_nb.notifier_call =
			cdns_uart_clk_notifier_cb;
	if (clk_notifier_register(cdns_uart_data->uartclk,
				&cdns_uart_data->clk_rate_change_nb))
1639
		dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1640
#endif
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	/* At this point, we've got an empty uart_port struct, initialize it */
	spin_lock_init(&port->lock);
	port->type	= PORT_UNKNOWN;
	port->iotype	= UPIO_MEM32;
	port->flags	= UPF_BOOT_AUTOCONF;
	port->ops	= &cdns_uart_ops;
	port->fifosize	= CDNS_UART_FIFO_SIZE;
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	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
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	/*
	 * Register the port.
	 * This function also registers this device with the tty layer
	 * and triggers invocation of the config_port() entry point.
	 */
	port->mapbase = res->start;
	port->irq = irq;
	port->dev = &pdev->dev;
	port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
	port->private_data = cdns_uart_data;
	cdns_uart_data->port = port;
	platform_set_drvdata(pdev, port);

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	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
	pm_runtime_set_active(&pdev->dev);
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	pm_runtime_enable(&pdev->dev);
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	device_init_wakeup(port->dev, true);
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#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
	/*
	 * If console hasn't been found yet try to assign this port
	 * because it is required to be assigned for console setup function.
	 * If register_console() don't assign value, then console_port pointer
	 * is cleanup.
	 */
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	if (!console_port)
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		console_port = port;
#endif

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	rc = uart_add_one_port(cdns_uart_uart_driver, port);
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	if (rc) {
		dev_err(&pdev->dev,
			"uart_add_one_port() failed; err=%i\n", rc);
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		goto err_out_pm_disable;
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	}

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#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
	/* This is not port which is used for console that's why clean it up */
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	if (console_port == port &&
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	    !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
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		console_port = NULL;
#endif

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	cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
							     "cts-override");
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	return 0;

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err_out_pm_disable:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_set_suspended(&pdev->dev);
	pm_runtime_dont_use_autosuspend(&pdev->dev);
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#ifdef CONFIG_COMMON_CLK
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	clk_notifier_unregister(cdns_uart_data->uartclk,
			&cdns_uart_data->clk_rate_change_nb);
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#endif
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err_out_clk_disable:
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	clk_disable_unprepare(cdns_uart_data->uartclk);
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err_out_clk_dis_pclk:
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	clk_disable_unprepare(cdns_uart_data->pclk);
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err_out_unregister_driver:
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	uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
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err_out_id:
	mutex_lock(&bitmap_lock);
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	clear_bit(cdns_uart_data->id, bitmap);
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	mutex_unlock(&bitmap_lock);
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	return rc;
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}

/**
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 * cdns_uart_remove - called when the platform driver is unregistered
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 * @pdev: Pointer to the platform device structure
 *
Soren Brinkmann's avatar
Soren Brinkmann committed
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 * Return: 0 on success, negative errno otherwise
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 */
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static int cdns_uart_remove(struct platform_device *pdev)
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{
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	struct uart_port *port = platform_get_drvdata(pdev);
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	struct cdns_uart *cdns_uart_data = port->private_data;
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	int rc;
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	/* Remove the cdns_uart port from the serial core */
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#ifdef CONFIG_COMMON_CLK
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	clk_notifier_unregister(cdns_uart_data->uartclk,
			&cdns_uart_data->clk_rate_change_nb);
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#endif
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	rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
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	port->mapbase = 0;
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	mutex_lock(&bitmap_lock);
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	clear_bit(cdns_uart_data->id, bitmap);
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	mutex_unlock(&bitmap_lock);
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	clk_disable_unprepare(cdns_uart_data->uartclk);
	clk_disable_unprepare(cdns_uart_data->pclk);
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	pm_runtime_disable(&pdev->dev);
	pm_runtime_set_suspended(&pdev->dev);
	pm_runtime_dont_use_autosuspend(&pdev->dev);
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	device_init_wakeup(&pdev->dev, false);
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#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
	if (console_port == port)
		console_port = NULL;
#endif

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	uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
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	return rc;
}

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static struct platform_driver cdns_uart_platform_driver = {
	.probe   = cdns_uart_probe,
	.remove  = cdns_uart_remove,
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	.driver  = {
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		.name = CDNS_UART_NAME,
		.of_match_table = cdns_uart_of_match,
		.pm = &cdns_uart_dev_pm_ops,
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		.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
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		},
};

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static int __init cdns_uart_init(void)
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{
	/* Register the platform driver */
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	return platform_driver_register(&cdns_uart_platform_driver);
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}

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static void __exit cdns_uart_exit(void)
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{
	/* Unregister the platform driver */
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	platform_driver_unregister(&cdns_uart_platform_driver);
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}

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arch_initcall(cdns_uart_init);
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module_exit(cdns_uart_exit);
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MODULE_DESCRIPTION("Driver for Cadence UART");
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MODULE_AUTHOR("Xilinx Inc.");
MODULE_LICENSE("GPL");