setup_32.c 6.31 KB
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/*
 * Common prep/pmac/chrp boot and setup code.
 */

#include <linux/module.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include <linux/delay.h>
#include <linux/initrd.h>
#include <linux/tty.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/console.h>
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#include <linux/memblock.h>
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#include <linux/export.h>
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#include <asm/io.h>
#include <asm/prom.h>
#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/setup.h>
#include <asm/smp.h>
#include <asm/elf.h>
#include <asm/cputable.h>
#include <asm/bootx.h>
#include <asm/btext.h>
#include <asm/machdep.h>
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#include <linux/uaccess.h>
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#include <asm/pmac_feature.h>
#include <asm/sections.h>
#include <asm/nvram.h>
#include <asm/xmon.h>
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#include <asm/time.h>
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#include <asm/serial.h>
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#include <asm/udbg.h>
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#include <asm/code-patching.h>
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#include <asm/cpu_has_feature.h>
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#include <asm/asm-prototypes.h>
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#include <asm/kdump.h>
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#include <asm/feature-fixups.h>
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#include "setup.h"

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#define DBG(fmt...)

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extern void bootx_init(unsigned long r4, unsigned long phys);

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int boot_cpuid_phys;
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EXPORT_SYMBOL_GPL(boot_cpuid_phys);
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int smp_hw_index[NR_CPUS];
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EXPORT_SYMBOL(smp_hw_index);
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unsigned long ISA_DMA_THRESHOLD;
unsigned int DMA_MODE_READ;
unsigned int DMA_MODE_WRITE;

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EXPORT_SYMBOL(DMA_MODE_READ);
EXPORT_SYMBOL(DMA_MODE_WRITE);

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/*
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 * We're called here very early in the boot.
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 *
 * Note that the kernel may be running at an address which is different
 * from the address that it was linked at, so we must use RELOC/PTRRELOC
 * to access static data (including strings).  -- paulus
 */
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notrace unsigned long __init early_init(unsigned long dt_ptr)
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{
	unsigned long offset = reloc_offset();

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	/* First zero the BSS -- use memset_io, some platforms don't have
	 * caches on yet */
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	memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
			__bss_stop - __bss_start);
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	/*
	 * Identify the CPU type and fix up code sections
	 * that depend on which cpu we have.
	 */
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	identify_cpu(offset, mfspr(SPRN_PVR));
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	apply_feature_fixups();
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	return KERNELBASE + offset;
}


/*
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 * This is run before start_kernel(), the kernel has been relocated
 * and we are running with enough of the MMU enabled to have our
 * proper kernel virtual addresses
 *
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 * We do the initial parsing of the flat device-tree and prepares
 * for the MMU to be fully initialized.
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 */
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notrace void __init machine_init(u64 dt_ptr)
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{
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	unsigned int *addr = (unsigned int *)patch_site_addr(&patch__memset_nocache);
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	unsigned long insn;

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	/* Configure static keys first, now that we're relocated. */
	setup_feature_keys();

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	/* Enable early debugging if any specified (see udbg.h) */
	udbg_early_init();
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	patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP);
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	insn = create_cond_branch(addr, branch_target(addr), 0x820000);
	patch_instruction(addr, insn);	/* replace b by bne cr0 */
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	/* Do some early initialization based on the flat device tree */
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	early_init_devtree(__va(dt_ptr));

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	early_init_mmu();

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	setup_kdump_trampoline();
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}

/* Checks "l2cr=xxxx" command-line option */
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static int __init ppc_setup_l2cr(char *str)
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{
	if (cpu_has_feature(CPU_FTR_L2CR)) {
		unsigned long val = simple_strtoul(str, NULL, 0);
		printk(KERN_INFO "l2cr set to %lx\n", val);
		_set_L2CR(0);		/* force invalidate by disable cache */
		_set_L2CR(val);		/* and enable it */
	}
	return 1;
}
__setup("l2cr=", ppc_setup_l2cr);

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/* Checks "l3cr=xxxx" command-line option */
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static int __init ppc_setup_l3cr(char *str)
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{
	if (cpu_has_feature(CPU_FTR_L3CR)) {
		unsigned long val = simple_strtoul(str, NULL, 0);
		printk(KERN_INFO "l3cr set to %lx\n", val);
		_set_L3CR(val);		/* and enable it */
	}
	return 1;
}
__setup("l3cr=", ppc_setup_l3cr);

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#ifdef CONFIG_GENERIC_NVRAM

/* Generic nvram hooks used by drivers/char/gen_nvram.c */
unsigned char nvram_read_byte(int addr)
{
	if (ppc_md.nvram_read_val)
		return ppc_md.nvram_read_val(addr);
	return 0xff;
}
EXPORT_SYMBOL(nvram_read_byte);

void nvram_write_byte(unsigned char val, int addr)
{
	if (ppc_md.nvram_write_val)
		ppc_md.nvram_write_val(addr, val);
}
EXPORT_SYMBOL(nvram_write_byte);

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ssize_t nvram_get_size(void)
{
	if (ppc_md.nvram_size)
		return ppc_md.nvram_size();
	return -1;
}
EXPORT_SYMBOL(nvram_get_size);

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void nvram_sync(void)
{
	if (ppc_md.nvram_sync)
		ppc_md.nvram_sync();
}
EXPORT_SYMBOL(nvram_sync);

#endif /* CONFIG_NVRAM */

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static int __init ppc_init(void)
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{
	/* clear the progress line */
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	if (ppc_md.progress)
		ppc_md.progress("             ", 0xffff);
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	/* call platform init */
	if (ppc_md.init != NULL) {
		ppc_md.init();
	}
	return 0;
}
arch_initcall(ppc_init);

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static void *__init alloc_stack(void)
{
	void *ptr = memblock_alloc(THREAD_SIZE, THREAD_SIZE);

	if (!ptr)
		panic("cannot allocate %d bytes for stack at %pS\n",
		      THREAD_SIZE, (void *)_RET_IP_);

	return ptr;
}

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void __init irqstack_early_init(void)
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{
	unsigned int i;

	/* interrupt stacks must be in lowmem, we get that for free on ppc32
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	 * as the memblock is limited to lowmem by default */
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	for_each_possible_cpu(i) {
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		softirq_ctx[i] = alloc_stack();
		hardirq_ctx[i] = alloc_stack();
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	}
}

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#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
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void __init exc_lvl_early_init(void)
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{
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	unsigned int i, hw_cpu;
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	/* interrupt stacks must be in lowmem, we get that for free on ppc32
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	 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
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	for_each_possible_cpu(i) {
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#ifdef CONFIG_SMP
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		hw_cpu = get_hard_smp_processor_id(i);
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#else
		hw_cpu = 0;
#endif

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		critirq_ctx[hw_cpu] = alloc_stack();
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#ifdef CONFIG_BOOKE
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		dbgirq_ctx[hw_cpu] = alloc_stack();
		mcheckirq_ctx[hw_cpu] = alloc_stack();
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#endif
	}
}
#endif

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void __init setup_power_save(void)
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{
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#ifdef CONFIG_PPC_BOOK3S_32
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	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
	    cpu_has_feature(CPU_FTR_CAN_NAP))
		ppc_md.power_save = ppc6xx_idle;
#endif

#ifdef CONFIG_E500
	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
	    cpu_has_feature(CPU_FTR_CAN_NAP))
		ppc_md.power_save = e500_idle;
#endif
}

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__init void initialize_cache_info(void)
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{
	/*
	 * Set cache line size based on type of cpu as a default.
	 * Systems with OF can look in the properties on the cpu node(s)
	 * for a possibly more accurate value.
	 */
	dcache_bsize = cur_cpu_spec->dcache_bsize;
	icache_bsize = cur_cpu_spec->icache_bsize;
	ucache_bsize = 0;
	if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
		ucache_bsize = icache_bsize = dcache_bsize;
}