nv50_display.c 61.3 KB
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	/*
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 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

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#include <linux/dma-mapping.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
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#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_gem.h"
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#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"
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#include "nouveau_fence.h"
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#include "nv50_display.h"
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#include <core/client.h>
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#include <core/gpuobj.h>
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#include <core/class.h>
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#include <subdev/timer.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
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#include <subdev/i2c.h>
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#define EVO_DMA_NR 9

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#define EVO_MASTER  (0x00)
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#define EVO_FLIP(c) (0x01 + (c))
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#define EVO_OVLY(c) (0x05 + (c))
#define EVO_OIMM(c) (0x09 + (c))
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#define EVO_CURS(c) (0x0d + (c))

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/* offsets in shared sync bo of various structures */
#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
#define EVO_MAST_NTFY     EVO_SYNC(  0, 0x00)
#define EVO_FLIP_SEM0(c)  EVO_SYNC((c), 0x00)
#define EVO_FLIP_SEM1(c)  EVO_SYNC((c), 0x10)

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#define EVO_CORE_HANDLE      (0xd1500000)
#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
#define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
#define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) |                               \
			      (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))

/******************************************************************************
 * EVO channel
 *****************************************************************************/

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struct nv50_chan {
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	struct nouveau_object *user;
	u32 handle;
};

static int
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nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
		 void *data, u32 size, struct nv50_chan *chan)
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{
	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
	const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
	const u32 handle = EVO_CHAN_HANDLE(bclass, head);
	int ret;

	ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
				 oclass, data, size, &chan->user);
	if (ret)
		return ret;

	chan->handle = handle;
	return 0;
}

static void
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nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
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{
	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
	if (chan->handle)
		nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
}

/******************************************************************************
 * PIO EVO channel
 *****************************************************************************/

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struct nv50_pioc {
	struct nv50_chan base;
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};

static void
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nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
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{
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	nv50_chan_destroy(core, &pioc->base);
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}

static int
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nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
		 void *data, u32 size, struct nv50_pioc *pioc)
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{
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	return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
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}

/******************************************************************************
 * DMA EVO channel
 *****************************************************************************/

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struct nv50_dmac {
	struct nv50_chan base;
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	dma_addr_t handle;
	u32 *ptr;
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	/* Protects against concurrent pushbuf access to this channel, lock is
	 * grabbed by evo_wait (if the pushbuf reservation is successful) and
	 * dropped again by evo_kick. */
	struct mutex lock;
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};

static void
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nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
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{
	if (dmac->ptr) {
		struct pci_dev *pdev = nv_device(core)->pdev;
		pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
	}

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	nv50_chan_destroy(core, &dmac->base);
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}

static int
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nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
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{
	struct nouveau_fb *pfb = nouveau_fb(core);
	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
	struct nouveau_object *object;
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	int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
				     NV_DMA_IN_MEMORY_CLASS,
				     &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
					.conf0 = NV50_DMA_CONF0_ENABLE |
					         NV50_DMA_CONF0_PART_256,
				     }, sizeof(struct nv_dma_class), &object);
	if (ret)
		return ret;
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	ret = nouveau_object_new(client, parent, NvEvoFB16,
				 NV_DMA_IN_MEMORY_CLASS,
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				 &(struct nv_dma_class) {
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					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
					.conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
					         NV50_DMA_CONF0_PART_256,
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				 }, sizeof(struct nv_dma_class), &object);
	if (ret)
		return ret;

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	ret = nouveau_object_new(client, parent, NvEvoFB32,
				 NV_DMA_IN_MEMORY_CLASS,
				 &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
					.conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
					         NV50_DMA_CONF0_PART_256,
				 }, sizeof(struct nv_dma_class), &object);
	return ret;
}

static int
nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
{
	struct nouveau_fb *pfb = nouveau_fb(core);
	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
	struct nouveau_object *object;
	int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
				     NV_DMA_IN_MEMORY_CLASS,
				     &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
					.conf0 = NVC0_DMA_CONF0_ENABLE,
				     }, sizeof(struct nv_dma_class), &object);
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	if (ret)
		return ret;

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	ret = nouveau_object_new(client, parent, NvEvoFB16,
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				 NV_DMA_IN_MEMORY_CLASS,
				 &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
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					.start = 0,
					.limit = pfb->ram.size - 1,
					.conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
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				 }, sizeof(struct nv_dma_class), &object);
	if (ret)
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		return ret;
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	ret = nouveau_object_new(client, parent, NvEvoFB32,
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				 NV_DMA_IN_MEMORY_CLASS,
				 &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
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					.conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
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				 }, sizeof(struct nv_dma_class), &object);
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	return ret;
}

static int
nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
{
	struct nouveau_fb *pfb = nouveau_fb(core);
	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
	struct nouveau_object *object;
	int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
				     NV_DMA_IN_MEMORY_CLASS,
				     &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
					.conf0 = NVD0_DMA_CONF0_ENABLE |
						 NVD0_DMA_CONF0_PAGE_LP,
				     }, sizeof(struct nv_dma_class), &object);
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	if (ret)
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		return ret;
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	ret = nouveau_object_new(client, parent, NvEvoFB32,
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				 NV_DMA_IN_MEMORY_CLASS,
				 &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
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					.conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
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						 NVD0_DMA_CONF0_PAGE_LP,
				 }, sizeof(struct nv_dma_class), &object);
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	return ret;
}

static int
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nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
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		 void *data, u32 size, u64 syncbuf,
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		 struct nv50_dmac *dmac)
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{
	struct nouveau_fb *pfb = nouveau_fb(core);
	struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
	struct nouveau_object *object;
	u32 pushbuf = *(u32 *)data;
	int ret;

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	mutex_init(&dmac->lock);

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	dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
					&dmac->handle);
	if (!dmac->ptr)
		return -ENOMEM;

	ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
				 NV_DMA_FROM_MEMORY_CLASS,
				 &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_PCI_US |
						 NV_DMA_ACCESS_RD,
					.start = dmac->handle + 0x0000,
					.limit = dmac->handle + 0x0fff,
				 }, sizeof(struct nv_dma_class), &object);
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	if (ret)
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		return ret;
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	ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
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	if (ret)
		return ret;

	ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
				 NV_DMA_IN_MEMORY_CLASS,
				 &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = syncbuf + 0x0000,
					.limit = syncbuf + 0x0fff,
				 }, sizeof(struct nv_dma_class), &object);
	if (ret)
		return ret;

	ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
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				 NV_DMA_IN_MEMORY_CLASS,
				 &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = 0,
					.limit = pfb->ram.size - 1,
				 }, sizeof(struct nv_dma_class), &object);
	if (ret)
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		return ret;

	if (nv_device(core)->card_type < NV_C0)
		ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
	else
	if (nv_device(core)->card_type < NV_D0)
		ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
	else
		ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
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	return ret;
}

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struct nv50_mast {
	struct nv50_dmac base;
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};

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struct nv50_curs {
	struct nv50_pioc base;
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};

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struct nv50_sync {
	struct nv50_dmac base;
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	struct {
		u32 offset;
		u16 value;
	} sem;
};

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struct nv50_ovly {
	struct nv50_dmac base;
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};
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struct nv50_oimm {
	struct nv50_pioc base;
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};

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struct nv50_head {
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	struct nouveau_crtc base;
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	struct nv50_curs curs;
	struct nv50_sync sync;
	struct nv50_ovly ovly;
	struct nv50_oimm oimm;
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};

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#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
#define nv50_curs(c) (&nv50_head(c)->curs)
#define nv50_sync(c) (&nv50_head(c)->sync)
#define nv50_ovly(c) (&nv50_head(c)->ovly)
#define nv50_oimm(c) (&nv50_head(c)->oimm)
#define nv50_chan(c) (&(c)->base.base)
#define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
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struct nv50_disp {
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	struct nouveau_object *core;
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	struct nv50_mast mast;
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	u32 modeset;

	struct nouveau_bo *sync;
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};

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static struct nv50_disp *
nv50_disp(struct drm_device *dev)
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{
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	return nouveau_display(dev)->priv;
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}

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#define nv50_mast(d) (&nv50_disp(d)->mast)
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static struct drm_crtc *
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nv50_display_crtc_get(struct drm_encoder *encoder)
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{
	return nouveau_encoder(encoder)->crtc;
}

/******************************************************************************
 * EVO channel helpers
 *****************************************************************************/
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static u32 *
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evo_wait(void *evoc, int nr)
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{
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	struct nv50_dmac *dmac = evoc;
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	u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
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	mutex_lock(&dmac->lock);
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	if (put + nr >= (PAGE_SIZE / 4) - 8) {
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		dmac->ptr[put] = 0x20000000;
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		nv_wo32(dmac->base.user, 0x0000, 0x00000000);
		if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
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			mutex_unlock(&dmac->lock);
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			NV_ERROR(dmac->base.user, "channel stalled\n");
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			return NULL;
		}

		put = 0;
	}

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	return dmac->ptr + put;
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}

static void
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evo_kick(u32 *push, void *evoc)
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{
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	struct nv50_dmac *dmac = evoc;
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	nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
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	mutex_unlock(&dmac->lock);
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}

#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
#define evo_data(p,d)   *((p)++) = (d)

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static bool
evo_sync_wait(void *data)
{
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	if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
		return true;
	usleep_range(1, 2);
	return false;
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}

static int
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evo_sync(struct drm_device *dev)
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{
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	struct nouveau_device *device = nouveau_dev(dev);
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	struct nv50_disp *disp = nv50_disp(dev);
	struct nv50_mast *mast = nv50_mast(dev);
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	u32 *push = evo_wait(mast, 8);
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	if (push) {
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		nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
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		evo_mthd(push, 0x0084, 1);
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		evo_data(push, 0x80000000 | EVO_MAST_NTFY);
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		evo_mthd(push, 0x0080, 2);
		evo_data(push, 0x00000000);
		evo_data(push, 0x00000000);
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		evo_kick(push, mast);
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		if (nv_wait_cb(device, evo_sync_wait, disp->sync))
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			return 0;
	}

	return -EBUSY;
}

/******************************************************************************
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 * Page flipping channel
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 *****************************************************************************/
struct nouveau_bo *
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nv50_display_crtc_sema(struct drm_device *dev, int crtc)
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{
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	return nv50_disp(dev)->sync;
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}

void
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nv50_display_flip_stop(struct drm_crtc *crtc)
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{
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	struct nv50_sync *sync = nv50_sync(crtc);
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	u32 *push;

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	push = evo_wait(sync, 8);
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	if (push) {
		evo_mthd(push, 0x0084, 1);
		evo_data(push, 0x00000000);
		evo_mthd(push, 0x0094, 1);
		evo_data(push, 0x00000000);
		evo_mthd(push, 0x00c0, 1);
		evo_data(push, 0x00000000);
		evo_mthd(push, 0x0080, 1);
		evo_data(push, 0x00000000);
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		evo_kick(push, sync);
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	}
}

int
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nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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		       struct nouveau_channel *chan, u32 swap_interval)
{
	struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
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	struct nv50_disp *disp = nv50_disp(crtc->dev);
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	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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	struct nv50_sync *sync = nv50_sync(crtc);
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	u32 *push;
	int ret;

	swap_interval <<= 4;
	if (swap_interval == 0)
		swap_interval |= 0x100;

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	push = evo_wait(sync, 128);
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	if (unlikely(push == NULL))
		return -EBUSY;

	/* synchronise with the rendering channel, if necessary */
	if (likely(chan)) {
		ret = RING_SPACE(chan, 10);
		if (ret)
			return ret;

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		if (nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
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			BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
			OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
			OUT_RING  (chan, sync->sem.offset);
			BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
			OUT_RING  (chan, 0xf00d0000 | sync->sem.value);
			BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
			OUT_RING  (chan, sync->sem.offset ^ 0x10);
			OUT_RING  (chan, 0x74b1e000);
			BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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			OUT_RING  (chan, NvSema);
		} else
		if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
			u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
			offset += sync->sem.offset;

			BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
			OUT_RING  (chan, upper_32_bits(offset));
			OUT_RING  (chan, lower_32_bits(offset));
			OUT_RING  (chan, 0xf00d0000 | sync->sem.value);
			OUT_RING  (chan, 0x00000002);
			BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
			OUT_RING  (chan, upper_32_bits(offset));
			OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
			OUT_RING  (chan, 0x74b1e000);
			OUT_RING  (chan, 0x00000001);
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		} else {
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			u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
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			offset += sync->sem.offset;

			BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
			OUT_RING  (chan, upper_32_bits(offset));
			OUT_RING  (chan, lower_32_bits(offset));
			OUT_RING  (chan, 0xf00d0000 | sync->sem.value);
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			OUT_RING  (chan, 0x00001002);
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			BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
			OUT_RING  (chan, upper_32_bits(offset));
			OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
			OUT_RING  (chan, 0x74b1e000);
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			OUT_RING  (chan, 0x00001001);
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		}
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		FIRE_RING (chan);
	} else {
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		nouveau_bo_wr32(disp->sync, sync->sem.offset / 4,
				0xf00d0000 | sync->sem.value);
		evo_sync(crtc->dev);
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	}

	/* queue the flip */
	evo_mthd(push, 0x0100, 1);
	evo_data(push, 0xfffe0000);
	evo_mthd(push, 0x0084, 1);
	evo_data(push, swap_interval);
	if (!(swap_interval & 0x00000100)) {
		evo_mthd(push, 0x00e0, 1);
		evo_data(push, 0x40000000);
	}
	evo_mthd(push, 0x0088, 4);
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	evo_data(push, sync->sem.offset);
	evo_data(push, 0xf00d0000 | sync->sem.value);
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	evo_data(push, 0x74b1e000);
	evo_data(push, NvEvoSync);
	evo_mthd(push, 0x00a0, 2);
	evo_data(push, 0x00000000);
	evo_data(push, 0x00000000);
	evo_mthd(push, 0x00c0, 1);
	evo_data(push, nv_fb->r_dma);
	evo_mthd(push, 0x0110, 2);
	evo_data(push, 0x00000000);
	evo_data(push, 0x00000000);
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	if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
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		evo_mthd(push, 0x0800, 5);
		evo_data(push, nv_fb->nvbo->bo.offset >> 8);
		evo_data(push, 0);
		evo_data(push, (fb->height << 16) | fb->width);
		evo_data(push, nv_fb->r_pitch);
		evo_data(push, nv_fb->r_format);
	} else {
		evo_mthd(push, 0x0400, 5);
		evo_data(push, nv_fb->nvbo->bo.offset >> 8);
		evo_data(push, 0);
		evo_data(push, (fb->height << 16) | fb->width);
		evo_data(push, nv_fb->r_pitch);
		evo_data(push, nv_fb->r_format);
	}
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	evo_mthd(push, 0x0080, 1);
	evo_data(push, 0x00000000);
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	evo_kick(push, sync);
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	sync->sem.offset ^= 0x10;
	sync->sem.value++;
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	return 0;
}

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/******************************************************************************
 * CRTC
 *****************************************************************************/
static int
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nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
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{
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	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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	struct nouveau_connector *nv_connector;
	struct drm_connector *connector;
	u32 *push, mode = 0x00;
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	nv_connector = nouveau_crtc_connector_get(nv_crtc);
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	connector = &nv_connector->base;
	if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
		if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
			mode = DITHERING_MODE_DYNAMIC2X2;
	} else {
		mode = nv_connector->dithering_mode;
	}

	if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
		if (connector->display_info.bpc >= 8)
			mode |= DITHERING_DEPTH_8BPC;
	} else {
		mode |= nv_connector->dithering_depth;
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	}

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	push = evo_wait(mast, 4);
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	if (push) {
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		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
			evo_data(push, mode);
		} else
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		if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
			evo_data(push, mode);
		} else {
			evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
			evo_data(push, mode);
		}

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		if (update) {
			evo_mthd(push, 0x0080, 1);
			evo_data(push, 0x00000000);
		}
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		evo_kick(push, mast);
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	}

	return 0;
}

static int
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nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
667
{
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	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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	struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
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	struct drm_crtc *crtc = &nv_crtc->base;
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	struct nouveau_connector *nv_connector;
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	int mode = DRM_MODE_SCALE_NONE;
	u32 oX, oY, *push;
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	/* start off at the resolution we programmed the crtc for, this
	 * effectively handles NONE/FULL scaling
	 */
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	nv_connector = nouveau_crtc_connector_get(nv_crtc);
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	if (nv_connector && nv_connector->native_mode)
		mode = nv_connector->scaling_mode;

	if (mode != DRM_MODE_SCALE_NONE)
		omode = nv_connector->native_mode;
	else
		omode = umode;

	oX = omode->hdisplay;
	oY = omode->vdisplay;
	if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
		oY *= 2;

	/* add overscan compensation if necessary, will keep the aspect
	 * ratio the same as the backend mode unless overridden by the
	 * user setting both hborder and vborder properties.
	 */
	if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
			     (nv_connector->underscan == UNDERSCAN_AUTO &&
			      nv_connector->edid &&
			      drm_detect_hdmi_monitor(nv_connector->edid)))) {
		u32 bX = nv_connector->underscan_hborder;
		u32 bY = nv_connector->underscan_vborder;
		u32 aspect = (oY << 19) / oX;

		if (bX) {
			oX -= (bX * 2);
			if (bY) oY -= (bY * 2);
			else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
		} else {
			oX -= (oX >> 4) + 32;
			if (bY) oY -= (bY * 2);
			else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
		}
	}

	/* handle CENTER/ASPECT scaling, taking into account the areas
	 * removed already for overscan compensation
	 */
	switch (mode) {
	case DRM_MODE_SCALE_CENTER:
		oX = min((u32)umode->hdisplay, oX);
		oY = min((u32)umode->vdisplay, oY);
		/* fall-through */
	case DRM_MODE_SCALE_ASPECT:
		if (oY < oX) {
			u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
			oX = ((oY * aspect) + (aspect / 2)) >> 19;
		} else {
			u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
			oY = ((oX * aspect) + (aspect / 2)) >> 19;
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		}
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		break;
	default:
		break;
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	}
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	push = evo_wait(mast, 8);
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	if (push) {
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		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
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			/*XXX: SCALE_CTRL_ACTIVE??? */
			evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
			evo_data(push, (oY << 16) | oX);
			evo_data(push, (oY << 16) | oX);
			evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x00000000);
			evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
			evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
		} else {
			evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
			evo_data(push, (oY << 16) | oX);
			evo_data(push, (oY << 16) | oX);
			evo_data(push, (oY << 16) | oX);
			evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0x00000000);
			evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
			evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
		}

		evo_kick(push, mast);

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		if (update) {
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			nv50_display_flip_stop(crtc);
			nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
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		}
	}

	return 0;
}

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static int
770
nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
771
{
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	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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	u32 *push, hue, vib;
	int adj;

	adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
	vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
	hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;

	push = evo_wait(mast, 16);
	if (push) {
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		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
			evo_data(push, (hue << 20) | (vib << 8));
		} else {
			evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
			evo_data(push, (hue << 20) | (vib << 8));
		}

		if (update) {
			evo_mthd(push, 0x0080, 1);
			evo_data(push, 0x00000000);
		}
		evo_kick(push, mast);
	}

	return 0;
}

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static int
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nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
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		    int x, int y, bool update)
{
	struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
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	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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	u32 *push;

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	push = evo_wait(mast, 16);
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	if (push) {
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		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
			evo_data(push, nvfb->nvbo->bo.offset >> 8);
			evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
			evo_data(push, (fb->height << 16) | fb->width);
			evo_data(push, nvfb->r_pitch);
			evo_data(push, nvfb->r_format);
			evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
			evo_data(push, (y << 16) | x);
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			if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
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				evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
				evo_data(push, nvfb->r_dma);
			}
		} else {
			evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
			evo_data(push, nvfb->nvbo->bo.offset >> 8);
			evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
			evo_data(push, (fb->height << 16) | fb->width);
			evo_data(push, nvfb->r_pitch);
			evo_data(push, nvfb->r_format);
			evo_data(push, nvfb->r_dma);
			evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
			evo_data(push, (y << 16) | x);
		}

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		if (update) {
			evo_mthd(push, 0x0080, 1);
			evo_data(push, 0x00000000);
		}
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		evo_kick(push, mast);
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	}

842
	nv_crtc->fb.tile_flags = nvfb->r_dma;
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	return 0;
}

static void
847
nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
848
{
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	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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	u32 *push = evo_wait(mast, 16);
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	if (push) {
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		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
			evo_data(push, 0x85000000);
			evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
		} else
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		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
			evo_data(push, 0x85000000);
			evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
			evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
			evo_data(push, NvEvoVRAM);
		} else {
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			evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
			evo_data(push, 0x85000000);
			evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
			evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
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			evo_data(push, NvEvoVRAM);
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		}
		evo_kick(push, mast);
	}
}

static void
875
nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
876
{
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	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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	u32 *push = evo_wait(mast, 16);
	if (push) {
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		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x05000000);
		} else
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		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x05000000);
			evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x00000000);
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		} else {
			evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0x05000000);
			evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0x00000000);
		}
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		evo_kick(push, mast);
	}
}
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static void
900
nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
901
{
902
	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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	if (show)
905
		nv50_crtc_cursor_show(nv_crtc);
906
	else
907
		nv50_crtc_cursor_hide(nv_crtc);
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	if (update) {
		u32 *push = evo_wait(mast, 2);
		if (push) {
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			evo_mthd(push, 0x0080, 1);
			evo_data(push, 0x00000000);
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			evo_kick(push, mast);
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		}
	}
}

static void
920
nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
}

static void
925
nv50_crtc_prepare(struct drm_crtc *crtc)
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{
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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	struct nv50_mast *mast = nv50_mast(crtc->dev);
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	u32 *push;

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	nv50_display_flip_stop(crtc);
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	push = evo_wait(mast, 2);
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	if (push) {
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		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x00000000);
			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x40000000);
		} else
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		if (nv50_vers(mast) <  NVD0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x00000000);
			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x40000000);
			evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x00000000);
		} else {
			evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0x00000000);
			evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0x03000000);
			evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0x00000000);
		}

		evo_kick(push, mast);
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	}

960
	nv50_crtc_cursor_show_hide(nv_crtc, false, false);
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}

static void
964
nv50_crtc_commit(struct drm_crtc *crtc)
965 966
{
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
967
	struct nv50_mast *mast = nv50_mast(crtc->dev);
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	u32 *push;

970
	push = evo_wait(mast, 32);
971
	if (push) {
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		if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
			evo_data(push, NvEvoVRAM_LP);
			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
			evo_data(push, 0xc0000000);
			evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
		} else
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		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
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			evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
			evo_data(push, nv_crtc->fb.tile_flags);
			evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
			evo_data(push, 0xc0000000);
			evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
			evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
			evo_data(push, NvEvoVRAM);
		} else {
			evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
			evo_data(push, nv_crtc->fb.tile_flags);
			evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
			evo_data(push, 0x83000000);
			evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
			evo_data(push, 0x00000000);
			evo_data(push, 0x00000000);
			evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
			evo_data(push, NvEvoVRAM);
			evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0xffffff00);
		}

		evo_kick(push, mast);
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	}

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	nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
	nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
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}

static bool
1009
nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
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		     struct drm_display_mode *adjusted_mode)
{
	return true;
}

static int
1016
nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
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{
	struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
	int ret;

	ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
	if (ret)
		return ret;

	if (old_fb) {
		nvfb = nouveau_framebuffer(old_fb);
		nouveau_bo_unpin(nvfb->nvbo);
	}

	return 0;
}

static int
1034
nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
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		   struct drm_display_mode *mode, int x, int y,
		   struct drm_framebuffer *old_fb)
{
1038
	struct nv50_mast *mast = nv50_mast(crtc->dev);
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	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	struct nouveau_connector *nv_connector;
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	u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
	u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
	u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
	u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
	u32 vblan2e = 0, vblan2s = 1;
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	u32 *push;
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	int ret;

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	hactive = mode->htotal;
	hsynce  = mode->hsync_end - mode->hsync_start - 1;
	hbackp  = mode->htotal - mode->hsync_end;
	hblanke = hsynce + hbackp;
	hfrontp = mode->hsync_start - mode->hdisplay;
	hblanks = mode->htotal - hfrontp - 1;

	vactive = mode->vtotal * vscan / ilace;
	vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
	vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
	vblanke = vsynce + vbackp;
	vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
	vblanks = vactive - vfrontp - 1;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vblan2e = vactive + vsynce + vbackp;
		vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
		vactive = (vactive * 2) + 1;
	}

1068
	ret = nv50_crtc_swap_fbs(crtc, old_fb);
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	if (ret)
		return ret;

1072
	push = evo_wait(mast, 64);
1073
	if (push) {
1074
		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
			evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
			evo_data(push, 0x00800000 | mode->clock);
			evo_data(push, (ilace == 2) ? 2 : 0);
			evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
			evo_data(push, 0x00000000);
			evo_data(push, (vactive << 16) | hactive);
			evo_data(push, ( vsynce << 16) | hsynce);
			evo_data(push, (vblanke << 16) | hblanke);
			evo_data(push, (vblanks << 16) | hblanks);
			evo_data(push, (vblan2e << 16) | vblan2s);
			evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
			evo_data(push, 0x00000000);
			evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
			evo_data(push, 0x00000311);
			evo_data(push, 0x00000100);
		} else {
			evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
			evo_data(push, 0x00000000);
			evo_data(push, (vactive << 16) | hactive);
			evo_data(push, ( vsynce << 16) | hsynce);
			evo_data(push, (vblanke << 16) | hblanke);
			evo_data(push, (vblanks << 16) | hblanks);
			evo_data(push, (vblan2e << 16) | vblan2s);
			evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
			evo_data(push, 0x00000000); /* ??? */
			evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
			evo_data(push, mode->clock * 1000);
			evo_data(push, 0x00200000); /* ??? */
			evo_data(push, mode->clock * 1000);
			evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
			evo_data(push, 0x00000311);
			evo_data(push, 0x00000100);
		}

		evo_kick(push, mast);
1110 1111 1112
	}

	nv_connector = nouveau_crtc_connector_get(nv_crtc);
1113 1114 1115 1116
	nv50_crtc_set_dither(nv_crtc, false);
	nv50_crtc_set_scale(nv_crtc, false);
	nv50_crtc_set_color_vibrance(nv_crtc, false);
	nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
1117 1118 1119 1120
	return 0;
}

static int
1121
nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1122 1123
			struct drm_framebuffer *old_fb)
{
1124
	struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1125 1126 1127
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	int ret;

1128
	if (!crtc->fb) {
1129
		NV_DEBUG(drm, "No FB bound\n");
1130 1131 1132
		return 0;
	}

1133
	ret = nv50_crtc_swap_fbs(crtc, old_fb);
1134 1135 1136
	if (ret)
		return ret;

1137 1138 1139
	nv50_display_flip_stop(crtc);
	nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
	nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1140 1141 1142 1143
	return 0;
}

static int
1144
nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1145 1146 1147 1148
			       struct drm_framebuffer *fb, int x, int y,
			       enum mode_set_atomic state)
{
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1149 1150
	nv50_display_flip_stop(crtc);
	nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1151 1152 1153 1154
	return 0;
}

static void
1155
nv50_crtc_lut_load(struct drm_crtc *crtc)
1156
{
1157
	struct nv50_disp *disp = nv50_disp(crtc->dev);
1158 1159 1160 1161 1162
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
	int i;

	for (i = 0; i < 256; i++) {
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
		u16 r = nv_crtc->lut.r[i] >> 2;
		u16 g = nv_crtc->lut.g[i] >> 2;
		u16 b = nv_crtc->lut.b[i] >> 2;

		if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
			writew(r + 0x0000, lut + (i * 0x08) + 0);
			writew(g + 0x0000, lut + (i * 0x08) + 2);
			writew(b + 0x0000, lut + (i * 0x08) + 4);
		} else {
			writew(r + 0x6000, lut + (i * 0x20) + 0);
			writew(g + 0x6000, lut + (i * 0x20) + 2);
			writew(b + 0x6000, lut + (i * 0x20) + 4);
		}
1176 1177 1178 1179
	}
}

static int
1180
nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
		     uint32_t handle, uint32_t width, uint32_t height)
{
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct drm_gem_object *gem;
	struct nouveau_bo *nvbo;
	bool visible = (handle != 0);
	int i, ret = 0;

	if (visible) {
		if (width != 64 || height != 64)
			return -EINVAL;

		gem = drm_gem_object_lookup(dev, file_priv, handle);
		if (unlikely(!gem))
			return -ENOENT;
		nvbo = nouveau_gem_object(gem);

		ret = nouveau_bo_map(nvbo);
		if (ret == 0) {
			for (i = 0; i < 64 * 64; i++) {
				u32 v = nouveau_bo_rd32(nvbo, i);
				nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
			}
			nouveau_bo_unmap(nvbo);
		}

		drm_gem_object_unreference_unlocked(gem);
	}

	if (visible != nv_crtc->cursor.visible) {
1212
		nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1213 1214 1215 1216 1217 1218 1219
		nv_crtc->cursor.visible = visible;
	}

	return ret;
}

static int
1220
nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1221
{
1222 1223
	struct nv50_curs *curs = nv50_curs(crtc);
	struct nv50_chan *chan = nv50_chan(curs);
1224 1225
	nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
	nv_wo32(chan->user, 0x0080, 0x00000000);
1226 1227 1228 1229
	return 0;
}

static void
1230
nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
		    uint32_t start, uint32_t size)
{
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	u32 end = max(start + size, (u32)256);
	u32 i;

	for (i = start; i < end; i++) {
		nv_crtc->lut.r[i] = r[i];
		nv_crtc->lut.g[i] = g[i];
		nv_crtc->lut.b[i] = b[i];
	}

1243
	nv50_crtc_lut_load(crtc);
1244 1245 1246
}

static void
1247
nv50_crtc_destroy(struct drm_crtc *crtc)
1248 1249
{
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1250 1251 1252 1253 1254 1255
	struct nv50_disp *disp = nv50_disp(crtc->dev);
	struct nv50_head *head = nv50_head(crtc);
	nv50_dmac_destroy(disp->core, &head->ovly.base);
	nv50_pioc_destroy(disp->core, &head->oimm.base);
	nv50_dmac_destroy(disp->core, &head->sync.base);
	nv50_pioc_destroy(disp->core, &head->curs.base);
1256
	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1257 1258
	if (nv_crtc->cursor.nvbo)
		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1259 1260
	nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
	nouveau_bo_unmap(nv_crtc->lut.nvbo);
1261 1262
	if (nv_crtc->lut.nvbo)
		nouveau_bo_unpin(nv_crtc->lut.nvbo);
1263 1264 1265 1266 1267
	nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
	drm_crtc_cleanup(crtc);
	kfree(crtc);
}

1268 1269 1270 1271 1272 1273 1274 1275 1276
static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
	.dpms = nv50_crtc_dpms,
	.prepare = nv50_crtc_prepare,
	.commit = nv50_crtc_commit,
	.mode_fixup = nv50_crtc_mode_fixup,
	.mode_set = nv50_crtc_mode_set,
	.mode_set_base = nv50_crtc_mode_set_base,
	.mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
	.load_lut = nv50_crtc_lut_load,
1277 1278
};

1279 1280 1281 1282
static const struct drm_crtc_funcs nv50_crtc_func = {
	.cursor_set = nv50_crtc_cursor_set,
	.cursor_move = nv50_crtc_cursor_move,
	.gamma_set = nv50_crtc_gamma_set,
1283
	.set_config = drm_crtc_helper_set_config,
1284
	.destroy = nv50_crtc_destroy,
1285
	.page_flip = nouveau_crtc_page_flip,
1286 1287
};

1288
static void
1289
nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1290 1291 1292 1293
{
}

static void
1294
nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1295 1296 1297
{
}

1298
static int
1299
nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1300
{
1301 1302
	struct nv50_disp *disp = nv50_disp(dev);
	struct nv50_head *head;
1303 1304 1305
	struct drm_crtc *crtc;
	int ret, i;

1306 1307
	head = kzalloc(sizeof(*head), GFP_KERNEL);
	if (!head)
1308 1309
		return -ENOMEM;

1310
	head->base.index = index;
1311 1312 1313
	head->base.set_dither = nv50_crtc_set_dither;
	head->base.set_scale = nv50_crtc_set_scale;
	head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1314 1315
	head->base.color_vibrance = 50;
	head->base.vibrant_hue = 0;
1316 1317
	head->base.cursor.set_offset = nv50_cursor_set_offset;
	head->base.cursor.set_pos = nv50_cursor_set_pos;
1318
	for (i = 0; i < 256; i++) {
1319 1320 1321
		head->base.lut.r[i] = i << 8;
		head->base.lut.g[i] = i << 8;
		head->base.lut.b[i] = i << 8;
1322 1323
	}

1324
	crtc = &head->base.base;
1325 1326
	drm_crtc_init(dev, crtc, &nv50_crtc_func);
	drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1327 1328
	drm_mode_crtc_set_gamma_size(crtc, 256);

1329 1330 1331 1332
	ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
			     0, 0x0000, NULL, &head->base.lut.nvbo);
	if (!ret) {
		ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1333
		if (!ret) {
1334
			ret = nouveau_bo_map(head->base.lut.nvbo);
1335 1336 1337
			if (ret)
				nouveau_bo_unpin(head->base.lut.nvbo);
		}
1338 1339 1340 1341 1342 1343 1344
		if (ret)
			nouveau_bo_ref(NULL, &head->base.lut.nvbo);
	}

	if (ret)
		goto out;

1345
	nv50_crtc_lut_load(crtc);
1346 1347

	/* allocate cursor resources */
1348
	ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1349 1350 1351 1352 1353 1354 1355
			      &(struct nv50_display_curs_class) {
					.head = index,
			      }, sizeof(struct nv50_display_curs_class),
			      &head->curs.base);
	if (ret)
		goto out;

1356
	ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1357
			     0, 0x0000, NULL, &head->base.cursor.nvbo);
1358
	if (!ret) {
1359
		ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1360
		if (!ret) {
1361
			ret = nouveau_bo_map(head->base.cursor.nvbo);
1362 1363 1364
			if (ret)
				nouveau_bo_unpin(head->base.lut.nvbo);
		}
1365
		if (ret)
1366
			nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1367 1368 1369 1370 1371
	}

	if (ret)
		goto out;

1372
	/* allocate page flip / sync resources */
1373
	ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1374 1375 1376 1377 1378 1379 1380 1381 1382
			      &(struct nv50_display_sync_class) {
					.pushbuf = EVO_PUSH_HANDLE(SYNC, index),
					.head = index,
			      }, sizeof(struct nv50_display_sync_class),
			      disp->sync->bo.offset, &head->sync.base);
	if (ret)
		goto out;

	head->sync.sem.offset = EVO_SYNC(1 + index, 0x00);
1383

1384
	/* allocate overlay resources */
1385
	ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1386 1387 1388 1389
			      &(struct nv50_display_oimm_class) {
					.head = index,
			      }, sizeof(struct nv50_display_oimm_class),
			      &head->oimm.base);
1390 1391 1392
	if (ret)
		goto out;

1393
	ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1394 1395 1396 1397 1398 1399 1400
			      &(struct nv50_display_ovly_class) {
					.pushbuf = EVO_PUSH_HANDLE(OVLY, index),
					.head = index,
			      }, sizeof(struct nv50_display_ovly_class),
			      disp->sync->bo.offset, &head->ovly.base);
	if (ret)
		goto out;
1401 1402 1403

out:
	if (ret)
1404
		nv50_crtc_destroy(crtc);
1405 1406 1407
	return ret;
}

1408 1409 1410
/******************************************************************************
 * DAC
 *****************************************************************************/
1411
static void
1412
nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1413 1414
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1415
	struct nv50_disp *disp = nv50_disp(encoder->dev);
1416 1417 1418
	int or = nv_encoder->or;
	u32 dpms_ctrl;

1419
	dpms_ctrl = 0x00000000;
1420 1421 1422 1423 1424
	if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
		dpms_ctrl |= 0x00000001;
	if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
		dpms_ctrl |= 0x00000004;

1425
	nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1426 1427 1428
}

static bool
1429
nv50_dac_mode_fixup(struct drm_encoder *encoder,
1430
		    const struct drm_display_mode *mode,
1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448
		    struct drm_display_mode *adjusted_mode)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_connector *nv_connector;

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	if (nv_connector && nv_connector->native_mode) {
		if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
			int id = adjusted_mode->base.id;
			*adjusted_mode = *nv_connector->native_mode;
			adjusted_mode->base.id = id;
		}
	}

	return true;
}

static void
1449
nv50_dac_commit(struct drm_encoder *encoder)
1450 1451 1452 1453
{
}

static void
1454
nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1455 1456
		  struct drm_display_mode *adjusted_mode)
{
1457
	struct nv50_mast *mast = nv50_mast(encoder->dev);
1458 1459
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1460
	u32 *push;
1461

1462
	nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1463

1464
	push = evo_wait(mast, 8);
1465
	if (push) {
1466
		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496
			u32 syncs = 0x00000000;

			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
				syncs |= 0x00000001;
			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
				syncs |= 0x00000002;

			evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
			evo_data(push, 1 << nv_crtc->index);
			evo_data(push, syncs);
		} else {
			u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
			u32 syncs = 0x00000001;

			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
				syncs |= 0x00000008;
			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
				syncs |= 0x00000010;

			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
				magic |= 0x00000001;

			evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
			evo_data(push, syncs);
			evo_data(push, magic);
			evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
			evo_data(push, 1 << nv_crtc->index);
		}

		evo_kick(push, mast);
1497 1498 1499 1500 1501 1502
	}

	nv_encoder->crtc = encoder->crtc;
}

static void
1503
nv50_dac_disconnect(struct drm_encoder *encoder)
1504 1505
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1506
	struct nv50_mast *mast = nv50_mast(encoder->dev);
1507
	const int or = nv_encoder->or;
1508 1509 1510
	u32 *push;

	if (nv_encoder->crtc) {
1511
		nv50_crtc_prepare(nv_encoder->crtc);
1512

1513
		push = evo_wait(mast, 4);
1514
		if (push) {
1515
			if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1516 1517 1518 1519 1520 1521 1522
				evo_mthd(push, 0x0400 + (or * 0x080), 1);
				evo_data(push, 0x00000000);
			} else {
				evo_mthd(push, 0x0180 + (or * 0x020), 1);
				evo_data(push, 0x00000000);
			}
			evo_kick(push, mast);
1523 1524
		}
	}
1525 1526

	nv_encoder->crtc = NULL;
1527 1528
}

1529
static enum drm_connector_status
1530
nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1531
{
1532
	struct nv50_disp *disp = nv50_disp(encoder->dev);
1533
	int ret, or = nouveau_encoder(encoder)->or;
1534
	u32 load = 0;
Ben Skeggs's avatar
Ben Skeggs committed
1535

1536 1537 1538
	ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
	if (ret || load != 7)
		return connector_status_disconnected;
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Ben Skeggs committed
1539

1540
	return connector_status_connected;
1541 1542
}

1543
static void
1544
nv50_dac_destroy(struct drm_encoder *encoder)
1545 1546 1547 1548 1549
{
	drm_encoder_cleanup(encoder);
	kfree(encoder);
}

1550 1551 1552 1553 1554 1555 1556 1557 1558
static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
	.dpms = nv50_dac_dpms,
	.mode_fixup = nv50_dac_mode_fixup,
	.prepare = nv50_dac_disconnect,
	.commit = nv50_dac_commit,
	.mode_set = nv50_dac_mode_set,
	.disable = nv50_dac_disconnect,
	.get_crtc = nv50_display_crtc_get,
	.detect = nv50_dac_detect
1559 1560
};

1561 1562
static const struct drm_encoder_funcs nv50_dac_func = {
	.destroy = nv50_dac_destroy,
1563 1564 1565
};

static int
1566
nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1567
{
1568 1569
	struct nouveau_drm *drm = nouveau_drm(connector->dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1570 1571
	struct nouveau_encoder *nv_encoder;
	struct drm_encoder *encoder;
1572
	int type = DRM_MODE_ENCODER_DAC;
1573 1574 1575 1576 1577 1578

	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
	if (!nv_encoder)
		return -ENOMEM;
	nv_encoder->dcb = dcbe;
	nv_encoder->or = ffs(dcbe->or) - 1;
1579
	nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1580 1581 1582 1583

	encoder = to_drm_encoder(nv_encoder);
	encoder->possible_crtcs = dcbe->heads;
	encoder->possible_clones = 0;
1584
	drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1585
	drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1586 1587 1588 1589

	drm_mode_connector_attach_encoder(connector, encoder);
	return 0;
}
1590

1591 1592 1593 1594
/******************************************************************************
 * Audio
 *****************************************************************************/
static void
1595
nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1596 1597 1598
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_connector *nv_connector;
1599
	struct nv50_disp *disp = nv50_disp(encoder->dev);
1600 1601 1602 1603 1604 1605 1606

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	if (!drm_detect_monitor_audio(nv_connector->edid))
		return;

	drm_edid_to_eld(&nv_connector->base, nv_connector->edid);

1607 1608 1609
	nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
			    nv_connector->base.eld,
			    nv_connector->base.eld[2] * 4);
1610 1611 1612
}

static void
1613
nv50_audio_disconnect(struct drm_encoder *encoder)
1614 1615
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1616
	struct nv50_disp *disp = nv50_disp(encoder->dev);
1617

1618
	nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1619 1620 1621 1622 1623 1624
}

/******************************************************************************
 * HDMI
 *****************************************************************************/
static void
1625
nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1626
{
1627 1628 1629
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector;
1630
	struct nv50_disp *disp = nv50_disp(encoder->dev);
1631
	const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643
	u32 rekey = 56; /* binary driver, and tegra constant */
	u32 max_ac_packet;

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	if (!drm_detect_hdmi_monitor(nv_connector->edid))
		return;

	max_ac_packet  = mode->htotal - mode->hdisplay;
	max_ac_packet -= rekey;
	max_ac_packet -= 18; /* constant from tegra */
	max_ac_packet /= 32;

1644 1645 1646
	nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
			    NV84_DISP_SOR_HDMI_PWR_STATE_ON |
			    (max_ac_packet << 16) | rekey);
1647

1648
	nv50_audio_mode_set(encoder, mode);
1649 1650 1651
}

static void
1652
nv50_hdmi_disconnect(struct drm_encoder *encoder)
1653
{
1654 1655
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1656
	struct nv50_disp *disp = nv50_disp(encoder->dev);
1657
	const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1658

1659
	nv50_audio_disconnect(encoder);
1660

1661
	nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1662 1663
}

1664 1665 1666
/******************************************************************************
 * SOR
 *****************************************************************************/
1667
static void
1668
nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1669 1670 1671
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
1672
	struct nv50_disp *disp = nv50_disp(dev);
1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684
	struct drm_encoder *partner;
	int or = nv_encoder->or;

	nv_encoder->last_dpms = mode;

	list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
		struct nouveau_encoder *nv_partner = nouveau_encoder(partner);

		if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
			continue;

		if (nv_partner != nv_encoder &&
1685
		    nv_partner->dcb->or == nv_encoder->dcb->or) {
1686 1687 1688 1689 1690 1691
			if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
				return;
			break;
		}
	}

1692
	nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
1693 1694 1695
}

static bool
1696
nv50_sor_mode_fixup(struct drm_encoder *encoder,
1697
		    const struct drm_display_mode *mode,
1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714
		    struct drm_display_mode *adjusted_mode)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_connector *nv_connector;

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	if (nv_connector && nv_connector->native_mode) {
		if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
			int id = adjusted_mode->base.id;
			*adjusted_mode = *nv_connector->native_mode;
			adjusted_mode->base.id = id;
		}
	}

	return true;
}

1715
static void
1716
nv50_sor_disconnect(struct drm_encoder *encoder)
1717 1718
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1719
	struct nv50_mast *mast = nv50_mast(encoder->dev);
1720
	const int or = nv_encoder->or;
1721 1722 1723
	u32 *push;

	if (nv_encoder->crtc) {
1724
		nv50_crtc_prepare(nv_encoder->crtc);
1725

1726
		push = evo_wait(mast, 4);
1727
		if (push) {
1728
			if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1729 1730 1731 1732 1733 1734 1735
				evo_mthd(push, 0x0600 + (or * 0x40), 1);
				evo_data(push, 0x00000000);
			} else {
				evo_mthd(push, 0x0200 + (or * 0x20), 1);
				evo_data(push, 0x00000000);
			}
			evo_kick(push, mast);
1736 1737
		}

1738
		nv50_hdmi_disconnect(encoder);
1739
	}
1740 1741 1742

	nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
	nv_encoder->crtc = NULL;
1743 1744
}

1745
static void
1746
nv50_sor_commit(struct drm_encoder *encoder)
1747 1748 1749 1750
{
}

static void
1751
nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1752
		  struct drm_display_mode *mode)
1753
{
1754 1755
	struct nv50_disp *disp = nv50_disp(encoder->dev);
	struct nv50_mast *mast = nv50_mast(encoder->dev);
1756
	struct drm_device *dev = encoder->dev;
1757
	struct nouveau_drm *drm = nouveau_drm(dev);
1758 1759
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1760
	struct nouveau_connector *nv_connector;
1761
	struct nvbios *bios = &drm->vbios;
1762 1763 1764 1765
	u32 *push, lvds = 0;
	u8 owner = 1 << nv_crtc->index;
	u8 proto = 0xf;
	u8 depth = 0x0;
1766

1767 1768
	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	switch (nv_encoder->dcb->type) {
1769
	case DCB_OUTPUT_TMDS:
1770 1771
		if (nv_encoder->dcb->sorconf.link & 1) {
			if (mode->clock < 165000)
1772
				proto = 0x1;
1773
			else
1774
				proto = 0x5;
1775
		} else {
1776
			proto = 0x2;
1777 1778
		}

1779
		nv50_hdmi_mode_set(encoder, mode);
1780
		break;
1781
	case DCB_OUTPUT_LVDS:
1782 1783
		proto = 0x0;

1784 1785
		if (bios->fp_no_ddc) {
			if (bios->fp.dual_link)
1786
				lvds |= 0x0100;
1787
			if (bios->fp.if_is_24bit)
1788
				lvds |= 0x0200;
1789
		} else {
1790
			if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1791
				if (((u8 *)nv_connector->edid)[121] == 2)
1792
					lvds |= 0x0100;
1793 1794
			} else
			if (mode->clock >= bios->fp.duallink_transition_clk) {
1795
				lvds |= 0x0100;
1796
			}
1797

1798
			if (lvds & 0x0100) {
1799
				if (bios->fp.strapless_is_24bit & 2)
1800
					lvds |= 0x0200;
1801 1802
			} else {
				if (bios->fp.strapless_is_24bit & 1)
1803
					lvds |= 0x0200;
1804 1805 1806
			}

			if (nv_connector->base.display_info.bpc == 8)
1807
				lvds |= 0x0200;
1808
		}
1809

1810
		nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1811
		break;
1812
	case DCB_OUTPUT_DP:
1813
		if (nv_connector->base.display_info.bpc == 6) {
1814
			nv_encoder->dp.datarate = mode->clock * 18 / 8;
1815
			depth = 0x2;
1816 1817
		} else
		if (nv_connector->base.display_info.bpc == 8) {
1818
			nv_encoder->dp.datarate = mode->clock * 24 / 8;
1819
			depth = 0x5;
1820 1821 1822
		} else {
			nv_encoder->dp.datarate = mode->clock * 30 / 8;
			depth = 0x6;
1823
		}
1824 1825

		if (nv_encoder->dcb->sorconf.link & 1)
1826
			proto = 0x8;
1827
		else
1828
			proto = 0x9;
1829
		break;
1830 1831 1832 1833
	default:
		BUG_ON(1);
		break;
	}
1834

1835
	nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1836

1837
	push = evo_wait(nv50_mast(dev), 8);
1838
	if (push) {
1839
		if (nv50_vers(mast) < NVD0_DISP_CLASS) {
1840 1841 1842 1843 1844
			u32 ctrl = (depth << 16) | (proto << 8) | owner;
			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
				ctrl |= 0x00001000;
			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
				ctrl |= 0x00002000;
1845
			evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
1846
			evo_data(push, ctrl);
1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866
		} else {
			u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
			u32 syncs = 0x00000001;

			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
				syncs |= 0x00000008;
			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
				syncs |= 0x00000010;

			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
				magic |= 0x00000001;

			evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
			evo_data(push, syncs | (depth << 6));
			evo_data(push, magic);
			evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
			evo_data(push, owner | (proto << 8));
		}

		evo_kick(push, mast);
1867 1868 1869 1870 1871 1872
	}

	nv_encoder->crtc = encoder->crtc;
}

static void
1873
nv50_sor_destroy(struct drm_encoder *encoder)
1874 1875 1876 1877 1878
{
	drm_encoder_cleanup(encoder);
	kfree(encoder);
}

1879 1880 1881
static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
	.dpms = nv50_sor_dpms,
	.mode_fixup = nv50_sor_mode_fixup,
1882
	.prepare = nv50_sor_disconnect,
1883 1884 1885 1886
	.commit = nv50_sor_commit,
	.mode_set = nv50_sor_mode_set,
	.disable = nv50_sor_disconnect,
	.get_crtc = nv50_display_crtc_get,
1887 1888
};

1889 1890
static const struct drm_encoder_funcs nv50_sor_func = {
	.destroy = nv50_sor_destroy,
1891 1892 1893
};

static int
1894
nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1895
{
1896 1897
	struct nouveau_drm *drm = nouveau_drm(connector->dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1898 1899
	struct nouveau_encoder *nv_encoder;
	struct drm_encoder *encoder;
1900 1901 1902 1903 1904 1905 1906 1907 1908 1909
	int type;

	switch (dcbe->type) {
	case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
	case DCB_OUTPUT_TMDS:
	case DCB_OUTPUT_DP:
	default:
		type = DRM_MODE_ENCODER_TMDS;
		break;
	}
1910 1911 1912 1913 1914 1915

	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
	if (!nv_encoder)
		return -ENOMEM;
	nv_encoder->dcb = dcbe;
	nv_encoder->or = ffs(dcbe->or) - 1;
1916
	nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1917 1918 1919 1920 1921
	nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;

	encoder = to_drm_encoder(nv_encoder);
	encoder->possible_crtcs = dcbe->heads;
	encoder->possible_clones = 0;
1922
	drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
1923
	drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1924 1925 1926 1927

	drm_mode_connector_attach_encoder(connector, encoder);
	return 0;
}
1928

1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103
/******************************************************************************
 * PIOR
 *****************************************************************************/

static void
nv50_pior_dpms(struct drm_encoder *encoder, int mode)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nv50_disp *disp = nv50_disp(encoder->dev);
	u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
	u32 ctrl = (mode == DRM_MODE_DPMS_ON);
	nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
}

static bool
nv50_pior_mode_fixup(struct drm_encoder *encoder,
		     const struct drm_display_mode *mode,
		     struct drm_display_mode *adjusted_mode)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_connector *nv_connector;

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	if (nv_connector && nv_connector->native_mode) {
		if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
			int id = adjusted_mode->base.id;
			*adjusted_mode = *nv_connector->native_mode;
			adjusted_mode->base.id = id;
		}
	}

	adjusted_mode->clock *= 2;
	return true;
}

static void
nv50_pior_commit(struct drm_encoder *encoder)
{
}

static void
nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		   struct drm_display_mode *adjusted_mode)
{
	struct nv50_mast *mast = nv50_mast(encoder->dev);
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector;
	u8 owner = 1 << nv_crtc->index;
	u8 proto, depth;
	u32 *push;

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	switch (nv_connector->base.display_info.bpc) {
	case 10: depth = 0x6; break;
	case  8: depth = 0x5; break;
	case  6: depth = 0x2; break;
	default: depth = 0x0; break;
	}

	switch (nv_encoder->dcb->type) {
	case DCB_OUTPUT_TMDS:
	case DCB_OUTPUT_DP:
		proto = 0x0;
		break;
	default:
		BUG_ON(1);
		break;
	}

	nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);

	push = evo_wait(mast, 8);
	if (push) {
		if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
			u32 ctrl = (depth << 16) | (proto << 8) | owner;
			if (mode->flags & DRM_MODE_FLAG_NHSYNC)
				ctrl |= 0x00001000;
			if (mode->flags & DRM_MODE_FLAG_NVSYNC)
				ctrl |= 0x00002000;
			evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
			evo_data(push, ctrl);
		}

		evo_kick(push, mast);
	}

	nv_encoder->crtc = encoder->crtc;
}

static void
nv50_pior_disconnect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nv50_mast *mast = nv50_mast(encoder->dev);
	const int or = nv_encoder->or;
	u32 *push;

	if (nv_encoder->crtc) {
		nv50_crtc_prepare(nv_encoder->crtc);

		push = evo_wait(mast, 4);
		if (push) {
			if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
				evo_mthd(push, 0x0700 + (or * 0x040), 1);
				evo_data(push, 0x00000000);
			}
			evo_kick(push, mast);
		}
	}

	nv_encoder->crtc = NULL;
}

static void
nv50_pior_destroy(struct drm_encoder *encoder)
{
	drm_encoder_cleanup(encoder);
	kfree(encoder);
}

static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
	.dpms = nv50_pior_dpms,
	.mode_fixup = nv50_pior_mode_fixup,
	.prepare = nv50_pior_disconnect,
	.commit = nv50_pior_commit,
	.mode_set = nv50_pior_mode_set,
	.disable = nv50_pior_disconnect,
	.get_crtc = nv50_display_crtc_get,
};

static const struct drm_encoder_funcs nv50_pior_func = {
	.destroy = nv50_pior_destroy,
};

static int
nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
{
	struct nouveau_drm *drm = nouveau_drm(connector->dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_i2c_port *ddc = NULL;
	struct nouveau_encoder *nv_encoder;
	struct drm_encoder *encoder;
	int type;

	switch (dcbe->type) {
	case DCB_OUTPUT_TMDS:
		ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
		type = DRM_MODE_ENCODER_TMDS;
		break;
	case DCB_OUTPUT_DP:
		ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
		type = DRM_MODE_ENCODER_TMDS;
		break;
	default:
		return -ENODEV;
	}

	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
	if (!nv_encoder)
		return -ENOMEM;
	nv_encoder->dcb = dcbe;
	nv_encoder->or = ffs(dcbe->or) - 1;
	nv_encoder->i2c = ddc;

	encoder = to_drm_encoder(nv_encoder);
	encoder->possible_crtcs = dcbe->heads;
	encoder->possible_clones = 0;
	drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
	drm_encoder_helper_add(encoder, &nv50_pior_hfunc);

	drm_mode_connector_attach_encoder(connector, encoder);
	return 0;
}

2104 2105 2106
/******************************************************************************
 * Init
 *****************************************************************************/
2107
void
2108
nv50_display_fini(struct drm_device *dev)
2109 2110 2111 2112
{
}

int
2113
nv50_display_init(struct drm_device *dev)
2114
{
2115
	u32 *push = evo_wait(nv50_mast(dev), 32);
2116 2117 2118
	if (push) {
		evo_mthd(push, 0x0088, 1);
		evo_data(push, NvEvoSync);
2119
		evo_kick(push, nv50_mast(dev));
2120
		return 0;
2121
	}
2122

2123
	return -EBUSY;
2124 2125 2126
}

void
2127
nv50_display_destroy(struct drm_device *dev)
2128
{
2129
	struct nv50_disp *disp = nv50_disp(dev);
2130

2131
	nv50_dmac_destroy(disp->core, &disp->mast.base);
2132

2133
	nouveau_bo_unmap(disp->sync);
2134 2135
	if (disp->sync)
		nouveau_bo_unpin(disp->sync);
2136
	nouveau_bo_ref(NULL, &disp->sync);
2137

2138
	nouveau_display(dev)->priv = NULL;
2139 2140 2141 2142
	kfree(disp);
}

int
2143
nv50_display_create(struct drm_device *dev)
2144
{
2145 2146 2147
	static const u16 oclass[] = {
		NVE0_DISP_CLASS,
		NVD0_DISP_CLASS,
2148 2149 2150 2151 2152
		NVA3_DISP_CLASS,
		NV94_DISP_CLASS,
		NVA0_DISP_CLASS,
		NV84_DISP_CLASS,
		NV50_DISP_CLASS,
2153
	};
2154 2155 2156
	struct nouveau_device *device = nouveau_dev(dev);
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct dcb_table *dcb = &drm->vbios.dcb;
2157
	struct drm_connector *connector, *tmp;
2158
	struct nv50_disp *disp;
2159
	struct dcb_output *dcbe;
2160
	int crtcs, ret, i;
2161 2162 2163 2164

	disp = kzalloc(sizeof(*disp), GFP_KERNEL);
	if (!disp)
		return -ENOMEM;
2165 2166

	nouveau_display(dev)->priv = disp;
2167 2168 2169
	nouveau_display(dev)->dtor = nv50_display_destroy;
	nouveau_display(dev)->init = nv50_display_init;
	nouveau_display(dev)->fini = nv50_display_fini;
2170

2171 2172 2173 2174 2175
	/* small shared memory area we use for notifiers and semaphores */
	ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
			     0, 0x0000, NULL, &disp->sync);
	if (!ret) {
		ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2176
		if (!ret) {
2177
			ret = nouveau_bo_map(disp->sync);
2178 2179 2180
			if (ret)
				nouveau_bo_unpin(disp->sync);
		}
2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199
		if (ret)
			nouveau_bo_ref(NULL, &disp->sync);
	}

	if (ret)
		goto out;

	/* attempt to allocate a supported evo display class */
	ret = -ENODEV;
	for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
		ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
					 0xd1500000, oclass[i], NULL, 0,
					 &disp->core);
	}

	if (ret)
		goto out;

	/* allocate master evo channel */
2200
	ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
2201 2202 2203 2204 2205 2206 2207
			      &(struct nv50_display_mast_class) {
					.pushbuf = EVO_PUSH_HANDLE(MAST, 0),
			      }, sizeof(struct nv50_display_mast_class),
			      disp->sync->bo.offset, &disp->mast.base);
	if (ret)
		goto out;

2208
	/* create crtc objects to represent the hw heads */
2209 2210 2211 2212 2213
	if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
		crtcs = nv_rd32(device, 0x022448);
	else
		crtcs = 2;

2214
	for (i = 0; i < crtcs; i++) {
2215
		ret = nv50_crtc_create(dev, disp->core, i);
2216 2217 2218 2219
		if (ret)
			goto out;
	}

2220 2221 2222 2223 2224 2225
	/* create encoder/connector objects based on VBIOS DCB table */
	for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
		connector = nouveau_connector_create(dev, dcbe->connector);
		if (IS_ERR(connector))
			continue;

2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241
		if (dcbe->location == DCB_LOC_ON_CHIP) {
			switch (dcbe->type) {
			case DCB_OUTPUT_TMDS:
			case DCB_OUTPUT_LVDS:
			case DCB_OUTPUT_DP:
				ret = nv50_sor_create(connector, dcbe);
				break;
			case DCB_OUTPUT_ANALOG:
				ret = nv50_dac_create(connector, dcbe);
				break;
			default:
				ret = -ENODEV;
				break;
			}
		} else {
			ret = nv50_pior_create(connector, dcbe);
2242 2243
		}

2244 2245 2246 2247
		if (ret) {
			NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
				     dcbe->location, dcbe->type,
				     ffs(dcbe->or) - 1, ret);
2248 2249 2250 2251 2252 2253 2254 2255
		}
	}

	/* cull any connectors we created that don't have an encoder */
	list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
		if (connector->encoder_ids[0])
			continue;

2256
		NV_WARN(drm, "%s has no encoders, removing\n",
2257 2258 2259 2260
			drm_get_connector_name(connector));
		connector->funcs->destroy(connector);
	}

2261 2262
out:
	if (ret)
2263
		nv50_display_destroy(dev);
2264 2265
	return ret;
}