• Paulo Zanoni's avatar
    drm/i915: fix Haswell FDI link training code · 04945641
    Paulo Zanoni authored
    This commit makes hsw_fdi_link_train responsible for implementing
    everything described in the "Enable and train FDI" section from the
    Hawell CRT mode set sequence documentation. We completely rewrite
    hsw_fdi_link_train to match the documentation and we also call it in
    the right place.
    
    This patch was initially sent as a series of tiny patches fixing every
    little problem of the function, but since there were too many patches
    fixing the same function it got a little difficult to get the "big
    picture" of how the function would be in the end, so here we amended
    all the patches into a single big patch fixing the whole function.
    
    Problems we fixed:
    
      1 - Train Haswell FDI at the right time.
    
        We need to train the FDI before enabling the pipes and planes, so
        we're moving the call from lpt_pch_enable to haswell_crtc_enable
        directly.
    
        We are also removing ironlake_fdi_pll_enable since the PLL
        enablement on Haswell is completely different and is also done
        during the link training steps.
    
      2 - Use the right FDI_RX_CTL register on Haswell
    
        There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
        Using "pipe" here is wrong.
    
      3 - Don't rely on DDI_BUF_CTL previous values
    
        Just set the bits we want, everything else is zero. Also
        POSTING_READ the register before sleeping.
    
      4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
    
        According to the mode set sequence documentation, this is the
        right place. According to the FDI_RX_TUSIZE register description,
        this is the value we should set.
    
        Also remove the code that sets this register from the old
        location: lpt_pch_enable.
    
      5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
    
      6 - Wait only 35us for the FDI link training
    
        First we wait 30us for the FDI receiver lane calibration, then we
        wait 5us for the FDI auto training time.
    
      7 - Remove an useless indentation level on hsw_fdi_link_train
    
        We already "break" when the link training succeeds.
    
      8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
    
        When we fail the training.
    
      9 - Change Haswell FDI link training error messages
    
        We shouldn't call DRM_ERROR when still looping through voltage
        levels since this is expected and not really a failure. So in this
        commit we adjust the error path to only DRM_ERROR when we really
        fail after trying everything.
    
        While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
        it's what we use everywhere.
    
      10 - Try each voltage twice at hsw_fdi_link_train
    
        Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
    Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
    [danvet: Applied tiny bikesheds:
    - mention in comment that we test each voltage/emphasis level twice
    - realing arguments of the only untouched reg write, it spilled over
      the 80 char limit ...]
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    04945641
intel_ddi.c 38.3 KB