• Linus Torvalds's avatar
    Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc · 0890a264
    Linus Torvalds authored
    Pull ARC architecture updates from Vineet Gupta:
    
     - support for HS38 cores based on ARCv2 ISA
    
         ARCv2 is the next generation ISA from Synopsys and basis for the
         HS3{4,6,8} families of processors which retain the traditional ARC mantra of
         low power and configurability and are now more performant and feature rich.
    
         HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
         SMP (upto 4 cores) among other features.
    
         + www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
         + http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
         + http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps
    
     - support for ARC SDP (Software Development platform): Main Board + CPU Cards
        = AXS101: CPU Card with ARC700 in silicon @ 700 MHz
        = AXS103: CPU Card with HS38x in FPGA
    
     - refactoring of ARCompact port to accomodate new ARCv2 ISA
    
     - misc updates/cleanups
    
    * tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (72 commits)
      ARC: Fix build failures for ARCompact in linux-next after ARCv2 support
      ARCv2: Allow older gcc to cope with new regime of ARCv2/ARCompact support
      ARCv2: [vdk] dts files and defconfig for HS38 VDK
      ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores
      ARC: [axs101] Prepare for AXS103
      ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores
      ARCv2: All bits in place, allow ARCv2 builds
      ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
      ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock
      ARC: Reduce bitops lines of code using macros
      ARCv2: barriers
      arch: conditionally define smp_{mb,rmb,wmb}
      ARC: add smp barriers around atomics per Documentation/atomic_ops.txt
      ARC: add compiler barrier to LLSC based cmpxchg
      ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution
      ARCv2: SMP: clocksource: Enable Global Real Time counter
      ARCv2: SMP: ARConnect debug/robustness
      ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al
      ARC: make plat_smp_ops weak to allow over-rides
      ARCv2: clocksource: Introduce 64bit local RTC counter
      ...
    0890a264
barrier.h 2.38 KB