• Heiko Stuebner's avatar
    clk: rockchip: add optional sync to pll rate parameters · 0bb66d3b
    Heiko Stuebner authored
    In some cases firmware brings up plls with different parameters than the ones
    noted in the rate table for the specific frequency. These firmware-selected
    parameters are worse than the tested ones in the pll rate tables but cannot
    be changed by a simple clk_set_rate call when the rate stays the same.
    
    Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback
    that checks the runtime-parameters against the matching rate table entry
    and adjusts them to the table-ones if necessary.
    
    If no rate table is set or the current rate does not match any rate-table
    entry no changes are made.
    
    Being able to limit this adjustment to specific plls is necessary to not
    touch the ones supplying core components like the apll and dpll supplying
    the armcores and dram.
    Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
    Reviewed-by: default avatarKever Yang <kever.yang@rock-chips.com>
    Tested-by: default avatarKever Yang <kever.yang@rock-chips.com>
    0bb66d3b
clk.h 10.8 KB