• Nikola Cornij's avatar
    drm/amd/display: Set DSC before DIG front-end is connected to its back-end · 1a9e3d45
    Nikola Cornij authored
    [why]
    At the time DIG FE is connected to its BE, the clocks in OTG are enabled and
    PHY will also be set up. When DSC has to be used to fit the stream into the
    available bandwidth, without DSC being set DIG could get exposed to the
    higer bandwidth it (or link) could handle. This causes the HW to "reject"
    video enable setup (the register shows that video enable was attempted, but
    the status bit shows it as disabled).
    
    [how]
    - Separate DSC setup into DSC register config and DSC PPS SDP setup
    
    - Move most of the DSC setup (register config) to before
      dcn10_link_encoder_connect_dig_be_to_fe() is  called
    
    - Set up DSC PPS SDP after DIG FE is connected to its BE. This is because
      setting DSC PPS SDP before that has no effect.
    Signed-off-by: default avatarNikola Cornij <nikola.cornij@amd.com>
    Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
    Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
    Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
    1a9e3d45
dcn20_dsc.c 29.2 KB