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Dongxiao Xu authored
Host software could issue interrupts to ME firmware, using H_IG bit. While Setting H_IG bit, host software should preserve all the other bits in H_CSR unchanged. In the original function which sets H_CSR register, they first read the register, then set some bits, and write the whole 32bits back to the register. And that the special behavior of H_IS (write-one-to-zero) causes problem. This patch fixes the issue in the following ways: - Modify heci_set_csr_register() function so that it doesn't change H_IS bit. - Add interface heci_csr_clear_his() to clear H_IS bit. This function is called after H_IS checking (dev->host_hw_state & H_IS == H_IS). - In original heci_csr_disable_interrupts() function, it not only clears H_IE bit, sometimes it also clears H_IS bit. This patch separates the two parts. - Avoid calling write_heci_register() function to set H_CSR register directly, and instead using heci_set_csr_register() function Signed-off-by:
Dongxiao Xu <dongxiao.xu@intel.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de>
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