The power button (SW2) on Odroid XU3/4 is connected to the PWRON pin
of the S2MPS11 PMIC.

The S2MPS11 datasheet says that ONOB pin operates as 'PWRON key active
low signal'. In fact, S2MPS11 PMIC acts as a 16ms debouce filter and
signal inverter, thus effectively repeating PWRON (active high) to ONOB
pin (active low).

ONOB PMIC pin is then connected to XEINT3 SoC pin, so we get the state
of the power button on the gpx0-3 GPIO.

This patch adds device-tree bindings for the power button of Odroid
XU3/4 boards.
Signed-off-by: Brian Kim <brian.kim@hardkernel.com>
[mszyprow: extended commit message, added comments and fixed minor
 issues in the dts]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>