• Paul Walmsley's avatar
    OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz · 4519c2bf
    Paul Walmsley authored
    According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
    DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
    clock frequency from 83MHz to 166MHz.  CDP code unconditionally
    unlocked the DLL whenever shifting to a lower SDRC speed, but this
    seems unnecessary and error-prone, as the DLL is no longer able to
    compensate for process, voltage, and temperature variations.  Instead,
    only unlock the DLL when the SDRC clock rate would be less than 83MHz.
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    4519c2bf
sram.h 2.28 KB