• Catalin Marinas's avatar
    Fix the VFP handling on the Feroceon CPU · 85d6943a
    Catalin Marinas authored
    This CPU generates synchronous VFP exceptions in a non-standard way -
    the FPEXC.EX bit set but without the FPSCR.IXE bit being set like in the
    VFP subarchitecture 1 or just the FPEXC.DEX bit like in VFP
    subarchitecture 2. The main problem is that the faulty instruction
    (which needs to be emulated in software) will be restarted several times
    (normally until a context switch disables the VFP). This patch ensures
    that the VFP exception is treated as synchronous.
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Cc: Nicolas Pitre <nico@cam.org>
    85d6943a
vfphw.S 7.01 KB