• Vandana Kannan's avatar
    drm/i915/gen9: Add 2us read latency to WM level · 367294be
    Vandana Kannan authored
    According to the updated Bspec, The mailbox response data is not currently
    accounting for memory read latency. Add 2 microseconds to the result for
    each level.
    This patch adds 2us to latency of level 0 for all cases and
    for all other levels (1-7) only if latency[level] > 0.
    
    v2: Slightly rework the patch and add a big comment (Damien)
    v3: Rebase on top of the renames of the memory latency defines
    
    Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v1)
    Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
    Reviewed-by: M, Satheeshakrishna <satheeshakrishna.m@intel.com> (v1)
    Cc: Lespiau, Damien <damien.lespiau@intel.com>
    Cc: M, Satheeshakrishna <satheeshakrishna.m@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    367294be
intel_pm.c 199 KB