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Jim Quinlan authored
Older BrcmSTB chips do not have a separate register for MSI interrupts; the MSIs are in a register that also contains unrelated interrupts. In addition, the interrupts lie in bits [31..24] for these legacy chips. This commit provides common code for both legacy and non-legacy MSI interrupt registers. Link: https://lore.kernel.org/r/20200911175232.19016-9-james.quinlan@broadcom.comSigned-off-by:
Jim Quinlan <jquinlan@broadcom.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by:
Rob Herring <robh@kernel.org> Acked-by:
Florian Fainelli <f.fainelli@gmail.com>
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