The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack

    [MIPS] Hack for SB1 cache issues

    Removing flush_icache_page a while ago broke SB1 which was using an empty
    flush_data_cache_page function.  This glues things well enough so a more
    efficient but also more intrusive solution can be found later.
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

in the hope it was no longer needed.  As it turns it still is so resurrect
it until there is a better solution.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>