• Magnus Damm's avatar
    irqchip: Renesas INTC External IRQ pin driver · 44358048
    Magnus Damm authored
    This patch adds a driver for external IRQ pins connected
    to the INTC block on recent SoCs from Renesas.
    
    The INTC hardware block usually contains a rather wide
    range of features ranging from external IRQ pin handling
    to legacy interrupt controller support. On older SoCs
    the INTC is used as a general purpose interrupt controller
    both for external IRQ pins and on-chip devices.
    
    On more recent ARM based SoCs with Cortex-A9 the main
    interrupt controller is the GIC, but IRQ trigger setup
    still need to happen in the INTC hardware block.
    
    This driver implements the glue code needed to configure
    IRQ trigger and also handle mask/unmask and demux of
    external IRQ pins hooked up from the INTC to the GIC.
    
    Tested on sh73a0 and r8a7779. The hardware varies quite
    a bit with SoC model, for instance register width and
    bitfield widths vary wildly. The driver requires one GIC
    SPI per external IRQ pin to operate.  Each driver instance
    will handle up to 8 external IRQ pins.
    
    The SoCs using this driver are currently mainly used
    together with regular platform devices so this driver
    allows configuration via platform data to support things
    like static interrupt base address. DT support will
    be added incrementally in the not so distant future.
    Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
    Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
    Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
    44358048
irq-renesas-intc-irqpin.c 12.5 KB