• Alex Deucher's avatar
    drm/radeon: fixes for gfx clockgating on SI · 5594a558
    Alex Deucher authored
    Clockgating requires signalling between the CP and the
    RLC to work properly.  Resetting the CP block in the
    CP resume code messed up the internal coordination
    between the blocks.  Removing the reset allows gfx
    clockgating to work properly.  However, when gfx clock
    gating is enabled, there is a strange interaction with
    dpm which causes the chip to stay in the high performance
    level all the time, so leave gfx clockgating disabled
    for now.
    Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
    5594a558
si.c 198 KB