• Lin Huang's avatar
    clk: rockchip: add new clock-type for the ddrclk · a4f182bf
    Lin Huang authored
    Changing the rate of the DDR clock needs special care, as the DDR
    is of course in use and will react badly if the rate changes under it.
    
    Over time different approaches to handle that were used.
    
    Past SoCs like the rk3288 and before would store some code in SRAM
    while the rk3368 used a SCPI variant and let a coprocessor handle that.
    
    New rockchip platforms like the rk3399 have a dcf controller to do ddr
    frequency scaling, and support for this controller will be implemented
    in the arm-trusted-firmware.
    
    This new clock-type should over time handle all these methods for
    handling DDR rate changes, but right now it will concentrate on the
    SIP interface used to talk to ARM trusted firmware.
    
    The SIP interface counterpart was merged from pull-request #684 [0]
    into the upstream arm-trusted-firmware codebase.
    
    [0] https://github.com/ARM-software/arm-trusted-firmware/pull/684Signed-off-by: default avatarLin Huang <hl@rock-chips.com>
    Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
    a4f182bf
clk.c 15.2 KB