• Aneesh Kumar K.V's avatar
    mm: Use ptep/pmdp_set_numa() for updating _PAGE_NUMA bit · 56eecdb9
    Aneesh Kumar K.V authored
    Archs like ppc64 doesn't do tlb flush in set_pte/pmd functions when using
    a hash table MMU for various reasons (the flush is handled as part of
    the PTE modification when necessary).
    
    ppc64 thus doesn't implement flush_tlb_range for hash based MMUs.
    
    Additionally ppc64 require the tlb flushing to be batched within ptl locks.
    
    The reason to do that is to ensure that the hash page table is in sync with
    linux page table.
    
    We track the hpte index in linux pte and if we clear them without flushing
    hash and drop the ptl lock, we can have another cpu update the pte and can
    end up with duplicate entry in the hash table, which is fatal.
    
    We also want to keep set_pte_at simpler by not requiring them to do hash
    flush for performance reason. We do that by assuming that set_pte_at() is
    never *ever* called on a PTE that is already valid.
    
    This was the case until the NUMA code went in which broke that assumption.
    
    Fix that by introducing a new pair of helpers to set _PAGE_NUMA in a
    way similar to ptep/pmdp_set_wrprotect(), with a generic implementation
    using set_pte_at() and a powerpc specific one using the appropriate
    mechanism needed to keep the hash table in sync.
    Acked-by: default avatarMel Gorman <mgorman@suse.de>
    Reviewed-by: default avatarRik van Riel <riel@redhat.com>
    Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
    Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
    56eecdb9
huge_memory.c 77.7 KB