• Jan Remmet's avatar
    regulator: tps65910: Work around silicon erratum SWCZ010 · 8f9165c9
    Jan Remmet authored
    http://www.ti.com/lit/pdf/SWCZ010:
      DCDC o/p voltage can go higher than programmed value
    
    Impact:
    VDDI, VDD2, and VIO output programmed voltage level can go higher than
    expected or crash, when coming out of PFM to PWM mode or using DVFS.
    
    Description:
    When DCDC CLK SYNC bits are 11/01:
    * VIO 3-MHz oscillator is the source clock of the digital core and input
      clock of VDD1 and VDD2
    * Turn-on of VDD1 and VDD2 HSD PFETis synchronized or at a constant
      phase shift
    * Current pulled though VCC1+VCC2 is Iload(VDD1) + Iload(VDD2)
    * The 3 HSD PFET will be turned-on at the same time, causing the highest
      possible switching noise on the application. This noise level depends
      on the layout, the VBAT level, and the load current. The noise level
      increases with improper layout.
    
    When DCDC CLK SYNC bits are 00:
    * VIO 3-MHz oscillator is the source clock of digital core
    * VDD1 and VDD2 are running on their own 3-MHz oscillator
    * Current pulled though VCC1+VCC2 average of Iload(VDD1) + Iload(VDD2)
    * The switching noise of the 3 SMPS will be randomly spread over time,
      causing lower overall switching noise.
    
    Workaround:
    Set DCDCCTRL_REG[1:0]= 00.
    Signed-off-by: default avatarJan Remmet <j.remmet@phytec.de>
    Signed-off-by: default avatarMark Brown <broonie@kernel.org>
    Cc: stable@vger.kernel.org
    8f9165c9
tps65910-regulator.c 33 KB