• Marc Zyngier's avatar
    irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn · 33625282
    Marc Zyngier authored
    We would like to reset the Group-0 Active Priority Registers
    at boot time if they are available to us. They would be available
    if SCR_EL3.FIQ was not set, but we cannot directly probe this bit,
    and short of checking, we may end-up trapping to EL3, and the
    firmware may not be please to get such an exception. Yes, this
    is dumb.
    
    Instead, let's use PMR to find out if its value gets affected by
    SCR_EL3.FIQ being set. We use the fact that when SCR_EL3.FIQ is
    set, the LSB of the priority is lost due to the shifting back and
    forth of the actual priority. If we read back a 0, we know that
    Group0 is unavailable. In case we read a non-zero value, we can
    safely reset the AP0Rn register.
    Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    33625282
arch_gicv3.h 9.72 KB